drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <ethdev_driver.h>
   9 #include <ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    3
  31 #define DRV_MODULE_VER_SUBMINOR 0
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) RTE_DIM(x)
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  55
  56 enum ethtool_stringset {
  57         ETH_SS_TEST             = 0,
  58         ETH_SS_STATS,
  59 };
  60
  61 struct ena_stats {
  62         char name[ETH_GSTRING_LEN];
  63         int stat_offset;
  64 };
  65
  66 #define ENA_STAT_ENTRY(stat, stat_type) { \
  67         .name = #stat, \
  68         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  69 }
  70
  71 #define ENA_STAT_RX_ENTRY(stat) \
  72         ENA_STAT_ENTRY(stat, rx)
  73
  74 #define ENA_STAT_TX_ENTRY(stat) \
  75         ENA_STAT_ENTRY(stat, tx)
  76
  77 #define ENA_STAT_ENI_ENTRY(stat) \
  78         ENA_STAT_ENTRY(stat, eni)
  79
  80 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  81         ENA_STAT_ENTRY(stat, dev)
  82
  83 /* Device arguments */
  84 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  85
  86 /*
  87  * Each rte_memzone should have unique name.
  88  * To satisfy it, count number of allocation and add it to name.
  89  */
  90 rte_atomic64_t ena_alloc_cnt;
  91
  92 static const struct ena_stats ena_stats_global_strings[] = {
  93         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  94         ENA_STAT_GLOBAL_ENTRY(dev_start),
  95         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  96         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  97 };
  98
  99 static const struct ena_stats ena_stats_eni_strings[] = {
 100         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
 101         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
 102         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
 103         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
 104         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
 105 };
 106
 107 static const struct ena_stats ena_stats_tx_strings[] = {
 108         ENA_STAT_TX_ENTRY(cnt),
 109         ENA_STAT_TX_ENTRY(bytes),
 110         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 111         ENA_STAT_TX_ENTRY(linearize),
 112         ENA_STAT_TX_ENTRY(linearize_failed),
 113         ENA_STAT_TX_ENTRY(tx_poll),
 114         ENA_STAT_TX_ENTRY(doorbells),
 115         ENA_STAT_TX_ENTRY(bad_req_id),
 116         ENA_STAT_TX_ENTRY(available_desc),
 117 };
 118
 119 static const struct ena_stats ena_stats_rx_strings[] = {
 120         ENA_STAT_RX_ENTRY(cnt),
 121         ENA_STAT_RX_ENTRY(bytes),
 122         ENA_STAT_RX_ENTRY(refill_partial),
 123         ENA_STAT_RX_ENTRY(bad_csum),
 124         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 125         ENA_STAT_RX_ENTRY(bad_desc_num),
 126         ENA_STAT_RX_ENTRY(bad_req_id),
 127 };
 128
 129 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 130 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 131 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 132 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 133
 134 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 135                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 136                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 137                         DEV_TX_OFFLOAD_TCP_TSO)
 138 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 139                        PKT_TX_IP_CKSUM |\
 140                        PKT_TX_TCP_SEG)
 141
 142 /** Vendor ID used by Amazon devices */
 143 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 144 /** Amazon devices */
 145 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 146 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 147
 148 #define ENA_TX_OFFLOAD_MASK     (\
 149         PKT_TX_L4_MASK |         \
 150         PKT_TX_IPV6 |            \
 151         PKT_TX_IPV4 |            \
 152         PKT_TX_IP_CKSUM |        \
 153         PKT_TX_TCP_SEG)
 154
 155 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 156         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 157
 158 static const struct rte_pci_id pci_id_ena_map[] = {
 159         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 160         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 161         { .device_id = 0 },
 162 };
 163
 164 static struct ena_aenq_handlers aenq_handlers;
 165
 166 static int ena_device_init(struct ena_com_dev *ena_dev,
 167                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 168                            bool *wd_state);
 169 static int ena_dev_configure(struct rte_eth_dev *dev);
 170 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 171         struct ena_tx_buffer *tx_info,
 172         struct rte_mbuf *mbuf,
 173         void **push_header,
 174         uint16_t *header_len);
 175 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 176 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 177 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 178                                   uint16_t nb_pkts);
 179 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 180                 uint16_t nb_pkts);
 181 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 182                               uint16_t nb_desc, unsigned int socket_id,
 183                               const struct rte_eth_txconf *tx_conf);
 184 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 185                               uint16_t nb_desc, unsigned int socket_id,
 186                               const struct rte_eth_rxconf *rx_conf,
 187                               struct rte_mempool *mp);
 188 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 189 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 190                                     struct ena_com_rx_buf_info *ena_bufs,
 191                                     uint32_t descs,
 192                                     uint16_t *next_to_clean,
 193                                     uint8_t offset);
 194 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 195                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 196 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 197                                   struct rte_mbuf *mbuf, uint16_t id);
 198 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 199 static void ena_init_rings(struct ena_adapter *adapter,
 200                            bool disable_meta_caching);
 201 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202 static int ena_start(struct rte_eth_dev *dev);
 203 static int ena_stop(struct rte_eth_dev *dev);
 204 static int ena_close(struct rte_eth_dev *dev);
 205 static int ena_dev_reset(struct rte_eth_dev *dev);
 206 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 207 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 208 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 209 static void ena_rx_queue_release(void *queue);
 210 static void ena_tx_queue_release(void *queue);
 211 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 212 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 213 static int ena_link_update(struct rte_eth_dev *dev,
 214                            int wait_to_complete);
 215 static int ena_create_io_queue(struct ena_ring *ring);
 216 static void ena_queue_stop(struct ena_ring *ring);
 217 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 218                               enum ena_ring_type ring_type);
 219 static int ena_queue_start(struct ena_ring *ring);
 220 static int ena_queue_start_all(struct rte_eth_dev *dev,
 221                                enum ena_ring_type ring_type);
 222 static void ena_stats_restart(struct rte_eth_dev *dev);
 223 static int ena_infos_get(struct rte_eth_dev *dev,
 224                          struct rte_eth_dev_info *dev_info);
 225 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 226                                struct rte_eth_rss_reta_entry64 *reta_conf,
 227                                uint16_t reta_size);
 228 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 229                               struct rte_eth_rss_reta_entry64 *reta_conf,
 230                               uint16_t reta_size);
 231 static void ena_interrupt_handler_rte(void *cb_arg);
 232 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 233 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 234 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 235 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 236                                 struct rte_eth_xstat_name *xstats_names,
 237                                 unsigned int n);
 238 static int ena_xstats_get(struct rte_eth_dev *dev,
 239                           struct rte_eth_xstat *stats,
 240                           unsigned int n);
 241 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 242                                 const uint64_t *ids,
 243                                 uint64_t *values,
 244                                 unsigned int n);
 245 static int ena_process_bool_devarg(const char *key,
 246                                    const char *value,
 247                                    void *opaque);
 248 static int ena_parse_devargs(struct ena_adapter *adapter,
 249                              struct rte_devargs *devargs);
 250 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 251
 252 static const struct eth_dev_ops ena_dev_ops = {
 253         .dev_configure        = ena_dev_configure,
 254         .dev_infos_get        = ena_infos_get,
 255         .rx_queue_setup       = ena_rx_queue_setup,
 256         .tx_queue_setup       = ena_tx_queue_setup,
 257         .dev_start            = ena_start,
 258         .dev_stop             = ena_stop,
 259         .link_update          = ena_link_update,
 260         .stats_get            = ena_stats_get,
 261         .xstats_get_names     = ena_xstats_get_names,
 262         .xstats_get           = ena_xstats_get,
 263         .xstats_get_by_id     = ena_xstats_get_by_id,
 264         .mtu_set              = ena_mtu_set,
 265         .rx_queue_release     = ena_rx_queue_release,
 266         .tx_queue_release     = ena_tx_queue_release,
 267         .dev_close            = ena_close,
 268         .dev_reset            = ena_dev_reset,
 269         .reta_update          = ena_rss_reta_update,
 270         .reta_query           = ena_rss_reta_query,
 271 };
 272
 273 void ena_rss_key_fill(void *key, size_t size)
 274 {
 275         static bool key_generated;
 276         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 277         size_t i;
 278
 279         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 280
 281         if (!key_generated) {
 282                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 283                         default_key[i] = rte_rand() & 0xff;
 284                 key_generated = true;
 285         }
 286
 287         rte_memcpy(key, default_key, size);
 288 }
 289
 290 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 291                                        struct ena_com_rx_ctx *ena_rx_ctx)
 292 {
 293         uint64_t ol_flags = 0;
 294         uint32_t packet_type = 0;
 295
 296         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 297                 packet_type |= RTE_PTYPE_L4_TCP;
 298         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 299                 packet_type |= RTE_PTYPE_L4_UDP;
 300
 301         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 302                 packet_type |= RTE_PTYPE_L3_IPV4;
 303                 if (unlikely(ena_rx_ctx->l3_csum_err))
 304                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
 305                 else
 306                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 307         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 308                 packet_type |= RTE_PTYPE_L3_IPV6;
 309         }
 310
 311         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 312                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 313         else
 314                 if (unlikely(ena_rx_ctx->l4_csum_err))
 315                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 316                 else
 317                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 318
 319         if (likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 320                 ol_flags |= PKT_RX_RSS_HASH;
 321                 mbuf->hash.rss = ena_rx_ctx->hash;
 322         }
 323
 324         mbuf->ol_flags = ol_flags;
 325         mbuf->packet_type = packet_type;
 326 }
 327
 328 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 329                                        struct ena_com_tx_ctx *ena_tx_ctx,
 330                                        uint64_t queue_offloads,
 331                                        bool disable_meta_caching)
 332 {
 333         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 334
 335         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 336             (queue_offloads & QUEUE_OFFLOADS)) {
 337                 /* check if TSO is required */
 338                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 339                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 340                         ena_tx_ctx->tso_enable = true;
 341
 342                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 343                 }
 344
 345                 /* check if L3 checksum is needed */
 346                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 347                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 348                         ena_tx_ctx->l3_csum_enable = true;
 349
 350                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 351                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 352                 } else {
 353                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 354
 355                         /* set don't fragment (DF) flag */
 356                         if (mbuf->packet_type &
 357                                 (RTE_PTYPE_L4_NONFRAG
 358                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 359                                 ena_tx_ctx->df = true;
 360                 }
 361
 362                 /* check if L4 checksum is needed */
 363                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 364                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 365                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 366                         ena_tx_ctx->l4_csum_enable = true;
 367                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 368                                 PKT_TX_UDP_CKSUM) &&
 369                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 370                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 371                         ena_tx_ctx->l4_csum_enable = true;
 372                 } else {
 373                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 374                         ena_tx_ctx->l4_csum_enable = false;
 375                 }
 376
 377                 ena_meta->mss = mbuf->tso_segsz;
 378                 ena_meta->l3_hdr_len = mbuf->l3_len;
 379                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 380
 381                 ena_tx_ctx->meta_valid = true;
 382         } else if (disable_meta_caching) {
 383                 memset(ena_meta, 0, sizeof(*ena_meta));
 384                 ena_tx_ctx->meta_valid = true;
 385         } else {
 386                 ena_tx_ctx->meta_valid = false;
 387         }
 388 }
 389
 390 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 391 {
 392         struct ena_tx_buffer *tx_info = NULL;
 393
 394         if (likely(req_id < tx_ring->ring_size)) {
 395                 tx_info = &tx_ring->tx_buffer_info[req_id];
 396                 if (likely(tx_info->mbuf))
 397                         return 0;
 398         }
 399
 400         if (tx_info)
 401                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 402         else
 403                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 404
 405         /* Trigger device reset */
 406         ++tx_ring->tx_stats.bad_req_id;
 407         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 408         tx_ring->adapter->trigger_reset = true;
 409         return -EFAULT;
 410 }
 411
 412 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 413 {
 414         struct ena_admin_host_info *host_info;
 415         int rc;
 416
 417         /* Allocate only the host info */
 418         rc = ena_com_allocate_host_info(ena_dev);
 419         if (rc) {
 420                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 421                 return;
 422         }
 423
 424         host_info = ena_dev->host_attr.host_info;
 425
 426         host_info->os_type = ENA_ADMIN_OS_DPDK;
 427         host_info->kernel_ver = RTE_VERSION;
 428         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 429                 sizeof(host_info->kernel_ver_str));
 430         host_info->os_dist = RTE_VERSION;
 431         strlcpy((char *)host_info->os_dist_str, rte_version(),
 432                 sizeof(host_info->os_dist_str));
 433         host_info->driver_version =
 434                 (DRV_MODULE_VER_MAJOR) |
 435                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 436                 (DRV_MODULE_VER_SUBMINOR <<
 437                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 438         host_info->num_cpus = rte_lcore_count();
 439
 440         host_info->driver_supported_features =
 441                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 442
 443         rc = ena_com_set_host_attributes(ena_dev);
 444         if (rc) {
 445                 if (rc == -ENA_COM_UNSUPPORTED)
 446                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 447                 else
 448                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 449
 450                 goto err;
 451         }
 452
 453         return;
 454
 455 err:
 456         ena_com_delete_host_info(ena_dev);
 457 }
 458
 459 /* This function calculates the number of xstats based on the current config */
 460 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 461 {
 462         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 463                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 464                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 465 }
 466
 467 static void ena_config_debug_area(struct ena_adapter *adapter)
 468 {
 469         u32 debug_area_size;
 470         int rc, ss_count;
 471
 472         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 473
 474         /* allocate 32 bytes for each string and 64bit for the value */
 475         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 476
 477         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 478         if (rc) {
 479                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 480                 return;
 481         }
 482
 483         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 484         if (rc) {
 485                 if (rc == -ENA_COM_UNSUPPORTED)
 486                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 487                 else
 488                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 489
 490                 goto err;
 491         }
 492
 493         return;
 494 err:
 495         ena_com_delete_debug_area(&adapter->ena_dev);
 496 }
 497
 498 static int ena_close(struct rte_eth_dev *dev)
 499 {
 500         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 501         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 502         struct ena_adapter *adapter = dev->data->dev_private;
 503         int ret = 0;
 504
 505         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 506                 return 0;
 507
 508         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 509                 ret = ena_stop(dev);
 510         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 511
 512         ena_rx_queue_release_all(dev);
 513         ena_tx_queue_release_all(dev);
 514
 515         rte_free(adapter->drv_stats);
 516         adapter->drv_stats = NULL;
 517
 518         rte_intr_disable(intr_handle);
 519         rte_intr_callback_unregister(intr_handle,
 520                                      ena_interrupt_handler_rte,
 521                                      adapter);
 522
 523         /*
 524          * MAC is not allocated dynamically. Setting NULL should prevent from
 525          * release of the resource in the rte_eth_dev_release_port().
 526          */
 527         dev->data->mac_addrs = NULL;
 528
 529         return ret;
 530 }
 531
 532 static int
 533 ena_dev_reset(struct rte_eth_dev *dev)
 534 {
 535         int rc = 0;
 536
 537         ena_destroy_device(dev);
 538         rc = eth_ena_dev_init(dev);
 539         if (rc)
 540                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 541
 542         return rc;
 543 }
 544
 545 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 546                                struct rte_eth_rss_reta_entry64 *reta_conf,
 547                                uint16_t reta_size)
 548 {
 549         struct ena_adapter *adapter = dev->data->dev_private;
 550         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 551         int rc, i;
 552         u16 entry_value;
 553         int conf_idx;
 554         int idx;
 555
 556         if ((reta_size == 0) || (reta_conf == NULL))
 557                 return -EINVAL;
 558
 559         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 560                 PMD_DRV_LOG(WARNING,
 561                         "indirection table %d is bigger than supported (%d)\n",
 562                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 563                 return -EINVAL;
 564         }
 565
 566         for (i = 0 ; i < reta_size ; i++) {
 567                 /* each reta_conf is for 64 entries.
 568                  * to support 128 we use 2 conf of 64
 569                  */
 570                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 571                 idx = i % RTE_RETA_GROUP_SIZE;
 572                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 573                         entry_value =
 574                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 575
 576                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 577                                                                i,
 578                                                                entry_value);
 579                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 580                                 PMD_DRV_LOG(ERR,
 581                                         "Cannot fill indirect table\n");
 582                                 return rc;
 583                         }
 584                 }
 585         }
 586
 587         rte_spinlock_lock(&adapter->admin_lock);
 588         rc = ena_com_indirect_table_set(ena_dev);
 589         rte_spinlock_unlock(&adapter->admin_lock);
 590         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 591                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 592                 return rc;
 593         }
 594
 595         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 596                 __func__, reta_size, adapter->rte_dev->data->port_id);
 597
 598         return 0;
 599 }
 600
 601 /* Query redirection table. */
 602 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 603                               struct rte_eth_rss_reta_entry64 *reta_conf,
 604                               uint16_t reta_size)
 605 {
 606         struct ena_adapter *adapter = dev->data->dev_private;
 607         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 608         int rc;
 609         int i;
 610         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 611         int reta_conf_idx;
 612         int reta_idx;
 613
 614         if (reta_size == 0 || reta_conf == NULL ||
 615             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 616                 return -EINVAL;
 617
 618         rte_spinlock_lock(&adapter->admin_lock);
 619         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 620         rte_spinlock_unlock(&adapter->admin_lock);
 621         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 622                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 623                 return -ENOTSUP;
 624         }
 625
 626         for (i = 0 ; i < reta_size ; i++) {
 627                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 628                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 629                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 630                         reta_conf[reta_conf_idx].reta[reta_idx] =
 631                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 632         }
 633
 634         return 0;
 635 }
 636
 637 static int ena_rss_init_default(struct ena_adapter *adapter)
 638 {
 639         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 640         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 641         int rc, i;
 642         u32 val;
 643
 644         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 645         if (unlikely(rc)) {
 646                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 647                 goto err_rss_init;
 648         }
 649
 650         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 651                 val = i % nb_rx_queues;
 652                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 653                                                        ENA_IO_RXQ_IDX(val));
 654                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 655                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 656                         goto err_fill_indir;
 657                 }
 658         }
 659
 660         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 661                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 662         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 663                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 664                 goto err_fill_indir;
 665         }
 666
 667         rc = ena_com_set_default_hash_ctrl(ena_dev);
 668         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 669                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 670                 goto err_fill_indir;
 671         }
 672
 673         rc = ena_com_indirect_table_set(ena_dev);
 674         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 675                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 676                 goto err_fill_indir;
 677         }
 678         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 679                 adapter->rte_dev->data->port_id);
 680
 681         return 0;
 682
 683 err_fill_indir:
 684         ena_com_rss_destroy(ena_dev);
 685 err_rss_init:
 686
 687         return rc;
 688 }
 689
 690 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 691 {
 692         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 693         int nb_queues = dev->data->nb_rx_queues;
 694         int i;
 695
 696         for (i = 0; i < nb_queues; i++)
 697                 ena_rx_queue_release(queues[i]);
 698 }
 699
 700 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 701 {
 702         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 703         int nb_queues = dev->data->nb_tx_queues;
 704         int i;
 705
 706         for (i = 0; i < nb_queues; i++)
 707                 ena_tx_queue_release(queues[i]);
 708 }
 709
 710 static void ena_rx_queue_release(void *queue)
 711 {
 712         struct ena_ring *ring = (struct ena_ring *)queue;
 713
 714         /* Free ring resources */
 715         if (ring->rx_buffer_info)
 716                 rte_free(ring->rx_buffer_info);
 717         ring->rx_buffer_info = NULL;
 718
 719         if (ring->rx_refill_buffer)
 720                 rte_free(ring->rx_refill_buffer);
 721         ring->rx_refill_buffer = NULL;
 722
 723         if (ring->empty_rx_reqs)
 724                 rte_free(ring->empty_rx_reqs);
 725         ring->empty_rx_reqs = NULL;
 726
 727         ring->configured = 0;
 728
 729         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 730                 ring->port_id, ring->id);
 731 }
 732
 733 static void ena_tx_queue_release(void *queue)
 734 {
 735         struct ena_ring *ring = (struct ena_ring *)queue;
 736
 737         /* Free ring resources */
 738         if (ring->push_buf_intermediate_buf)
 739                 rte_free(ring->push_buf_intermediate_buf);
 740
 741         if (ring->tx_buffer_info)
 742                 rte_free(ring->tx_buffer_info);
 743
 744         if (ring->empty_tx_reqs)
 745                 rte_free(ring->empty_tx_reqs);
 746
 747         ring->empty_tx_reqs = NULL;
 748         ring->tx_buffer_info = NULL;
 749         ring->push_buf_intermediate_buf = NULL;
 750
 751         ring->configured = 0;
 752
 753         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 754                 ring->port_id, ring->id);
 755 }
 756
 757 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 758 {
 759         unsigned int i;
 760
 761         for (i = 0; i < ring->ring_size; ++i) {
 762                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 763                 if (rx_info->mbuf) {
 764                         rte_mbuf_raw_free(rx_info->mbuf);
 765                         rx_info->mbuf = NULL;
 766                 }
 767         }
 768 }
 769
 770 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 771 {
 772         unsigned int i;
 773
 774         for (i = 0; i < ring->ring_size; ++i) {
 775                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 776
 777                 if (tx_buf->mbuf) {
 778                         rte_pktmbuf_free(tx_buf->mbuf);
 779                         tx_buf->mbuf = NULL;
 780                 }
 781         }
 782 }
 783
 784 static int ena_link_update(struct rte_eth_dev *dev,
 785                            __rte_unused int wait_to_complete)
 786 {
 787         struct rte_eth_link *link = &dev->data->dev_link;
 788         struct ena_adapter *adapter = dev->data->dev_private;
 789
 790         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 791         link->link_speed = ETH_SPEED_NUM_NONE;
 792         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 793
 794         return 0;
 795 }
 796
 797 static int ena_queue_start_all(struct rte_eth_dev *dev,
 798                                enum ena_ring_type ring_type)
 799 {
 800         struct ena_adapter *adapter = dev->data->dev_private;
 801         struct ena_ring *queues = NULL;
 802         int nb_queues;
 803         int i = 0;
 804         int rc = 0;
 805
 806         if (ring_type == ENA_RING_TYPE_RX) {
 807                 queues = adapter->rx_ring;
 808                 nb_queues = dev->data->nb_rx_queues;
 809         } else {
 810                 queues = adapter->tx_ring;
 811                 nb_queues = dev->data->nb_tx_queues;
 812         }
 813         for (i = 0; i < nb_queues; i++) {
 814                 if (queues[i].configured) {
 815                         if (ring_type == ENA_RING_TYPE_RX) {
 816                                 ena_assert_msg(
 817                                         dev->data->rx_queues[i] == &queues[i],
 818                                         "Inconsistent state of rx queues\n");
 819                         } else {
 820                                 ena_assert_msg(
 821                                         dev->data->tx_queues[i] == &queues[i],
 822                                         "Inconsistent state of tx queues\n");
 823                         }
 824
 825                         rc = ena_queue_start(&queues[i]);
 826
 827                         if (rc) {
 828                                 PMD_INIT_LOG(ERR,
 829                                              "failed to start queue %d type(%d)",
 830                                              i, ring_type);
 831                                 goto err;
 832                         }
 833                 }
 834         }
 835
 836         return 0;
 837
 838 err:
 839         while (i--)
 840                 if (queues[i].configured)
 841                         ena_queue_stop(&queues[i]);
 842
 843         return rc;
 844 }
 845
 846 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 847 {
 848         uint32_t max_frame_len = adapter->max_mtu;
 849
 850         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 851             DEV_RX_OFFLOAD_JUMBO_FRAME)
 852                 max_frame_len =
 853                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 854
 855         return max_frame_len;
 856 }
 857
 858 static int ena_check_valid_conf(struct ena_adapter *adapter)
 859 {
 860         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 861
 862         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 863                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 864                                   "max mtu: %d, min mtu: %d",
 865                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 866                 return ENA_COM_UNSUPPORTED;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int
 873 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 874                        bool use_large_llq_hdr)
 875 {
 876         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 877         struct ena_com_dev *ena_dev = ctx->ena_dev;
 878         uint32_t max_tx_queue_size;
 879         uint32_t max_rx_queue_size;
 880
 881         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 882                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 883                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 884                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 885                         max_queue_ext->max_rx_sq_depth);
 886                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 887
 888                 if (ena_dev->tx_mem_queue_type ==
 889                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 890                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 891                                 llq->max_llq_depth);
 892                 } else {
 893                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 894                                 max_queue_ext->max_tx_sq_depth);
 895                 }
 896
 897                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 898                         max_queue_ext->max_per_packet_rx_descs);
 899                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 900                         max_queue_ext->max_per_packet_tx_descs);
 901         } else {
 902                 struct ena_admin_queue_feature_desc *max_queues =
 903                         &ctx->get_feat_ctx->max_queues;
 904                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 905                         max_queues->max_sq_depth);
 906                 max_tx_queue_size = max_queues->max_cq_depth;
 907
 908                 if (ena_dev->tx_mem_queue_type ==
 909                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 910                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 911                                 llq->max_llq_depth);
 912                 } else {
 913                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 914                                 max_queues->max_sq_depth);
 915                 }
 916
 917                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 918                         max_queues->max_packet_rx_descs);
 919                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 920                         max_queues->max_packet_tx_descs);
 921         }
 922
 923         /* Round down to the nearest power of 2 */
 924         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 925         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 926
 927         if (use_large_llq_hdr) {
 928                 if ((llq->entry_size_ctrl_supported &
 929                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 930                     (ena_dev->tx_mem_queue_type ==
 931                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 932                         max_tx_queue_size /= 2;
 933                         PMD_INIT_LOG(INFO,
 934                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 935                                 max_tx_queue_size);
 936                 } else {
 937                         PMD_INIT_LOG(ERR,
 938                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 939                 }
 940         }
 941
 942         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 943                 PMD_INIT_LOG(ERR, "Invalid queue size");
 944                 return -EFAULT;
 945         }
 946
 947         ctx->max_tx_queue_size = max_tx_queue_size;
 948         ctx->max_rx_queue_size = max_rx_queue_size;
 949
 950         return 0;
 951 }
 952
 953 static void ena_stats_restart(struct rte_eth_dev *dev)
 954 {
 955         struct ena_adapter *adapter = dev->data->dev_private;
 956
 957         rte_atomic64_init(&adapter->drv_stats->ierrors);
 958         rte_atomic64_init(&adapter->drv_stats->oerrors);
 959         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 960         adapter->drv_stats->rx_drops = 0;
 961 }
 962
 963 static int ena_stats_get(struct rte_eth_dev *dev,
 964                           struct rte_eth_stats *stats)
 965 {
 966         struct ena_admin_basic_stats ena_stats;
 967         struct ena_adapter *adapter = dev->data->dev_private;
 968         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 969         int rc;
 970         int i;
 971         int max_rings_stats;
 972
 973         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 974                 return -ENOTSUP;
 975
 976         memset(&ena_stats, 0, sizeof(ena_stats));
 977
 978         rte_spinlock_lock(&adapter->admin_lock);
 979         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 980         rte_spinlock_unlock(&adapter->admin_lock);
 981         if (unlikely(rc)) {
 982                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 983                 return rc;
 984         }
 985
 986         /* Set of basic statistics from ENA */
 987         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 988                                           ena_stats.rx_pkts_low);
 989         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 990                                           ena_stats.tx_pkts_low);
 991         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 992                                         ena_stats.rx_bytes_low);
 993         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 994                                         ena_stats.tx_bytes_low);
 995
 996         /* Driver related stats */
 997         stats->imissed = adapter->drv_stats->rx_drops;
 998         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 999         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1000         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1001
1002         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1003                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1004         for (i = 0; i < max_rings_stats; ++i) {
1005                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1006
1007                 stats->q_ibytes[i] = rx_stats->bytes;
1008                 stats->q_ipackets[i] = rx_stats->cnt;
1009                 stats->q_errors[i] = rx_stats->bad_desc_num +
1010                         rx_stats->bad_req_id;
1011         }
1012
1013         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1014                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1015         for (i = 0; i < max_rings_stats; ++i) {
1016                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1017
1018                 stats->q_obytes[i] = tx_stats->bytes;
1019                 stats->q_opackets[i] = tx_stats->cnt;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1026 {
1027         struct ena_adapter *adapter;
1028         struct ena_com_dev *ena_dev;
1029         int rc = 0;
1030
1031         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1032         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1033         adapter = dev->data->dev_private;
1034
1035         ena_dev = &adapter->ena_dev;
1036         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1037
1038         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1039                 PMD_DRV_LOG(ERR,
1040                         "Invalid MTU setting. new_mtu: %d "
1041                         "max mtu: %d min mtu: %d\n",
1042                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1043                 return -EINVAL;
1044         }
1045
1046         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1047         if (rc)
1048                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1049         else
1050                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1051
1052         return rc;
1053 }
1054
1055 static int ena_start(struct rte_eth_dev *dev)
1056 {
1057         struct ena_adapter *adapter = dev->data->dev_private;
1058         uint64_t ticks;
1059         int rc = 0;
1060
1061         rc = ena_check_valid_conf(adapter);
1062         if (rc)
1063                 return rc;
1064
1065         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1066         if (rc)
1067                 return rc;
1068
1069         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1070         if (rc)
1071                 goto err_start_tx;
1072
1073         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1074             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1075                 rc = ena_rss_init_default(adapter);
1076                 if (rc)
1077                         goto err_rss_init;
1078         }
1079
1080         ena_stats_restart(dev);
1081
1082         adapter->timestamp_wd = rte_get_timer_cycles();
1083         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1084
1085         ticks = rte_get_timer_hz();
1086         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1087                         ena_timer_wd_callback, adapter);
1088
1089         ++adapter->dev_stats.dev_start;
1090         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1091
1092         return 0;
1093
1094 err_rss_init:
1095         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1096 err_start_tx:
1097         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1098         return rc;
1099 }
1100
1101 static int ena_stop(struct rte_eth_dev *dev)
1102 {
1103         struct ena_adapter *adapter = dev->data->dev_private;
1104         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1105         int rc;
1106
1107         rte_timer_stop_sync(&adapter->timer_wd);
1108         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1109         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1110
1111         if (adapter->trigger_reset) {
1112                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1113                 if (rc)
1114                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1115         }
1116
1117         ++adapter->dev_stats.dev_stop;
1118         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1119         dev->data->dev_started = 0;
1120
1121         return 0;
1122 }
1123
1124 static int ena_create_io_queue(struct ena_ring *ring)
1125 {
1126         struct ena_adapter *adapter;
1127         struct ena_com_dev *ena_dev;
1128         struct ena_com_create_io_ctx ctx =
1129                 /* policy set to _HOST just to satisfy icc compiler */
1130                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1131                   0, 0, 0, 0, 0 };
1132         uint16_t ena_qid;
1133         unsigned int i;
1134         int rc;
1135
1136         adapter = ring->adapter;
1137         ena_dev = &adapter->ena_dev;
1138
1139         if (ring->type == ENA_RING_TYPE_TX) {
1140                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1141                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1142                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1143                 for (i = 0; i < ring->ring_size; i++)
1144                         ring->empty_tx_reqs[i] = i;
1145         } else {
1146                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1147                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1148                 for (i = 0; i < ring->ring_size; i++)
1149                         ring->empty_rx_reqs[i] = i;
1150         }
1151         ctx.queue_size = ring->ring_size;
1152         ctx.qid = ena_qid;
1153         ctx.msix_vector = -1; /* interrupts not used */
1154         ctx.numa_node = ring->numa_socket_id;
1155
1156         rc = ena_com_create_io_queue(ena_dev, &ctx);
1157         if (rc) {
1158                 PMD_DRV_LOG(ERR,
1159                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1160                         ring->id, ena_qid, rc);
1161                 return rc;
1162         }
1163
1164         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1165                                      &ring->ena_com_io_sq,
1166                                      &ring->ena_com_io_cq);
1167         if (rc) {
1168                 PMD_DRV_LOG(ERR,
1169                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1170                         ring->id, rc);
1171                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1172                 return rc;
1173         }
1174
1175         if (ring->type == ENA_RING_TYPE_TX)
1176                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1177
1178         return 0;
1179 }
1180
1181 static void ena_queue_stop(struct ena_ring *ring)
1182 {
1183         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1184
1185         if (ring->type == ENA_RING_TYPE_RX) {
1186                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1187                 ena_rx_queue_release_bufs(ring);
1188         } else {
1189                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1190                 ena_tx_queue_release_bufs(ring);
1191         }
1192 }
1193
1194 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1195                               enum ena_ring_type ring_type)
1196 {
1197         struct ena_adapter *adapter = dev->data->dev_private;
1198         struct ena_ring *queues = NULL;
1199         uint16_t nb_queues, i;
1200
1201         if (ring_type == ENA_RING_TYPE_RX) {
1202                 queues = adapter->rx_ring;
1203                 nb_queues = dev->data->nb_rx_queues;
1204         } else {
1205                 queues = adapter->tx_ring;
1206                 nb_queues = dev->data->nb_tx_queues;
1207         }
1208
1209         for (i = 0; i < nb_queues; ++i)
1210                 if (queues[i].configured)
1211                         ena_queue_stop(&queues[i]);
1212 }
1213
1214 static int ena_queue_start(struct ena_ring *ring)
1215 {
1216         int rc, bufs_num;
1217
1218         ena_assert_msg(ring->configured == 1,
1219                        "Trying to start unconfigured queue\n");
1220
1221         rc = ena_create_io_queue(ring);
1222         if (rc) {
1223                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1224                 return rc;
1225         }
1226
1227         ring->next_to_clean = 0;
1228         ring->next_to_use = 0;
1229
1230         if (ring->type == ENA_RING_TYPE_TX) {
1231                 ring->tx_stats.available_desc =
1232                         ena_com_free_q_entries(ring->ena_com_io_sq);
1233                 return 0;
1234         }
1235
1236         bufs_num = ring->ring_size - 1;
1237         rc = ena_populate_rx_queue(ring, bufs_num);
1238         if (rc != bufs_num) {
1239                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1240                                          ENA_IO_RXQ_IDX(ring->id));
1241                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1242                 return ENA_COM_FAULT;
1243         }
1244         /* Flush per-core RX buffers pools cache as they can be used on other
1245          * cores as well.
1246          */
1247         rte_mempool_cache_flush(NULL, ring->mb_pool);
1248
1249         return 0;
1250 }
1251
1252 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1253                               uint16_t queue_idx,
1254                               uint16_t nb_desc,
1255                               unsigned int socket_id,
1256                               const struct rte_eth_txconf *tx_conf)
1257 {
1258         struct ena_ring *txq = NULL;
1259         struct ena_adapter *adapter = dev->data->dev_private;
1260         unsigned int i;
1261
1262         txq = &adapter->tx_ring[queue_idx];
1263
1264         if (txq->configured) {
1265                 PMD_DRV_LOG(CRIT,
1266                         "API violation. Queue %d is already configured\n",
1267                         queue_idx);
1268                 return ENA_COM_FAULT;
1269         }
1270
1271         if (!rte_is_power_of_2(nb_desc)) {
1272                 PMD_DRV_LOG(ERR,
1273                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1274                         nb_desc);
1275                 return -EINVAL;
1276         }
1277
1278         if (nb_desc > adapter->max_tx_ring_size) {
1279                 PMD_DRV_LOG(ERR,
1280                         "Unsupported size of TX queue (max size: %d)\n",
1281                         adapter->max_tx_ring_size);
1282                 return -EINVAL;
1283         }
1284
1285         txq->port_id = dev->data->port_id;
1286         txq->next_to_clean = 0;
1287         txq->next_to_use = 0;
1288         txq->ring_size = nb_desc;
1289         txq->size_mask = nb_desc - 1;
1290         txq->numa_socket_id = socket_id;
1291         txq->pkts_without_db = false;
1292
1293         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1294                                           sizeof(struct ena_tx_buffer) *
1295                                           txq->ring_size,
1296                                           RTE_CACHE_LINE_SIZE);
1297         if (!txq->tx_buffer_info) {
1298                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1299                 return -ENOMEM;
1300         }
1301
1302         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1303                                          sizeof(u16) * txq->ring_size,
1304                                          RTE_CACHE_LINE_SIZE);
1305         if (!txq->empty_tx_reqs) {
1306                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1307                 rte_free(txq->tx_buffer_info);
1308                 return -ENOMEM;
1309         }
1310
1311         txq->push_buf_intermediate_buf =
1312                 rte_zmalloc("txq->push_buf_intermediate_buf",
1313                             txq->tx_max_header_size,
1314                             RTE_CACHE_LINE_SIZE);
1315         if (!txq->push_buf_intermediate_buf) {
1316                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1317                 rte_free(txq->tx_buffer_info);
1318                 rte_free(txq->empty_tx_reqs);
1319                 return -ENOMEM;
1320         }
1321
1322         for (i = 0; i < txq->ring_size; i++)
1323                 txq->empty_tx_reqs[i] = i;
1324
1325         if (tx_conf != NULL) {
1326                 txq->offloads =
1327                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1328         }
1329         /* Store pointer to this queue in upper layer */
1330         txq->configured = 1;
1331         dev->data->tx_queues[queue_idx] = txq;
1332
1333         return 0;
1334 }
1335
1336 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1337                               uint16_t queue_idx,
1338                               uint16_t nb_desc,
1339                               unsigned int socket_id,
1340                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1341                               struct rte_mempool *mp)
1342 {
1343         struct ena_adapter *adapter = dev->data->dev_private;
1344         struct ena_ring *rxq = NULL;
1345         size_t buffer_size;
1346         int i;
1347
1348         rxq = &adapter->rx_ring[queue_idx];
1349         if (rxq->configured) {
1350                 PMD_DRV_LOG(CRIT,
1351                         "API violation. Queue %d is already configured\n",
1352                         queue_idx);
1353                 return ENA_COM_FAULT;
1354         }
1355
1356         if (!rte_is_power_of_2(nb_desc)) {
1357                 PMD_DRV_LOG(ERR,
1358                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1359                         nb_desc);
1360                 return -EINVAL;
1361         }
1362
1363         if (nb_desc > adapter->max_rx_ring_size) {
1364                 PMD_DRV_LOG(ERR,
1365                         "Unsupported size of RX queue (max size: %d)\n",
1366                         adapter->max_rx_ring_size);
1367                 return -EINVAL;
1368         }
1369
1370         /* ENA isn't supporting buffers smaller than 1400 bytes */
1371         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1372         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1373                 PMD_DRV_LOG(ERR,
1374                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1375                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1376                 return -EINVAL;
1377         }
1378
1379         rxq->port_id = dev->data->port_id;
1380         rxq->next_to_clean = 0;
1381         rxq->next_to_use = 0;
1382         rxq->ring_size = nb_desc;
1383         rxq->size_mask = nb_desc - 1;
1384         rxq->numa_socket_id = socket_id;
1385         rxq->mb_pool = mp;
1386
1387         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1388                 sizeof(struct ena_rx_buffer) * nb_desc,
1389                 RTE_CACHE_LINE_SIZE);
1390         if (!rxq->rx_buffer_info) {
1391                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1392                 return -ENOMEM;
1393         }
1394
1395         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1396                                             sizeof(struct rte_mbuf *) * nb_desc,
1397                                             RTE_CACHE_LINE_SIZE);
1398
1399         if (!rxq->rx_refill_buffer) {
1400                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1401                 rte_free(rxq->rx_buffer_info);
1402                 rxq->rx_buffer_info = NULL;
1403                 return -ENOMEM;
1404         }
1405
1406         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1407                                          sizeof(uint16_t) * nb_desc,
1408                                          RTE_CACHE_LINE_SIZE);
1409         if (!rxq->empty_rx_reqs) {
1410                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1411                 rte_free(rxq->rx_buffer_info);
1412                 rxq->rx_buffer_info = NULL;
1413                 rte_free(rxq->rx_refill_buffer);
1414                 rxq->rx_refill_buffer = NULL;
1415                 return -ENOMEM;
1416         }
1417
1418         for (i = 0; i < nb_desc; i++)
1419                 rxq->empty_rx_reqs[i] = i;
1420
1421         /* Store pointer to this queue in upper layer */
1422         rxq->configured = 1;
1423         dev->data->rx_queues[queue_idx] = rxq;
1424
1425         return 0;
1426 }
1427
1428 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1429                                   struct rte_mbuf *mbuf, uint16_t id)
1430 {
1431         struct ena_com_buf ebuf;
1432         int rc;
1433
1434         /* prepare physical address for DMA transaction */
1435         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1436         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1437
1438         /* pass resource to device */
1439         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1440         if (unlikely(rc != 0))
1441                 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1442
1443         return rc;
1444 }
1445
1446 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1447 {
1448         unsigned int i;
1449         int rc;
1450         uint16_t next_to_use = rxq->next_to_use;
1451         uint16_t in_use, req_id;
1452         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1453
1454         if (unlikely(!count))
1455                 return 0;
1456
1457         in_use = rxq->ring_size - 1 -
1458                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1459         ena_assert_msg(((in_use + count) < rxq->ring_size),
1460                 "bad ring state\n");
1461
1462         /* get resources for incoming packets */
1463         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1464         if (unlikely(rc < 0)) {
1465                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1466                 ++rxq->rx_stats.mbuf_alloc_fail;
1467                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1468                 return 0;
1469         }
1470
1471         for (i = 0; i < count; i++) {
1472                 struct rte_mbuf *mbuf = mbufs[i];
1473                 struct ena_rx_buffer *rx_info;
1474
1475                 if (likely((i + 4) < count))
1476                         rte_prefetch0(mbufs[i + 4]);
1477
1478                 req_id = rxq->empty_rx_reqs[next_to_use];
1479                 rx_info = &rxq->rx_buffer_info[req_id];
1480
1481                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1482                 if (unlikely(rc != 0))
1483                         break;
1484
1485                 rx_info->mbuf = mbuf;
1486                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1487         }
1488
1489         if (unlikely(i < count)) {
1490                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1491                         "buffers (from %d)\n", rxq->id, i, count);
1492                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1493                 ++rxq->rx_stats.refill_partial;
1494         }
1495
1496         /* When we submitted free recources to device... */
1497         if (likely(i > 0)) {
1498                 /* ...let HW know that it can fill buffers with data. */
1499                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1500
1501                 rxq->next_to_use = next_to_use;
1502         }
1503
1504         return i;
1505 }
1506
1507 static int ena_device_init(struct ena_com_dev *ena_dev,
1508                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1509                            bool *wd_state)
1510 {
1511         uint32_t aenq_groups;
1512         int rc;
1513         bool readless_supported;
1514
1515         /* Initialize mmio registers */
1516         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1517         if (rc) {
1518                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1519                 return rc;
1520         }
1521
1522         /* The PCIe configuration space revision id indicate if mmio reg
1523          * read is disabled.
1524          */
1525         readless_supported =
1526                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1527                                & ENA_MMIO_DISABLE_REG_READ);
1528         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1529
1530         /* reset device */
1531         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1532         if (rc) {
1533                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1534                 goto err_mmio_read_less;
1535         }
1536
1537         /* check FW version */
1538         rc = ena_com_validate_version(ena_dev);
1539         if (rc) {
1540                 PMD_DRV_LOG(ERR, "device version is too low\n");
1541                 goto err_mmio_read_less;
1542         }
1543
1544         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1545
1546         /* ENA device administration layer init */
1547         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1548         if (rc) {
1549                 PMD_DRV_LOG(ERR,
1550                         "cannot initialize ena admin queue with device\n");
1551                 goto err_mmio_read_less;
1552         }
1553
1554         /* To enable the msix interrupts the driver needs to know the number
1555          * of queues. So the driver uses polling mode to retrieve this
1556          * information.
1557          */
1558         ena_com_set_admin_polling_mode(ena_dev, true);
1559
1560         ena_config_host_info(ena_dev);
1561
1562         /* Get Device Attributes and features */
1563         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1564         if (rc) {
1565                 PMD_DRV_LOG(ERR,
1566                         "cannot get attribute for ena device rc= %d\n", rc);
1567                 goto err_admin_init;
1568         }
1569
1570         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1571                       BIT(ENA_ADMIN_NOTIFICATION) |
1572                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1573                       BIT(ENA_ADMIN_FATAL_ERROR) |
1574                       BIT(ENA_ADMIN_WARNING);
1575
1576         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1577         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1578         if (rc) {
1579                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1580                 goto err_admin_init;
1581         }
1582
1583         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1584
1585         return 0;
1586
1587 err_admin_init:
1588         ena_com_admin_destroy(ena_dev);
1589
1590 err_mmio_read_less:
1591         ena_com_mmio_reg_read_request_destroy(ena_dev);
1592
1593         return rc;
1594 }
1595
1596 static void ena_interrupt_handler_rte(void *cb_arg)
1597 {
1598         struct ena_adapter *adapter = cb_arg;
1599         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1600
1601         ena_com_admin_q_comp_intr_handler(ena_dev);
1602         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1603                 ena_com_aenq_intr_handler(ena_dev, adapter);
1604 }
1605
1606 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1607 {
1608         if (!adapter->wd_state)
1609                 return;
1610
1611         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1612                 return;
1613
1614         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1615             adapter->keep_alive_timeout)) {
1616                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1617                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1618                 adapter->trigger_reset = true;
1619                 ++adapter->dev_stats.wd_expired;
1620         }
1621 }
1622
1623 /* Check if admin queue is enabled */
1624 static void check_for_admin_com_state(struct ena_adapter *adapter)
1625 {
1626         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1627                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1628                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1629                 adapter->trigger_reset = true;
1630         }
1631 }
1632
1633 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1634                                   void *arg)
1635 {
1636         struct ena_adapter *adapter = arg;
1637         struct rte_eth_dev *dev = adapter->rte_dev;
1638
1639         check_for_missing_keep_alive(adapter);
1640         check_for_admin_com_state(adapter);
1641
1642         if (unlikely(adapter->trigger_reset)) {
1643                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1644                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1645                         NULL);
1646         }
1647 }
1648
1649 static inline void
1650 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1651                                struct ena_admin_feature_llq_desc *llq,
1652                                bool use_large_llq_hdr)
1653 {
1654         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1655         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1656         llq_config->llq_num_decs_before_header =
1657                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1658
1659         if (use_large_llq_hdr &&
1660             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1661                 llq_config->llq_ring_entry_size =
1662                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1663                 llq_config->llq_ring_entry_size_value = 256;
1664         } else {
1665                 llq_config->llq_ring_entry_size =
1666                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1667                 llq_config->llq_ring_entry_size_value = 128;
1668         }
1669 }
1670
1671 static int
1672 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1673                                 struct ena_com_dev *ena_dev,
1674                                 struct ena_admin_feature_llq_desc *llq,
1675                                 struct ena_llq_configurations *llq_default_configurations)
1676 {
1677         int rc;
1678         u32 llq_feature_mask;
1679
1680         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1681         if (!(ena_dev->supported_features & llq_feature_mask)) {
1682                 PMD_DRV_LOG(INFO,
1683                         "LLQ is not supported. Fallback to host mode policy.\n");
1684                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1685                 return 0;
1686         }
1687
1688         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1689         if (unlikely(rc)) {
1690                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1691                         "Fallback to host mode policy.");
1692                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1693                 return 0;
1694         }
1695
1696         /* Nothing to config, exit */
1697         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1698                 return 0;
1699
1700         if (!adapter->dev_mem_base) {
1701                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1702                         "Fallback to host mode policy.\n.");
1703                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1704                 return 0;
1705         }
1706
1707         ena_dev->mem_bar = adapter->dev_mem_base;
1708
1709         return 0;
1710 }
1711
1712 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1713         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1714 {
1715         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1716
1717         /* Regular queues capabilities */
1718         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1719                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1720                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1721                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1722                                     max_queue_ext->max_rx_cq_num);
1723                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1724                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1725         } else {
1726                 struct ena_admin_queue_feature_desc *max_queues =
1727                         &get_feat_ctx->max_queues;
1728                 io_tx_sq_num = max_queues->max_sq_num;
1729                 io_tx_cq_num = max_queues->max_cq_num;
1730                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1731         }
1732
1733         /* In case of LLQ use the llq number in the get feature cmd */
1734         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1735                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1736
1737         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1738         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1739         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1740
1741         if (unlikely(max_num_io_queues == 0)) {
1742                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1743                 return -EFAULT;
1744         }
1745
1746         return max_num_io_queues;
1747 }
1748
1749 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1750 {
1751         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1752         struct rte_pci_device *pci_dev;
1753         struct rte_intr_handle *intr_handle;
1754         struct ena_adapter *adapter = eth_dev->data->dev_private;
1755         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1756         struct ena_com_dev_get_features_ctx get_feat_ctx;
1757         struct ena_llq_configurations llq_config;
1758         const char *queue_type_str;
1759         uint32_t max_num_io_queues;
1760         int rc;
1761         static int adapters_found;
1762         bool disable_meta_caching;
1763         bool wd_state = false;
1764
1765         eth_dev->dev_ops = &ena_dev_ops;
1766         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1767         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1768         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1769
1770         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1771                 return 0;
1772
1773         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1774
1775         memset(adapter, 0, sizeof(struct ena_adapter));
1776         ena_dev = &adapter->ena_dev;
1777
1778         adapter->rte_eth_dev_data = eth_dev->data;
1779         adapter->rte_dev = eth_dev;
1780
1781         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1782         adapter->pdev = pci_dev;
1783
1784         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1785                      pci_dev->addr.domain,
1786                      pci_dev->addr.bus,
1787                      pci_dev->addr.devid,
1788                      pci_dev->addr.function);
1789
1790         intr_handle = &pci_dev->intr_handle;
1791
1792         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1793         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1794
1795         if (!adapter->regs) {
1796                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1797                              ENA_REGS_BAR);
1798                 return -ENXIO;
1799         }
1800
1801         ena_dev->reg_bar = adapter->regs;
1802         ena_dev->dmadev = adapter->pdev;
1803
1804         adapter->id_number = adapters_found;
1805
1806         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1807                  adapter->id_number);
1808
1809         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1810         if (rc != 0) {
1811                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1812                 goto err;
1813         }
1814
1815         /* device specific initialization routine */
1816         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1817         if (rc) {
1818                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1819                 goto err;
1820         }
1821         adapter->wd_state = wd_state;
1822
1823         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1824                 adapter->use_large_llq_hdr);
1825         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1826                                              &get_feat_ctx.llq, &llq_config);
1827         if (unlikely(rc)) {
1828                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1829                 return rc;
1830         }
1831
1832         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1833                 queue_type_str = "Regular";
1834         else
1835                 queue_type_str = "Low latency";
1836         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1837
1838         calc_queue_ctx.ena_dev = ena_dev;
1839         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1840
1841         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1842         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1843                 adapter->use_large_llq_hdr);
1844         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1845                 rc = -EFAULT;
1846                 goto err_device_destroy;
1847         }
1848
1849         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1850         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1851         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1852         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1853         adapter->max_num_io_queues = max_num_io_queues;
1854
1855         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1856                 disable_meta_caching =
1857                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1858                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1859         } else {
1860                 disable_meta_caching = false;
1861         }
1862
1863         /* prepare ring structures */
1864         ena_init_rings(adapter, disable_meta_caching);
1865
1866         ena_config_debug_area(adapter);
1867
1868         /* Set max MTU for this device */
1869         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1870
1871         /* set device support for offloads */
1872         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1873                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1874         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1875                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1876         adapter->offloads.rx_csum_supported =
1877                 (get_feat_ctx.offload.rx_supported &
1878                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1879
1880         /* Copy MAC address and point DPDK to it */
1881         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1882         rte_ether_addr_copy((struct rte_ether_addr *)
1883                         get_feat_ctx.dev_attr.mac_addr,
1884                         (struct rte_ether_addr *)adapter->mac_addr);
1885
1886         adapter->drv_stats = rte_zmalloc("adapter stats",
1887                                          sizeof(*adapter->drv_stats),
1888                                          RTE_CACHE_LINE_SIZE);
1889         if (!adapter->drv_stats) {
1890                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1891                 rc = -ENOMEM;
1892                 goto err_delete_debug_area;
1893         }
1894
1895         rte_spinlock_init(&adapter->admin_lock);
1896
1897         rte_intr_callback_register(intr_handle,
1898                                    ena_interrupt_handler_rte,
1899                                    adapter);
1900         rte_intr_enable(intr_handle);
1901         ena_com_set_admin_polling_mode(ena_dev, false);
1902         ena_com_admin_aenq_enable(ena_dev);
1903
1904         if (adapters_found == 0)
1905                 rte_timer_subsystem_init();
1906         rte_timer_init(&adapter->timer_wd);
1907
1908         adapters_found++;
1909         adapter->state = ENA_ADAPTER_STATE_INIT;
1910
1911         return 0;
1912
1913 err_delete_debug_area:
1914         ena_com_delete_debug_area(ena_dev);
1915
1916 err_device_destroy:
1917         ena_com_delete_host_info(ena_dev);
1918         ena_com_admin_destroy(ena_dev);
1919
1920 err:
1921         return rc;
1922 }
1923
1924 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1925 {
1926         struct ena_adapter *adapter = eth_dev->data->dev_private;
1927         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1928
1929         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1930                 return;
1931
1932         ena_com_set_admin_running_state(ena_dev, false);
1933
1934         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1935                 ena_close(eth_dev);
1936
1937         ena_com_delete_debug_area(ena_dev);
1938         ena_com_delete_host_info(ena_dev);
1939
1940         ena_com_abort_admin_commands(ena_dev);
1941         ena_com_wait_for_abort_completion(ena_dev);
1942         ena_com_admin_destroy(ena_dev);
1943         ena_com_mmio_reg_read_request_destroy(ena_dev);
1944
1945         adapter->state = ENA_ADAPTER_STATE_FREE;
1946 }
1947
1948 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1949 {
1950         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1951                 return 0;
1952
1953         ena_destroy_device(eth_dev);
1954
1955         return 0;
1956 }
1957
1958 static int ena_dev_configure(struct rte_eth_dev *dev)
1959 {
1960         struct ena_adapter *adapter = dev->data->dev_private;
1961
1962         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1963
1964         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1965                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1966
1967         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1968         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1969         return 0;
1970 }
1971
1972 static void ena_init_rings(struct ena_adapter *adapter,
1973                            bool disable_meta_caching)
1974 {
1975         size_t i;
1976
1977         for (i = 0; i < adapter->max_num_io_queues; i++) {
1978                 struct ena_ring *ring = &adapter->tx_ring[i];
1979
1980                 ring->configured = 0;
1981                 ring->type = ENA_RING_TYPE_TX;
1982                 ring->adapter = adapter;
1983                 ring->id = i;
1984                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1985                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1986                 ring->sgl_size = adapter->max_tx_sgl_size;
1987                 ring->disable_meta_caching = disable_meta_caching;
1988         }
1989
1990         for (i = 0; i < adapter->max_num_io_queues; i++) {
1991                 struct ena_ring *ring = &adapter->rx_ring[i];
1992
1993                 ring->configured = 0;
1994                 ring->type = ENA_RING_TYPE_RX;
1995                 ring->adapter = adapter;
1996                 ring->id = i;
1997                 ring->sgl_size = adapter->max_rx_sgl_size;
1998         }
1999 }
2000
2001 static int ena_infos_get(struct rte_eth_dev *dev,
2002                           struct rte_eth_dev_info *dev_info)
2003 {
2004         struct ena_adapter *adapter;
2005         struct ena_com_dev *ena_dev;
2006         uint64_t rx_feat = 0, tx_feat = 0;
2007
2008         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2009         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2010         adapter = dev->data->dev_private;
2011
2012         ena_dev = &adapter->ena_dev;
2013         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2014
2015         dev_info->speed_capa =
2016                         ETH_LINK_SPEED_1G   |
2017                         ETH_LINK_SPEED_2_5G |
2018                         ETH_LINK_SPEED_5G   |
2019                         ETH_LINK_SPEED_10G  |
2020                         ETH_LINK_SPEED_25G  |
2021                         ETH_LINK_SPEED_40G  |
2022                         ETH_LINK_SPEED_50G  |
2023                         ETH_LINK_SPEED_100G;
2024
2025         /* Set Tx & Rx features available for device */
2026         if (adapter->offloads.tso4_supported)
2027                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2028
2029         if (adapter->offloads.tx_csum_supported)
2030                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2031                         DEV_TX_OFFLOAD_UDP_CKSUM |
2032                         DEV_TX_OFFLOAD_TCP_CKSUM;
2033
2034         if (adapter->offloads.rx_csum_supported)
2035                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2036                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2037                         DEV_RX_OFFLOAD_TCP_CKSUM;
2038
2039         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2040
2041         /* Inform framework about available features */
2042         dev_info->rx_offload_capa = rx_feat;
2043         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
2044         dev_info->rx_queue_offload_capa = rx_feat;
2045         dev_info->tx_offload_capa = tx_feat;
2046         dev_info->tx_queue_offload_capa = tx_feat;
2047
2048         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2049                                            ETH_RSS_UDP;
2050
2051         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2052         dev_info->max_rx_pktlen  = adapter->max_mtu;
2053         dev_info->max_mac_addrs = 1;
2054
2055         dev_info->max_rx_queues = adapter->max_num_io_queues;
2056         dev_info->max_tx_queues = adapter->max_num_io_queues;
2057         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2058
2059         adapter->tx_supported_offloads = tx_feat;
2060         adapter->rx_supported_offloads = rx_feat;
2061
2062         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2063         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2064         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2065                                         adapter->max_rx_sgl_size);
2066         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2067                                         adapter->max_rx_sgl_size);
2068
2069         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2070         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2071         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2072                                         adapter->max_tx_sgl_size);
2073         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2074                                         adapter->max_tx_sgl_size);
2075
2076         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2077         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2078
2079         return 0;
2080 }
2081
2082 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2083 {
2084         mbuf->data_len = len;
2085         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2086         mbuf->refcnt = 1;
2087         mbuf->next = NULL;
2088 }
2089
2090 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2091                                     struct ena_com_rx_buf_info *ena_bufs,
2092                                     uint32_t descs,
2093                                     uint16_t *next_to_clean,
2094                                     uint8_t offset)
2095 {
2096         struct rte_mbuf *mbuf;
2097         struct rte_mbuf *mbuf_head;
2098         struct ena_rx_buffer *rx_info;
2099         int rc;
2100         uint16_t ntc, len, req_id, buf = 0;
2101
2102         if (unlikely(descs == 0))
2103                 return NULL;
2104
2105         ntc = *next_to_clean;
2106
2107         len = ena_bufs[buf].len;
2108         req_id = ena_bufs[buf].req_id;
2109
2110         rx_info = &rx_ring->rx_buffer_info[req_id];
2111
2112         mbuf = rx_info->mbuf;
2113         RTE_ASSERT(mbuf != NULL);
2114
2115         ena_init_rx_mbuf(mbuf, len);
2116
2117         /* Fill the mbuf head with the data specific for 1st segment. */
2118         mbuf_head = mbuf;
2119         mbuf_head->nb_segs = descs;
2120         mbuf_head->port = rx_ring->port_id;
2121         mbuf_head->pkt_len = len;
2122         mbuf_head->data_off += offset;
2123
2124         rx_info->mbuf = NULL;
2125         rx_ring->empty_rx_reqs[ntc] = req_id;
2126         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2127
2128         while (--descs) {
2129                 ++buf;
2130                 len = ena_bufs[buf].len;
2131                 req_id = ena_bufs[buf].req_id;
2132
2133                 rx_info = &rx_ring->rx_buffer_info[req_id];
2134                 RTE_ASSERT(rx_info->mbuf != NULL);
2135
2136                 if (unlikely(len == 0)) {
2137                         /*
2138                          * Some devices can pass descriptor with the length 0.
2139                          * To avoid confusion, the PMD is simply putting the
2140                          * descriptor back, as it was never used. We'll avoid
2141                          * mbuf allocation that way.
2142                          */
2143                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2144                                 rx_info->mbuf, req_id);
2145                         if (unlikely(rc != 0)) {
2146                                 /* Free the mbuf in case of an error. */
2147                                 rte_mbuf_raw_free(rx_info->mbuf);
2148                         } else {
2149                                 /*
2150                                  * If there was no error, just exit the loop as
2151                                  * 0 length descriptor is always the last one.
2152                                  */
2153                                 break;
2154                         }
2155                 } else {
2156                         /* Create an mbuf chain. */
2157                         mbuf->next = rx_info->mbuf;
2158                         mbuf = mbuf->next;
2159
2160                         ena_init_rx_mbuf(mbuf, len);
2161                         mbuf_head->pkt_len += len;
2162                 }
2163
2164                 /*
2165                  * Mark the descriptor as depleted and perform necessary
2166                  * cleanup.
2167                  * This code will execute in two cases:
2168                  *  1. Descriptor len was greater than 0 - normal situation.
2169                  *  2. Descriptor len was 0 and we failed to add the descriptor
2170                  *     to the device. In that situation, we should try to add
2171                  *     the mbuf again in the populate routine and mark the
2172                  *     descriptor as used up by the device.
2173                  */
2174                 rx_info->mbuf = NULL;
2175                 rx_ring->empty_rx_reqs[ntc] = req_id;
2176                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2177         }
2178
2179         *next_to_clean = ntc;
2180
2181         return mbuf_head;
2182 }
2183
2184 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2185                                   uint16_t nb_pkts)
2186 {
2187         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2188         unsigned int free_queue_entries;
2189         unsigned int refill_threshold;
2190         uint16_t next_to_clean = rx_ring->next_to_clean;
2191         uint16_t descs_in_use;
2192         struct rte_mbuf *mbuf;
2193         uint16_t completed;
2194         struct ena_com_rx_ctx ena_rx_ctx;
2195         int i, rc = 0;
2196
2197         /* Check adapter state */
2198         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2199                 PMD_DRV_LOG(ALERT,
2200                         "Trying to receive pkts while device is NOT running\n");
2201                 return 0;
2202         }
2203
2204         descs_in_use = rx_ring->ring_size -
2205                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2206         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2207
2208         for (completed = 0; completed < nb_pkts; completed++) {
2209                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2210                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2211                 ena_rx_ctx.descs = 0;
2212                 ena_rx_ctx.pkt_offset = 0;
2213                 /* receive packet context */
2214                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2215                                     rx_ring->ena_com_io_sq,
2216                                     &ena_rx_ctx);
2217                 if (unlikely(rc)) {
2218                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2219                         if (rc == ENA_COM_NO_SPACE) {
2220                                 ++rx_ring->rx_stats.bad_desc_num;
2221                                 rx_ring->adapter->reset_reason =
2222                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2223                         } else {
2224                                 ++rx_ring->rx_stats.bad_req_id;
2225                                 rx_ring->adapter->reset_reason =
2226                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2227                         }
2228                         rx_ring->adapter->trigger_reset = true;
2229                         return 0;
2230                 }
2231
2232                 mbuf = ena_rx_mbuf(rx_ring,
2233                         ena_rx_ctx.ena_bufs,
2234                         ena_rx_ctx.descs,
2235                         &next_to_clean,
2236                         ena_rx_ctx.pkt_offset);
2237                 if (unlikely(mbuf == NULL)) {
2238                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2239                                 rx_ring->empty_rx_reqs[next_to_clean] =
2240                                         rx_ring->ena_bufs[i].req_id;
2241                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2242                                         next_to_clean, rx_ring->size_mask);
2243                         }
2244                         break;
2245                 }
2246
2247                 /* fill mbuf attributes if any */
2248                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2249
2250                 if (unlikely(mbuf->ol_flags &
2251                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2252                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2253                         ++rx_ring->rx_stats.bad_csum;
2254                 }
2255
2256                 rx_pkts[completed] = mbuf;
2257                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2258         }
2259
2260         rx_ring->rx_stats.cnt += completed;
2261         rx_ring->next_to_clean = next_to_clean;
2262
2263         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2264         refill_threshold =
2265                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2266                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2267
2268         /* Burst refill to save doorbells, memory barriers, const interval */
2269         if (free_queue_entries > refill_threshold) {
2270                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2271                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2272         }
2273
2274         return completed;
2275 }
2276
2277 static uint16_t
2278 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2279                 uint16_t nb_pkts)
2280 {
2281         int32_t ret;
2282         uint32_t i;
2283         struct rte_mbuf *m;
2284         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2285         struct rte_ipv4_hdr *ip_hdr;
2286         uint64_t ol_flags;
2287         uint16_t frag_field;
2288
2289         for (i = 0; i != nb_pkts; i++) {
2290                 m = tx_pkts[i];
2291                 ol_flags = m->ol_flags;
2292
2293                 if (!(ol_flags & PKT_TX_IPV4))
2294                         continue;
2295
2296                 /* If there was not L2 header length specified, assume it is
2297                  * length of the ethernet header.
2298                  */
2299                 if (unlikely(m->l2_len == 0))
2300                         m->l2_len = sizeof(struct rte_ether_hdr);
2301
2302                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2303                                                  m->l2_len);
2304                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2305
2306                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2307                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2308
2309                         /* If IPv4 header has DF flag enabled and TSO support is
2310                          * disabled, partial chcecksum should not be calculated.
2311                          */
2312                         if (!tx_ring->adapter->offloads.tso4_supported)
2313                                 continue;
2314                 }
2315
2316                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2317                                 (ol_flags & PKT_TX_L4_MASK) ==
2318                                 PKT_TX_SCTP_CKSUM) {
2319                         rte_errno = ENOTSUP;
2320                         return i;
2321                 }
2322
2323 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2324                 ret = rte_validate_tx_offload(m);
2325                 if (ret != 0) {
2326                         rte_errno = -ret;
2327                         return i;
2328                 }
2329 #endif
2330
2331                 /* In case we are supposed to TSO and have DF not set (DF=0)
2332                  * hardware must be provided with partial checksum, otherwise
2333                  * it will take care of necessary calculations.
2334                  */
2335
2336                 ret = rte_net_intel_cksum_flags_prepare(m,
2337                         ol_flags & ~PKT_TX_TCP_SEG);
2338                 if (ret != 0) {
2339                         rte_errno = -ret;
2340                         return i;
2341                 }
2342         }
2343
2344         return i;
2345 }
2346
2347 static void ena_update_hints(struct ena_adapter *adapter,
2348                              struct ena_admin_ena_hw_hints *hints)
2349 {
2350         if (hints->admin_completion_tx_timeout)
2351                 adapter->ena_dev.admin_queue.completion_timeout =
2352                         hints->admin_completion_tx_timeout * 1000;
2353
2354         if (hints->mmio_read_timeout)
2355                 /* convert to usec */
2356                 adapter->ena_dev.mmio_read.reg_read_to =
2357                         hints->mmio_read_timeout * 1000;
2358
2359         if (hints->driver_watchdog_timeout) {
2360                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2361                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2362                 else
2363                         // Convert msecs to ticks
2364                         adapter->keep_alive_timeout =
2365                                 (hints->driver_watchdog_timeout *
2366                                 rte_get_timer_hz()) / 1000;
2367         }
2368 }
2369
2370 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2371                                               struct rte_mbuf *mbuf)
2372 {
2373         struct ena_com_dev *ena_dev;
2374         int num_segments, header_len, rc;
2375
2376         ena_dev = &tx_ring->adapter->ena_dev;
2377         num_segments = mbuf->nb_segs;
2378         header_len = mbuf->data_len;
2379
2380         if (likely(num_segments < tx_ring->sgl_size))
2381                 goto checkspace;
2382
2383         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2384             (num_segments == tx_ring->sgl_size) &&
2385             (header_len < tx_ring->tx_max_header_size))
2386                 goto checkspace;
2387
2388         /* Checking for space for 2 additional metadata descriptors due to
2389          * possible header split and metadata descriptor. Linearization will
2390          * be needed so we reduce the segments number from num_segments to 1
2391          */
2392         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2393                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2394                 return ENA_COM_NO_MEM;
2395         }
2396         ++tx_ring->tx_stats.linearize;
2397         rc = rte_pktmbuf_linearize(mbuf);
2398         if (unlikely(rc)) {
2399                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2400                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2401                 ++tx_ring->tx_stats.linearize_failed;
2402                 return rc;
2403         }
2404
2405         return 0;
2406
2407 checkspace:
2408         /* Checking for space for 2 additional metadata descriptors due to
2409          * possible header split and metadata descriptor
2410          */
2411         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2412                                           num_segments + 2)) {
2413                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2414                 return ENA_COM_NO_MEM;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2421         struct ena_tx_buffer *tx_info,
2422         struct rte_mbuf *mbuf,
2423         void **push_header,
2424         uint16_t *header_len)
2425 {
2426         struct ena_com_buf *ena_buf;
2427         uint16_t delta, seg_len, push_len;
2428
2429         delta = 0;
2430         seg_len = mbuf->data_len;
2431
2432         tx_info->mbuf = mbuf;
2433         ena_buf = tx_info->bufs;
2434
2435         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2436                 /*
2437                  * Tx header might be (and will be in most cases) smaller than
2438                  * tx_max_header_size. But it's not an issue to send more data
2439                  * to the device, than actually needed if the mbuf size is
2440                  * greater than tx_max_header_size.
2441                  */
2442                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2443                 *header_len = push_len;
2444
2445                 if (likely(push_len <= seg_len)) {
2446                         /* If the push header is in the single segment, then
2447                          * just point it to the 1st mbuf data.
2448                          */
2449                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2450                 } else {
2451                         /* If the push header lays in the several segments, copy
2452                          * it to the intermediate buffer.
2453                          */
2454                         rte_pktmbuf_read(mbuf, 0, push_len,
2455                                 tx_ring->push_buf_intermediate_buf);
2456                         *push_header = tx_ring->push_buf_intermediate_buf;
2457                         delta = push_len - seg_len;
2458                 }
2459         } else {
2460                 *push_header = NULL;
2461                 *header_len = 0;
2462                 push_len = 0;
2463         }
2464
2465         /* Process first segment taking into consideration pushed header */
2466         if (seg_len > push_len) {
2467                 ena_buf->paddr = mbuf->buf_iova +
2468                                 mbuf->data_off +
2469                                 push_len;
2470                 ena_buf->len = seg_len - push_len;
2471                 ena_buf++;
2472                 tx_info->num_of_bufs++;
2473         }
2474
2475         while ((mbuf = mbuf->next) != NULL) {
2476                 seg_len = mbuf->data_len;
2477
2478                 /* Skip mbufs if whole data is pushed as a header */
2479                 if (unlikely(delta > seg_len)) {
2480                         delta -= seg_len;
2481                         continue;
2482                 }
2483
2484                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2485                 ena_buf->len = seg_len - delta;
2486                 ena_buf++;
2487                 tx_info->num_of_bufs++;
2488
2489                 delta = 0;
2490         }
2491 }
2492
2493 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2494 {
2495         struct ena_tx_buffer *tx_info;
2496         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2497         uint16_t next_to_use;
2498         uint16_t header_len;
2499         uint16_t req_id;
2500         void *push_header;
2501         int nb_hw_desc;
2502         int rc;
2503
2504         rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2505         if (unlikely(rc))
2506                 return rc;
2507
2508         next_to_use = tx_ring->next_to_use;
2509
2510         req_id = tx_ring->empty_tx_reqs[next_to_use];
2511         tx_info = &tx_ring->tx_buffer_info[req_id];
2512         tx_info->num_of_bufs = 0;
2513
2514         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2515
2516         ena_tx_ctx.ena_bufs = tx_info->bufs;
2517         ena_tx_ctx.push_header = push_header;
2518         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2519         ena_tx_ctx.req_id = req_id;
2520         ena_tx_ctx.header_len = header_len;
2521
2522         /* Set Tx offloads flags, if applicable */
2523         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2524                 tx_ring->disable_meta_caching);
2525
2526         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2527                         &ena_tx_ctx))) {
2528                 PMD_DRV_LOG(DEBUG,
2529                         "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2530                         tx_ring->id);
2531                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2532                 tx_ring->tx_stats.doorbells++;
2533                 tx_ring->pkts_without_db = false;
2534         }
2535
2536         /* prepare the packet's descriptors to dma engine */
2537         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2538                 &nb_hw_desc);
2539         if (unlikely(rc)) {
2540                 ++tx_ring->tx_stats.prepare_ctx_err;
2541                 return rc;
2542         }
2543
2544         tx_info->tx_descs = nb_hw_desc;
2545
2546         tx_ring->tx_stats.cnt++;
2547         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2548
2549         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2550                 tx_ring->size_mask);
2551
2552         return 0;
2553 }
2554
2555 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2556 {
2557         unsigned int cleanup_budget;
2558         unsigned int total_tx_descs = 0;
2559         uint16_t next_to_clean = tx_ring->next_to_clean;
2560
2561         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2562                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2563
2564         while (likely(total_tx_descs < cleanup_budget)) {
2565                 struct rte_mbuf *mbuf;
2566                 struct ena_tx_buffer *tx_info;
2567                 uint16_t req_id;
2568
2569                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2570                         break;
2571
2572                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2573                         break;
2574
2575                 /* Get Tx info & store how many descs were processed  */
2576                 tx_info = &tx_ring->tx_buffer_info[req_id];
2577
2578                 mbuf = tx_info->mbuf;
2579                 rte_pktmbuf_free(mbuf);
2580
2581                 tx_info->mbuf = NULL;
2582                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2583
2584                 total_tx_descs += tx_info->tx_descs;
2585
2586                 /* Put back descriptor to the ring for reuse */
2587                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2588                         tx_ring->size_mask);
2589         }
2590
2591         if (likely(total_tx_descs > 0)) {
2592                 /* acknowledge completion of sent packets */
2593                 tx_ring->next_to_clean = next_to_clean;
2594                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2595                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2596         }
2597 }
2598
2599 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2600                                   uint16_t nb_pkts)
2601 {
2602         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2603         uint16_t sent_idx = 0;
2604
2605         /* Check adapter state */
2606         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2607                 PMD_DRV_LOG(ALERT,
2608                         "Trying to xmit pkts while device is NOT running\n");
2609                 return 0;
2610         }
2611
2612         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2613                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2614                         break;
2615                 tx_ring->pkts_without_db = true;
2616                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2617                         tx_ring->size_mask)]);
2618         }
2619
2620         tx_ring->tx_stats.available_desc =
2621                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2622
2623         /* If there are ready packets to be xmitted... */
2624         if (likely(tx_ring->pkts_without_db)) {
2625                 /* ...let HW do its best :-) */
2626                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2627                 tx_ring->tx_stats.doorbells++;
2628                 tx_ring->pkts_without_db = false;
2629         }
2630
2631         ena_tx_cleanup(tx_ring);
2632
2633         tx_ring->tx_stats.available_desc =
2634                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2635         tx_ring->tx_stats.tx_poll++;
2636
2637         return sent_idx;
2638 }
2639
2640 int ena_copy_eni_stats(struct ena_adapter *adapter)
2641 {
2642         struct ena_admin_eni_stats admin_eni_stats;
2643         int rc;
2644
2645         rte_spinlock_lock(&adapter->admin_lock);
2646         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2647         rte_spinlock_unlock(&adapter->admin_lock);
2648         if (rc != 0) {
2649                 if (rc == ENA_COM_UNSUPPORTED) {
2650                         PMD_DRV_LOG(DEBUG,
2651                                 "Retrieving ENI metrics is not supported.\n");
2652                 } else {
2653                         PMD_DRV_LOG(WARNING,
2654                                 "Failed to get ENI metrics: %d\n", rc);
2655                 }
2656                 return rc;
2657         }
2658
2659         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2660                 sizeof(struct ena_stats_eni));
2661
2662         return 0;
2663 }
2664
2665 /**
2666  * DPDK callback to retrieve names of extended device statistics
2667  *
2668  * @param dev
2669  *   Pointer to Ethernet device structure.
2670  * @param[out] xstats_names
2671  *   Buffer to insert names into.
2672  * @param n
2673  *   Number of names.
2674  *
2675  * @return
2676  *   Number of xstats names.
2677  */
2678 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2679                                 struct rte_eth_xstat_name *xstats_names,
2680                                 unsigned int n)
2681 {
2682         unsigned int xstats_count = ena_xstats_calc_num(dev);
2683         unsigned int stat, i, count = 0;
2684
2685         if (n < xstats_count || !xstats_names)
2686                 return xstats_count;
2687
2688         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2689                 strcpy(xstats_names[count].name,
2690                         ena_stats_global_strings[stat].name);
2691
2692         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2693                 strcpy(xstats_names[count].name,
2694                         ena_stats_eni_strings[stat].name);
2695
2696         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2697                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2698                         snprintf(xstats_names[count].name,
2699                                 sizeof(xstats_names[count].name),
2700                                 "rx_q%d_%s", i,
2701                                 ena_stats_rx_strings[stat].name);
2702
2703         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2704                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2705                         snprintf(xstats_names[count].name,
2706                                 sizeof(xstats_names[count].name),
2707                                 "tx_q%d_%s", i,
2708                                 ena_stats_tx_strings[stat].name);
2709
2710         return xstats_count;
2711 }
2712
2713 /**
2714  * DPDK callback to get extended device statistics.
2715  *
2716  * @param dev
2717  *   Pointer to Ethernet device structure.
2718  * @param[out] stats
2719  *   Stats table output buffer.
2720  * @param n
2721  *   The size of the stats table.
2722  *
2723  * @return
2724  *   Number of xstats on success, negative on failure.
2725  */
2726 static int ena_xstats_get(struct rte_eth_dev *dev,
2727                           struct rte_eth_xstat *xstats,
2728                           unsigned int n)
2729 {
2730         struct ena_adapter *adapter = dev->data->dev_private;
2731         unsigned int xstats_count = ena_xstats_calc_num(dev);
2732         unsigned int stat, i, count = 0;
2733         int stat_offset;
2734         void *stats_begin;
2735
2736         if (n < xstats_count)
2737                 return xstats_count;
2738
2739         if (!xstats)
2740                 return 0;
2741
2742         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2743                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2744                 stats_begin = &adapter->dev_stats;
2745
2746                 xstats[count].id = count;
2747                 xstats[count].value = *((uint64_t *)
2748                         ((char *)stats_begin + stat_offset));
2749         }
2750
2751         /* Even if the function below fails, we should copy previous (or initial
2752          * values) to keep structure of rte_eth_xstat consistent.
2753          */
2754         ena_copy_eni_stats(adapter);
2755         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2756                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2757                 stats_begin = &adapter->eni_stats;
2758
2759                 xstats[count].id = count;
2760                 xstats[count].value = *((uint64_t *)
2761                     ((char *)stats_begin + stat_offset));
2762         }
2763
2764         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2765                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2766                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2767                         stats_begin = &adapter->rx_ring[i].rx_stats;
2768
2769                         xstats[count].id = count;
2770                         xstats[count].value = *((uint64_t *)
2771                                 ((char *)stats_begin + stat_offset));
2772                 }
2773         }
2774
2775         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2776                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2777                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2778                         stats_begin = &adapter->tx_ring[i].rx_stats;
2779
2780                         xstats[count].id = count;
2781                         xstats[count].value = *((uint64_t *)
2782                                 ((char *)stats_begin + stat_offset));
2783                 }
2784         }
2785
2786         return count;
2787 }
2788
2789 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2790                                 const uint64_t *ids,
2791                                 uint64_t *values,
2792                                 unsigned int n)
2793 {
2794         struct ena_adapter *adapter = dev->data->dev_private;
2795         uint64_t id;
2796         uint64_t rx_entries, tx_entries;
2797         unsigned int i;
2798         int qid;
2799         int valid = 0;
2800         bool was_eni_copied = false;
2801
2802         for (i = 0; i < n; ++i) {
2803                 id = ids[i];
2804                 /* Check if id belongs to global statistics */
2805                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2806                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2807                         ++valid;
2808                         continue;
2809                 }
2810
2811                 /* Check if id belongs to ENI statistics */
2812                 id -= ENA_STATS_ARRAY_GLOBAL;
2813                 if (id < ENA_STATS_ARRAY_ENI) {
2814                         /* Avoid reading ENI stats multiple times in a single
2815                          * function call, as it requires communication with the
2816                          * admin queue.
2817                          */
2818                         if (!was_eni_copied) {
2819                                 was_eni_copied = true;
2820                                 ena_copy_eni_stats(adapter);
2821                         }
2822                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2823                         ++valid;
2824                         continue;
2825                 }
2826
2827                 /* Check if id belongs to rx queue statistics */
2828                 id -= ENA_STATS_ARRAY_ENI;
2829                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2830                 if (id < rx_entries) {
2831                         qid = id % dev->data->nb_rx_queues;
2832                         id /= dev->data->nb_rx_queues;
2833                         values[i] = *((uint64_t *)
2834                                 &adapter->rx_ring[qid].rx_stats + id);
2835                         ++valid;
2836                         continue;
2837                 }
2838                                 /* Check if id belongs to rx queue statistics */
2839                 id -= rx_entries;
2840                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2841                 if (id < tx_entries) {
2842                         qid = id % dev->data->nb_tx_queues;
2843                         id /= dev->data->nb_tx_queues;
2844                         values[i] = *((uint64_t *)
2845                                 &adapter->tx_ring[qid].tx_stats + id);
2846                         ++valid;
2847                         continue;
2848                 }
2849         }
2850
2851         return valid;
2852 }
2853
2854 static int ena_process_bool_devarg(const char *key,
2855                                    const char *value,
2856                                    void *opaque)
2857 {
2858         struct ena_adapter *adapter = opaque;
2859         bool bool_value;
2860
2861         /* Parse the value. */
2862         if (strcmp(value, "1") == 0) {
2863                 bool_value = true;
2864         } else if (strcmp(value, "0") == 0) {
2865                 bool_value = false;
2866         } else {
2867                 PMD_INIT_LOG(ERR,
2868                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2869                         value, key);
2870                 return -EINVAL;
2871         }
2872
2873         /* Now, assign it to the proper adapter field. */
2874         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
2875                 adapter->use_large_llq_hdr = bool_value;
2876
2877         return 0;
2878 }
2879
2880 static int ena_parse_devargs(struct ena_adapter *adapter,
2881                              struct rte_devargs *devargs)
2882 {
2883         static const char * const allowed_args[] = {
2884                 ENA_DEVARG_LARGE_LLQ_HDR,
2885                 NULL,
2886         };
2887         struct rte_kvargs *kvlist;
2888         int rc;
2889
2890         if (devargs == NULL)
2891                 return 0;
2892
2893         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2894         if (kvlist == NULL) {
2895                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2896                         devargs->args);
2897                 return -EINVAL;
2898         }
2899
2900         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2901                 ena_process_bool_devarg, adapter);
2902
2903         rte_kvargs_free(kvlist);
2904
2905         return rc;
2906 }
2907
2908 /*********************************************************************
2909  *  PMD configuration
2910  *********************************************************************/
2911 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2912         struct rte_pci_device *pci_dev)
2913 {
2914         return rte_eth_dev_pci_generic_probe(pci_dev,
2915                 sizeof(struct ena_adapter), eth_ena_dev_init);
2916 }
2917
2918 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2919 {
2920         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2921 }
2922
2923 static struct rte_pci_driver rte_ena_pmd = {
2924         .id_table = pci_id_ena_map,
2925         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2926                      RTE_PCI_DRV_WC_ACTIVATE,
2927         .probe = eth_ena_pci_probe,
2928         .remove = eth_ena_pci_remove,
2929 };
2930
2931 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2932 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2933 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2934 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2935 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
2936 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
2937 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2938 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, NOTICE);
2939 #endif
2940 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2941 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, NOTICE);
2942 #endif
2943 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2944 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx_free, tx_free, NOTICE);
2945 #endif
2946 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2947 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, NOTICE);
2948 #endif
2949
2950 /******************************************************************************
2951  ******************************** AENQ Handlers *******************************
2952  *****************************************************************************/
2953 static void ena_update_on_link_change(void *adapter_data,
2954                                       struct ena_admin_aenq_entry *aenq_e)
2955 {
2956         struct rte_eth_dev *eth_dev;
2957         struct ena_adapter *adapter;
2958         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2959         uint32_t status;
2960
2961         adapter = adapter_data;
2962         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2963         eth_dev = adapter->rte_dev;
2964
2965         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2966         adapter->link_status = status;
2967
2968         ena_link_update(eth_dev, 0);
2969         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2970 }
2971
2972 static void ena_notification(void *data,
2973                              struct ena_admin_aenq_entry *aenq_e)
2974 {
2975         struct ena_adapter *adapter = data;
2976         struct ena_admin_ena_hw_hints *hints;
2977
2978         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2979                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2980                         aenq_e->aenq_common_desc.group,
2981                         ENA_ADMIN_NOTIFICATION);
2982
2983         switch (aenq_e->aenq_common_desc.syndrome) {
2984         case ENA_ADMIN_UPDATE_HINTS:
2985                 hints = (struct ena_admin_ena_hw_hints *)
2986                         (&aenq_e->inline_data_w4);
2987                 ena_update_hints(adapter, hints);
2988                 break;
2989         default:
2990                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2991                         aenq_e->aenq_common_desc.syndrome);
2992         }
2993 }
2994
2995 static void ena_keep_alive(void *adapter_data,
2996                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2997 {
2998         struct ena_adapter *adapter = adapter_data;
2999         struct ena_admin_aenq_keep_alive_desc *desc;
3000         uint64_t rx_drops;
3001         uint64_t tx_drops;
3002
3003         adapter->timestamp_wd = rte_get_timer_cycles();
3004
3005         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3006         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3007         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3008
3009         adapter->drv_stats->rx_drops = rx_drops;
3010         adapter->dev_stats.tx_drops = tx_drops;
3011 }
3012
3013 /**
3014  * This handler will called for unknown event group or unimplemented handlers
3015  **/
3016 static void unimplemented_aenq_handler(__rte_unused void *data,
3017                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3018 {
3019         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3020                           "unimplemented handler\n");
3021 }
3022
3023 static struct ena_aenq_handlers aenq_handlers = {
3024         .handlers = {
3025                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3026                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3027                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3028         },
3029         .unimplemented_handler = unimplemented_aenq_handler
3030 };