1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <rte_version.h>
10 #include <rte_kvargs.h>
12 #include "ena_ethdev.h"
14 #include "ena_platform.h"
16 #include "ena_eth_com.h"
18 #include <ena_common_defs.h>
19 #include <ena_regs_defs.h>
20 #include <ena_admin_defs.h>
21 #include <ena_eth_io_defs.h>
23 #define DRV_MODULE_VER_MAJOR 2
24 #define DRV_MODULE_VER_MINOR 5
25 #define DRV_MODULE_VER_SUBMINOR 0
27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
29 #define GET_L4_HDR_LEN(mbuf) \
30 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
31 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
33 #define ETH_GSTRING_LEN 32
35 #define ARRAY_SIZE(x) RTE_DIM(x)
37 #define ENA_MIN_RING_DESC 128
39 #define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
42 char name[ETH_GSTRING_LEN];
46 #define ENA_STAT_ENTRY(stat, stat_type) { \
48 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
51 #define ENA_STAT_RX_ENTRY(stat) \
52 ENA_STAT_ENTRY(stat, rx)
54 #define ENA_STAT_TX_ENTRY(stat) \
55 ENA_STAT_ENTRY(stat, tx)
57 #define ENA_STAT_ENI_ENTRY(stat) \
58 ENA_STAT_ENTRY(stat, eni)
60 #define ENA_STAT_GLOBAL_ENTRY(stat) \
61 ENA_STAT_ENTRY(stat, dev)
63 /* Device arguments */
64 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
65 /* Timeout in seconds after which a single uncompleted Tx packet should be
66 * considered as a missing.
68 #define ENA_DEVARG_MISS_TXC_TO "miss_txc_to"
71 * Each rte_memzone should have unique name.
72 * To satisfy it, count number of allocation and add it to name.
74 rte_atomic64_t ena_alloc_cnt;
76 static const struct ena_stats ena_stats_global_strings[] = {
77 ENA_STAT_GLOBAL_ENTRY(wd_expired),
78 ENA_STAT_GLOBAL_ENTRY(dev_start),
79 ENA_STAT_GLOBAL_ENTRY(dev_stop),
80 ENA_STAT_GLOBAL_ENTRY(tx_drops),
83 static const struct ena_stats ena_stats_eni_strings[] = {
84 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
85 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
86 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
87 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
88 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
91 static const struct ena_stats ena_stats_tx_strings[] = {
92 ENA_STAT_TX_ENTRY(cnt),
93 ENA_STAT_TX_ENTRY(bytes),
94 ENA_STAT_TX_ENTRY(prepare_ctx_err),
95 ENA_STAT_TX_ENTRY(tx_poll),
96 ENA_STAT_TX_ENTRY(doorbells),
97 ENA_STAT_TX_ENTRY(bad_req_id),
98 ENA_STAT_TX_ENTRY(available_desc),
99 ENA_STAT_TX_ENTRY(missed_tx),
102 static const struct ena_stats ena_stats_rx_strings[] = {
103 ENA_STAT_RX_ENTRY(cnt),
104 ENA_STAT_RX_ENTRY(bytes),
105 ENA_STAT_RX_ENTRY(refill_partial),
106 ENA_STAT_RX_ENTRY(l3_csum_bad),
107 ENA_STAT_RX_ENTRY(l4_csum_bad),
108 ENA_STAT_RX_ENTRY(l4_csum_good),
109 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
110 ENA_STAT_RX_ENTRY(bad_desc_num),
111 ENA_STAT_RX_ENTRY(bad_req_id),
114 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
115 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings)
116 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
117 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
119 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
120 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
121 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
122 RTE_ETH_TX_OFFLOAD_TCP_TSO)
123 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
124 RTE_MBUF_F_TX_IP_CKSUM |\
125 RTE_MBUF_F_TX_TCP_SEG)
127 /** Vendor ID used by Amazon devices */
128 #define PCI_VENDOR_ID_AMAZON 0x1D0F
129 /** Amazon devices */
130 #define PCI_DEVICE_ID_ENA_VF 0xEC20
131 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21
133 #define ENA_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_L4_MASK | \
134 RTE_MBUF_F_TX_IPV6 | \
135 RTE_MBUF_F_TX_IPV4 | \
136 RTE_MBUF_F_TX_IP_CKSUM | \
137 RTE_MBUF_F_TX_TCP_SEG)
139 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
140 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
142 /** HW specific offloads capabilities. */
143 /* IPv4 checksum offload. */
144 #define ENA_L3_IPV4_CSUM 0x0001
145 /* TCP/UDP checksum offload for IPv4 packets. */
146 #define ENA_L4_IPV4_CSUM 0x0002
147 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
148 #define ENA_L4_IPV4_CSUM_PARTIAL 0x0004
149 /* TCP/UDP checksum offload for IPv6 packets. */
150 #define ENA_L4_IPV6_CSUM 0x0008
151 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
152 #define ENA_L4_IPV6_CSUM_PARTIAL 0x0010
153 /* TSO support for IPv4 packets. */
154 #define ENA_IPV4_TSO 0x0020
156 /* Device supports setting RSS hash. */
157 #define ENA_RX_RSS_HASH 0x0040
159 static const struct rte_pci_id pci_id_ena_map[] = {
160 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
161 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
165 static struct ena_aenq_handlers aenq_handlers;
167 static int ena_device_init(struct ena_adapter *adapter,
168 struct rte_pci_device *pdev,
169 struct ena_com_dev_get_features_ctx *get_feat_ctx);
170 static int ena_dev_configure(struct rte_eth_dev *dev);
171 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
172 struct ena_tx_buffer *tx_info,
173 struct rte_mbuf *mbuf,
175 uint16_t *header_len);
176 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
177 static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt);
178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
183 uint16_t nb_desc, unsigned int socket_id,
184 const struct rte_eth_txconf *tx_conf);
185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
186 uint16_t nb_desc, unsigned int socket_id,
187 const struct rte_eth_rxconf *rx_conf,
188 struct rte_mempool *mp);
189 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
190 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
191 struct ena_com_rx_buf_info *ena_bufs,
193 uint16_t *next_to_clean,
195 static uint16_t eth_ena_recv_pkts(void *rx_queue,
196 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
197 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
198 struct rte_mbuf *mbuf, uint16_t id);
199 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
200 static void ena_init_rings(struct ena_adapter *adapter,
201 bool disable_meta_caching);
202 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
203 static int ena_start(struct rte_eth_dev *dev);
204 static int ena_stop(struct rte_eth_dev *dev);
205 static int ena_close(struct rte_eth_dev *dev);
206 static int ena_dev_reset(struct rte_eth_dev *dev);
207 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
208 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
209 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
210 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
211 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
212 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
213 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
214 static int ena_link_update(struct rte_eth_dev *dev,
215 int wait_to_complete);
216 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
217 static void ena_queue_stop(struct ena_ring *ring);
218 static void ena_queue_stop_all(struct rte_eth_dev *dev,
219 enum ena_ring_type ring_type);
220 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
221 static int ena_queue_start_all(struct rte_eth_dev *dev,
222 enum ena_ring_type ring_type);
223 static void ena_stats_restart(struct rte_eth_dev *dev);
224 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
225 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
226 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
227 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
228 static int ena_infos_get(struct rte_eth_dev *dev,
229 struct rte_eth_dev_info *dev_info);
230 static void ena_interrupt_handler_rte(void *cb_arg);
231 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
232 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
233 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
234 static int ena_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static int ena_xstats_get_names_by_id(struct rte_eth_dev *dev,
239 struct rte_eth_xstat_name *xstats_names,
241 static int ena_xstats_get(struct rte_eth_dev *dev,
242 struct rte_eth_xstat *stats,
244 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
248 static int ena_process_bool_devarg(const char *key,
251 static int ena_parse_devargs(struct ena_adapter *adapter,
252 struct rte_devargs *devargs);
253 static int ena_copy_eni_stats(struct ena_adapter *adapter,
254 struct ena_stats_eni *stats);
255 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
256 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
258 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
260 static int ena_configure_aenq(struct ena_adapter *adapter);
261 static int ena_mp_primary_handle(const struct rte_mp_msg *mp_msg,
264 static const struct eth_dev_ops ena_dev_ops = {
265 .dev_configure = ena_dev_configure,
266 .dev_infos_get = ena_infos_get,
267 .rx_queue_setup = ena_rx_queue_setup,
268 .tx_queue_setup = ena_tx_queue_setup,
269 .dev_start = ena_start,
270 .dev_stop = ena_stop,
271 .link_update = ena_link_update,
272 .stats_get = ena_stats_get,
273 .xstats_get_names = ena_xstats_get_names,
274 .xstats_get_names_by_id = ena_xstats_get_names_by_id,
275 .xstats_get = ena_xstats_get,
276 .xstats_get_by_id = ena_xstats_get_by_id,
277 .mtu_set = ena_mtu_set,
278 .rx_queue_release = ena_rx_queue_release,
279 .tx_queue_release = ena_tx_queue_release,
280 .dev_close = ena_close,
281 .dev_reset = ena_dev_reset,
282 .reta_update = ena_rss_reta_update,
283 .reta_query = ena_rss_reta_query,
284 .rx_queue_intr_enable = ena_rx_queue_intr_enable,
285 .rx_queue_intr_disable = ena_rx_queue_intr_disable,
286 .rss_hash_update = ena_rss_hash_update,
287 .rss_hash_conf_get = ena_rss_hash_conf_get,
288 .tx_done_cleanup = ena_tx_cleanup,
291 /*********************************************************************
292 * Multi-Process communication bits
293 *********************************************************************/
294 /* rte_mp IPC message name */
295 #define ENA_MP_NAME "net_ena_mp"
296 /* Request timeout in seconds */
297 #define ENA_MP_REQ_TMO 5
299 /** Proxy request type */
301 ENA_MP_DEV_STATS_GET,
302 ENA_MP_ENI_STATS_GET,
308 /** Proxy message body. Shared between requests and responses. */
311 enum ena_mp_req type;
313 /* Processing result. Set in replies. 0 if message succeeded, negative
314 * error code otherwise.
318 int mtu; /* For ENA_MP_MTU_SET */
323 * Initialize IPC message.
326 * Pointer to the message to initialize.
330 * Port ID of target device.
334 mp_msg_init(struct rte_mp_msg *msg, enum ena_mp_req type, int port_id)
336 struct ena_mp_body *body = (struct ena_mp_body *)&msg->param;
338 memset(msg, 0, sizeof(*msg));
339 strlcpy(msg->name, ENA_MP_NAME, sizeof(msg->name));
340 msg->len_param = sizeof(*body);
342 body->port_id = port_id;
345 /*********************************************************************
346 * Multi-Process communication PMD API
347 *********************************************************************/
349 * Define proxy request descriptor
351 * Used to define all structures and functions required for proxying a given
352 * function to the primary process including the code to perform to prepare the
353 * request and process the response.
356 * Name of the function to proxy
358 * Message type to use
360 * Body of a function to prepare the request in form of a statement
361 * expression. It is passed all the original function arguments along with two
363 * - struct ena_adapter *adapter - PMD data of the device calling the proxy.
364 * - struct ena_mp_body *req - body of a request to prepare.
366 * Body of a function to process the response in form of a statement
367 * expression. It is passed all the original function arguments along with two
369 * - struct ena_adapter *adapter - PMD data of the device calling the proxy.
370 * - struct ena_mp_body *rsp - body of a response to process.
372 * Proxied function's arguments
374 * @note Inside prep and proc any parameters which aren't used should be marked
375 * as such (with ENA_TOUCH or __rte_unused).
377 #define ENA_PROXY_DESC(f, t, prep, proc, ...) \
378 static const enum ena_mp_req mp_type_ ## f = t; \
379 static const char *mp_name_ ## f = #t; \
380 static void mp_prep_ ## f(struct ena_adapter *adapter, \
381 struct ena_mp_body *req, \
386 static void mp_proc_ ## f(struct ena_adapter *adapter, \
387 struct ena_mp_body *rsp, \
394 * Proxy wrapper for calling primary functions in a secondary process.
396 * Depending on whether called in primary or secondary process, calls the
397 * @p func directly or proxies the call to the primary process via rte_mp IPC.
398 * This macro requires a proxy request descriptor to be defined for @p func
399 * using ENA_PROXY_DESC() macro.
402 * Device PMD data. Used for sending the message and sharing message results
403 * between primary and secondary.
407 * Arguments of @p func.
410 * - 0: Processing succeeded and response handler was called.
411 * - -EPERM: IPC is unavailable on this platform. This means only primary
412 * process may call the proxied function.
413 * - -EIO: IPC returned error on request send. Inspect rte_errno detailed
415 * - Negative error code from the proxied function.
417 * @note This mechanism is geared towards control-path tasks. Avoid calling it
418 * in fast-path unless unbound delays are allowed. This is due to the IPC
419 * mechanism itself (socket based).
420 * @note Due to IPC parameter size limitations the proxy logic shares call
421 * results through the struct ena_adapter shared memory. This makes the
422 * proxy mechanism strictly single-threaded. Therefore be sure to make all
423 * calls to the same proxied function under the same lock.
425 #define ENA_PROXY(a, f, ...) \
427 struct ena_adapter *_a = (a); \
428 struct timespec ts = { .tv_sec = ENA_MP_REQ_TMO }; \
429 struct ena_mp_body *req, *rsp; \
430 struct rte_mp_reply mp_rep; \
431 struct rte_mp_msg mp_req; \
434 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { \
435 ret = f(__VA_ARGS__); \
437 /* Prepare and send request */ \
438 req = (struct ena_mp_body *)&mp_req.param; \
439 mp_msg_init(&mp_req, mp_type_ ## f, _a->edev_data->port_id); \
440 mp_prep_ ## f(_a, req, ## __VA_ARGS__); \
442 ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts); \
443 if (likely(!ret)) { \
444 RTE_ASSERT(mp_rep.nb_received == 1); \
445 rsp = (struct ena_mp_body *)&mp_rep.msgs[0].param; \
448 mp_proc_##f(_a, rsp, ## __VA_ARGS__); \
451 "%s returned error: %d\n", \
452 mp_name_ ## f, rsp->result);\
455 } else if (rte_errno == ENOTSUP) { \
457 "No IPC, can't proxy to primary\n");\
460 PMD_DRV_LOG(ERR, "Request %s failed: %s\n", \
462 rte_strerror(rte_errno)); \
469 /*********************************************************************
470 * Multi-Process communication request descriptors
471 *********************************************************************/
473 ENA_PROXY_DESC(ena_com_get_dev_basic_stats, ENA_MP_DEV_STATS_GET,
483 if (stats != &adapter->basic_stats)
484 rte_memcpy(stats, &adapter->basic_stats, sizeof(*stats));
486 struct ena_com_dev *ena_dev, struct ena_admin_basic_stats *stats);
488 ENA_PROXY_DESC(ena_com_get_eni_stats, ENA_MP_ENI_STATS_GET,
498 if (stats != (struct ena_admin_eni_stats *)&adapter->eni_stats)
499 rte_memcpy(stats, &adapter->eni_stats, sizeof(*stats));
501 struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats);
503 ENA_PROXY_DESC(ena_com_set_dev_mtu, ENA_MP_MTU_SET,
515 struct ena_com_dev *ena_dev, int mtu);
517 ENA_PROXY_DESC(ena_com_indirect_table_set, ENA_MP_IND_TBL_SET,
528 struct ena_com_dev *ena_dev);
530 ENA_PROXY_DESC(ena_com_indirect_table_get, ENA_MP_IND_TBL_GET,
540 if (ind_tbl != adapter->indirect_table)
541 rte_memcpy(ind_tbl, adapter->indirect_table,
542 sizeof(adapter->indirect_table));
544 struct ena_com_dev *ena_dev, u32 *ind_tbl);
546 static inline void ena_trigger_reset(struct ena_adapter *adapter,
547 enum ena_regs_reset_reason_types reason)
549 if (likely(!adapter->trigger_reset)) {
550 adapter->reset_reason = reason;
551 adapter->trigger_reset = true;
555 static inline void ena_rx_mbuf_prepare(struct ena_ring *rx_ring,
556 struct rte_mbuf *mbuf,
557 struct ena_com_rx_ctx *ena_rx_ctx,
560 struct ena_stats_rx *rx_stats = &rx_ring->rx_stats;
561 uint64_t ol_flags = 0;
562 uint32_t packet_type = 0;
564 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
565 packet_type |= RTE_PTYPE_L4_TCP;
566 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
567 packet_type |= RTE_PTYPE_L4_UDP;
569 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
570 packet_type |= RTE_PTYPE_L3_IPV4;
571 if (unlikely(ena_rx_ctx->l3_csum_err)) {
572 ++rx_stats->l3_csum_bad;
573 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
575 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
577 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
578 packet_type |= RTE_PTYPE_L3_IPV6;
581 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) {
582 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
584 if (unlikely(ena_rx_ctx->l4_csum_err)) {
585 ++rx_stats->l4_csum_bad;
586 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
588 ++rx_stats->l4_csum_good;
589 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
594 likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
595 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
596 mbuf->hash.rss = ena_rx_ctx->hash;
599 mbuf->ol_flags = ol_flags;
600 mbuf->packet_type = packet_type;
603 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
604 struct ena_com_tx_ctx *ena_tx_ctx,
605 uint64_t queue_offloads,
606 bool disable_meta_caching)
608 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
610 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
611 (queue_offloads & QUEUE_OFFLOADS)) {
612 /* check if TSO is required */
613 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
614 (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
615 ena_tx_ctx->tso_enable = true;
617 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
620 /* check if L3 checksum is needed */
621 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
622 (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
623 ena_tx_ctx->l3_csum_enable = true;
625 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
626 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
627 /* For the IPv6 packets, DF always needs to be true. */
630 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
632 /* set don't fragment (DF) flag */
633 if (mbuf->packet_type &
634 (RTE_PTYPE_L4_NONFRAG
635 | RTE_PTYPE_INNER_L4_NONFRAG))
639 /* check if L4 checksum is needed */
640 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
641 (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
642 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
643 ena_tx_ctx->l4_csum_enable = true;
644 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
645 RTE_MBUF_F_TX_UDP_CKSUM) &&
646 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
647 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
648 ena_tx_ctx->l4_csum_enable = true;
650 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
651 ena_tx_ctx->l4_csum_enable = false;
654 ena_meta->mss = mbuf->tso_segsz;
655 ena_meta->l3_hdr_len = mbuf->l3_len;
656 ena_meta->l3_hdr_offset = mbuf->l2_len;
658 ena_tx_ctx->meta_valid = true;
659 } else if (disable_meta_caching) {
660 memset(ena_meta, 0, sizeof(*ena_meta));
661 ena_tx_ctx->meta_valid = true;
663 ena_tx_ctx->meta_valid = false;
667 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
669 struct ena_tx_buffer *tx_info = NULL;
671 if (likely(req_id < tx_ring->ring_size)) {
672 tx_info = &tx_ring->tx_buffer_info[req_id];
673 if (likely(tx_info->mbuf))
678 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
680 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
682 /* Trigger device reset */
683 ++tx_ring->tx_stats.bad_req_id;
684 ena_trigger_reset(tx_ring->adapter, ENA_REGS_RESET_INV_TX_REQ_ID);
688 static void ena_config_host_info(struct ena_com_dev *ena_dev)
690 struct ena_admin_host_info *host_info;
693 /* Allocate only the host info */
694 rc = ena_com_allocate_host_info(ena_dev);
696 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
700 host_info = ena_dev->host_attr.host_info;
702 host_info->os_type = ENA_ADMIN_OS_DPDK;
703 host_info->kernel_ver = RTE_VERSION;
704 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
705 sizeof(host_info->kernel_ver_str));
706 host_info->os_dist = RTE_VERSION;
707 strlcpy((char *)host_info->os_dist_str, rte_version(),
708 sizeof(host_info->os_dist_str));
709 host_info->driver_version =
710 (DRV_MODULE_VER_MAJOR) |
711 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
712 (DRV_MODULE_VER_SUBMINOR <<
713 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
714 host_info->num_cpus = rte_lcore_count();
716 host_info->driver_supported_features =
717 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
718 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
720 rc = ena_com_set_host_attributes(ena_dev);
722 if (rc == -ENA_COM_UNSUPPORTED)
723 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
725 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
733 ena_com_delete_host_info(ena_dev);
736 /* This function calculates the number of xstats based on the current config */
737 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
739 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
740 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
741 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
744 static void ena_config_debug_area(struct ena_adapter *adapter)
749 ss_count = ena_xstats_calc_num(adapter->edev_data);
751 /* allocate 32 bytes for each string and 64bit for the value */
752 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
754 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
756 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
760 rc = ena_com_set_host_attributes(&adapter->ena_dev);
762 if (rc == -ENA_COM_UNSUPPORTED)
763 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
765 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
772 ena_com_delete_debug_area(&adapter->ena_dev);
775 static int ena_close(struct rte_eth_dev *dev)
777 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
778 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
779 struct ena_adapter *adapter = dev->data->dev_private;
782 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
785 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
787 adapter->state = ENA_ADAPTER_STATE_CLOSED;
789 ena_rx_queue_release_all(dev);
790 ena_tx_queue_release_all(dev);
792 rte_free(adapter->drv_stats);
793 adapter->drv_stats = NULL;
795 rte_intr_disable(intr_handle);
796 rte_intr_callback_unregister(intr_handle,
797 ena_interrupt_handler_rte,
801 * MAC is not allocated dynamically. Setting NULL should prevent from
802 * release of the resource in the rte_eth_dev_release_port().
804 dev->data->mac_addrs = NULL;
810 ena_dev_reset(struct rte_eth_dev *dev)
814 /* Cannot release memory in secondary process */
815 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
816 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
820 ena_destroy_device(dev);
821 rc = eth_ena_dev_init(dev);
823 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
828 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
830 int nb_queues = dev->data->nb_rx_queues;
833 for (i = 0; i < nb_queues; i++)
834 ena_rx_queue_release(dev, i);
837 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
839 int nb_queues = dev->data->nb_tx_queues;
842 for (i = 0; i < nb_queues; i++)
843 ena_tx_queue_release(dev, i);
846 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
848 struct ena_ring *ring = dev->data->rx_queues[qid];
850 /* Free ring resources */
851 rte_free(ring->rx_buffer_info);
852 ring->rx_buffer_info = NULL;
854 rte_free(ring->rx_refill_buffer);
855 ring->rx_refill_buffer = NULL;
857 rte_free(ring->empty_rx_reqs);
858 ring->empty_rx_reqs = NULL;
860 ring->configured = 0;
862 PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
863 ring->port_id, ring->id);
866 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
868 struct ena_ring *ring = dev->data->tx_queues[qid];
870 /* Free ring resources */
871 rte_free(ring->push_buf_intermediate_buf);
873 rte_free(ring->tx_buffer_info);
875 rte_free(ring->empty_tx_reqs);
877 ring->empty_tx_reqs = NULL;
878 ring->tx_buffer_info = NULL;
879 ring->push_buf_intermediate_buf = NULL;
881 ring->configured = 0;
883 PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
884 ring->port_id, ring->id);
887 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
891 for (i = 0; i < ring->ring_size; ++i) {
892 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
894 rte_mbuf_raw_free(rx_info->mbuf);
895 rx_info->mbuf = NULL;
900 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
904 for (i = 0; i < ring->ring_size; ++i) {
905 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
908 rte_pktmbuf_free(tx_buf->mbuf);
914 static int ena_link_update(struct rte_eth_dev *dev,
915 __rte_unused int wait_to_complete)
917 struct rte_eth_link *link = &dev->data->dev_link;
918 struct ena_adapter *adapter = dev->data->dev_private;
920 link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
921 link->link_speed = RTE_ETH_SPEED_NUM_NONE;
922 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
927 static int ena_queue_start_all(struct rte_eth_dev *dev,
928 enum ena_ring_type ring_type)
930 struct ena_adapter *adapter = dev->data->dev_private;
931 struct ena_ring *queues = NULL;
936 if (ring_type == ENA_RING_TYPE_RX) {
937 queues = adapter->rx_ring;
938 nb_queues = dev->data->nb_rx_queues;
940 queues = adapter->tx_ring;
941 nb_queues = dev->data->nb_tx_queues;
943 for (i = 0; i < nb_queues; i++) {
944 if (queues[i].configured) {
945 if (ring_type == ENA_RING_TYPE_RX) {
947 dev->data->rx_queues[i] == &queues[i],
948 "Inconsistent state of Rx queues\n");
951 dev->data->tx_queues[i] == &queues[i],
952 "Inconsistent state of Tx queues\n");
955 rc = ena_queue_start(dev, &queues[i]);
959 "Failed to start queue[%d] of type(%d)\n",
970 if (queues[i].configured)
971 ena_queue_stop(&queues[i]);
976 static int ena_check_valid_conf(struct ena_adapter *adapter)
978 uint32_t mtu = adapter->edev_data->mtu;
980 if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
982 "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
983 mtu, adapter->max_mtu, ENA_MIN_MTU);
984 return ENA_COM_UNSUPPORTED;
991 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
992 bool use_large_llq_hdr)
994 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
995 struct ena_com_dev *ena_dev = ctx->ena_dev;
996 uint32_t max_tx_queue_size;
997 uint32_t max_rx_queue_size;
999 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1000 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1001 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
1002 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
1003 max_queue_ext->max_rx_sq_depth);
1004 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
1006 if (ena_dev->tx_mem_queue_type ==
1007 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1008 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1009 llq->max_llq_depth);
1011 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1012 max_queue_ext->max_tx_sq_depth);
1015 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1016 max_queue_ext->max_per_packet_rx_descs);
1017 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1018 max_queue_ext->max_per_packet_tx_descs);
1020 struct ena_admin_queue_feature_desc *max_queues =
1021 &ctx->get_feat_ctx->max_queues;
1022 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
1023 max_queues->max_sq_depth);
1024 max_tx_queue_size = max_queues->max_cq_depth;
1026 if (ena_dev->tx_mem_queue_type ==
1027 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1028 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1029 llq->max_llq_depth);
1031 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1032 max_queues->max_sq_depth);
1035 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1036 max_queues->max_packet_rx_descs);
1037 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1038 max_queues->max_packet_tx_descs);
1041 /* Round down to the nearest power of 2 */
1042 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
1043 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
1045 if (use_large_llq_hdr) {
1046 if ((llq->entry_size_ctrl_supported &
1047 ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
1048 (ena_dev->tx_mem_queue_type ==
1049 ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
1050 max_tx_queue_size /= 2;
1052 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
1056 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
1060 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
1061 PMD_INIT_LOG(ERR, "Invalid queue size\n");
1065 ctx->max_tx_queue_size = max_tx_queue_size;
1066 ctx->max_rx_queue_size = max_rx_queue_size;
1071 static void ena_stats_restart(struct rte_eth_dev *dev)
1073 struct ena_adapter *adapter = dev->data->dev_private;
1075 rte_atomic64_init(&adapter->drv_stats->ierrors);
1076 rte_atomic64_init(&adapter->drv_stats->oerrors);
1077 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
1078 adapter->drv_stats->rx_drops = 0;
1081 static int ena_stats_get(struct rte_eth_dev *dev,
1082 struct rte_eth_stats *stats)
1084 struct ena_admin_basic_stats ena_stats;
1085 struct ena_adapter *adapter = dev->data->dev_private;
1086 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1089 int max_rings_stats;
1091 memset(&ena_stats, 0, sizeof(ena_stats));
1093 rte_spinlock_lock(&adapter->admin_lock);
1094 rc = ENA_PROXY(adapter, ena_com_get_dev_basic_stats, ena_dev,
1096 rte_spinlock_unlock(&adapter->admin_lock);
1098 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
1102 /* Set of basic statistics from ENA */
1103 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1104 ena_stats.rx_pkts_low);
1105 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1106 ena_stats.tx_pkts_low);
1107 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1108 ena_stats.rx_bytes_low);
1109 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1110 ena_stats.tx_bytes_low);
1112 /* Driver related stats */
1113 stats->imissed = adapter->drv_stats->rx_drops;
1114 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1115 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1116 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1118 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1119 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1120 for (i = 0; i < max_rings_stats; ++i) {
1121 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1123 stats->q_ibytes[i] = rx_stats->bytes;
1124 stats->q_ipackets[i] = rx_stats->cnt;
1125 stats->q_errors[i] = rx_stats->bad_desc_num +
1126 rx_stats->bad_req_id;
1129 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1130 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1131 for (i = 0; i < max_rings_stats; ++i) {
1132 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1134 stats->q_obytes[i] = tx_stats->bytes;
1135 stats->q_opackets[i] = tx_stats->cnt;
1141 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1143 struct ena_adapter *adapter;
1144 struct ena_com_dev *ena_dev;
1147 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1148 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1149 adapter = dev->data->dev_private;
1151 ena_dev = &adapter->ena_dev;
1152 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1154 if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
1156 "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
1157 mtu, adapter->max_mtu, ENA_MIN_MTU);
1161 rc = ENA_PROXY(adapter, ena_com_set_dev_mtu, ena_dev, mtu);
1163 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1165 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
1170 static int ena_start(struct rte_eth_dev *dev)
1172 struct ena_adapter *adapter = dev->data->dev_private;
1176 /* Cannot allocate memory in secondary process */
1177 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1178 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
1182 rc = ena_check_valid_conf(adapter);
1186 rc = ena_setup_rx_intr(dev);
1190 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1194 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1198 if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
1199 rc = ena_rss_configure(adapter);
1204 ena_stats_restart(dev);
1206 adapter->timestamp_wd = rte_get_timer_cycles();
1207 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1209 ticks = rte_get_timer_hz();
1210 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1211 ena_timer_wd_callback, dev);
1213 ++adapter->dev_stats.dev_start;
1214 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1219 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1221 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1225 static int ena_stop(struct rte_eth_dev *dev)
1227 struct ena_adapter *adapter = dev->data->dev_private;
1228 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1229 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1230 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1233 /* Cannot free memory in secondary process */
1234 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1235 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
1239 rte_timer_stop_sync(&adapter->timer_wd);
1240 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1241 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1243 if (adapter->trigger_reset) {
1244 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1246 PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
1249 rte_intr_disable(intr_handle);
1251 rte_intr_efd_disable(intr_handle);
1253 /* Cleanup vector list */
1254 rte_intr_vec_list_free(intr_handle);
1256 rte_intr_enable(intr_handle);
1258 ++adapter->dev_stats.dev_stop;
1259 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1260 dev->data->dev_started = 0;
1265 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
1267 struct ena_adapter *adapter = ring->adapter;
1268 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1269 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1270 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1271 struct ena_com_create_io_ctx ctx =
1272 /* policy set to _HOST just to satisfy icc compiler */
1273 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1279 ctx.msix_vector = -1;
1280 if (ring->type == ENA_RING_TYPE_TX) {
1281 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1282 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1283 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1284 for (i = 0; i < ring->ring_size; i++)
1285 ring->empty_tx_reqs[i] = i;
1287 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1288 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1289 if (rte_intr_dp_is_en(intr_handle))
1291 rte_intr_vec_list_index_get(intr_handle,
1294 for (i = 0; i < ring->ring_size; i++)
1295 ring->empty_rx_reqs[i] = i;
1297 ctx.queue_size = ring->ring_size;
1299 ctx.numa_node = ring->numa_socket_id;
1301 rc = ena_com_create_io_queue(ena_dev, &ctx);
1304 "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1305 ring->id, ena_qid, rc);
1309 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1310 &ring->ena_com_io_sq,
1311 &ring->ena_com_io_cq);
1314 "Failed to get IO queue[%d] handlers, rc: %d\n",
1316 ena_com_destroy_io_queue(ena_dev, ena_qid);
1320 if (ring->type == ENA_RING_TYPE_TX)
1321 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1323 /* Start with Rx interrupts being masked. */
1324 if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1325 ena_rx_queue_intr_disable(dev, ring->id);
1330 static void ena_queue_stop(struct ena_ring *ring)
1332 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1334 if (ring->type == ENA_RING_TYPE_RX) {
1335 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1336 ena_rx_queue_release_bufs(ring);
1338 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1339 ena_tx_queue_release_bufs(ring);
1343 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1344 enum ena_ring_type ring_type)
1346 struct ena_adapter *adapter = dev->data->dev_private;
1347 struct ena_ring *queues = NULL;
1348 uint16_t nb_queues, i;
1350 if (ring_type == ENA_RING_TYPE_RX) {
1351 queues = adapter->rx_ring;
1352 nb_queues = dev->data->nb_rx_queues;
1354 queues = adapter->tx_ring;
1355 nb_queues = dev->data->nb_tx_queues;
1358 for (i = 0; i < nb_queues; ++i)
1359 if (queues[i].configured)
1360 ena_queue_stop(&queues[i]);
1363 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1367 ena_assert_msg(ring->configured == 1,
1368 "Trying to start unconfigured queue\n");
1370 rc = ena_create_io_queue(dev, ring);
1372 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1376 ring->next_to_clean = 0;
1377 ring->next_to_use = 0;
1379 if (ring->type == ENA_RING_TYPE_TX) {
1380 ring->tx_stats.available_desc =
1381 ena_com_free_q_entries(ring->ena_com_io_sq);
1385 bufs_num = ring->ring_size - 1;
1386 rc = ena_populate_rx_queue(ring, bufs_num);
1387 if (rc != bufs_num) {
1388 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1389 ENA_IO_RXQ_IDX(ring->id));
1390 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1391 return ENA_COM_FAULT;
1393 /* Flush per-core RX buffers pools cache as they can be used on other
1396 rte_mempool_cache_flush(NULL, ring->mb_pool);
1401 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1404 unsigned int socket_id,
1405 const struct rte_eth_txconf *tx_conf)
1407 struct ena_ring *txq = NULL;
1408 struct ena_adapter *adapter = dev->data->dev_private;
1410 uint16_t dyn_thresh;
1412 txq = &adapter->tx_ring[queue_idx];
1414 if (txq->configured) {
1416 "API violation. Queue[%d] is already configured\n",
1418 return ENA_COM_FAULT;
1421 if (!rte_is_power_of_2(nb_desc)) {
1423 "Unsupported size of Tx queue: %d is not a power of 2.\n",
1428 if (nb_desc > adapter->max_tx_ring_size) {
1430 "Unsupported size of Tx queue (max size: %d)\n",
1431 adapter->max_tx_ring_size);
1435 txq->port_id = dev->data->port_id;
1436 txq->next_to_clean = 0;
1437 txq->next_to_use = 0;
1438 txq->ring_size = nb_desc;
1439 txq->size_mask = nb_desc - 1;
1440 txq->numa_socket_id = socket_id;
1441 txq->pkts_without_db = false;
1442 txq->last_cleanup_ticks = 0;
1444 txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1445 sizeof(struct ena_tx_buffer) * txq->ring_size,
1446 RTE_CACHE_LINE_SIZE,
1448 if (!txq->tx_buffer_info) {
1450 "Failed to allocate memory for Tx buffer info\n");
1454 txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1455 sizeof(uint16_t) * txq->ring_size,
1456 RTE_CACHE_LINE_SIZE,
1458 if (!txq->empty_tx_reqs) {
1460 "Failed to allocate memory for empty Tx requests\n");
1461 rte_free(txq->tx_buffer_info);
1465 txq->push_buf_intermediate_buf =
1466 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1467 txq->tx_max_header_size,
1468 RTE_CACHE_LINE_SIZE,
1470 if (!txq->push_buf_intermediate_buf) {
1471 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1472 rte_free(txq->tx_buffer_info);
1473 rte_free(txq->empty_tx_reqs);
1477 for (i = 0; i < txq->ring_size; i++)
1478 txq->empty_tx_reqs[i] = i;
1480 txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1482 /* Check if caller provided the Tx cleanup threshold value. */
1483 if (tx_conf->tx_free_thresh != 0) {
1484 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1486 dyn_thresh = txq->ring_size -
1487 txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1488 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1489 txq->ring_size - ENA_REFILL_THRESH_PACKET);
1492 txq->missing_tx_completion_threshold =
1493 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1495 /* Store pointer to this queue in upper layer */
1496 txq->configured = 1;
1497 dev->data->tx_queues[queue_idx] = txq;
1502 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1505 unsigned int socket_id,
1506 const struct rte_eth_rxconf *rx_conf,
1507 struct rte_mempool *mp)
1509 struct ena_adapter *adapter = dev->data->dev_private;
1510 struct ena_ring *rxq = NULL;
1513 uint16_t dyn_thresh;
1515 rxq = &adapter->rx_ring[queue_idx];
1516 if (rxq->configured) {
1518 "API violation. Queue[%d] is already configured\n",
1520 return ENA_COM_FAULT;
1523 if (!rte_is_power_of_2(nb_desc)) {
1525 "Unsupported size of Rx queue: %d is not a power of 2.\n",
1530 if (nb_desc > adapter->max_rx_ring_size) {
1532 "Unsupported size of Rx queue (max size: %d)\n",
1533 adapter->max_rx_ring_size);
1537 /* ENA isn't supporting buffers smaller than 1400 bytes */
1538 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1539 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1541 "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1542 buffer_size, ENA_RX_BUF_MIN_SIZE);
1546 rxq->port_id = dev->data->port_id;
1547 rxq->next_to_clean = 0;
1548 rxq->next_to_use = 0;
1549 rxq->ring_size = nb_desc;
1550 rxq->size_mask = nb_desc - 1;
1551 rxq->numa_socket_id = socket_id;
1554 rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1555 sizeof(struct ena_rx_buffer) * nb_desc,
1556 RTE_CACHE_LINE_SIZE,
1558 if (!rxq->rx_buffer_info) {
1560 "Failed to allocate memory for Rx buffer info\n");
1564 rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1565 sizeof(struct rte_mbuf *) * nb_desc,
1566 RTE_CACHE_LINE_SIZE,
1568 if (!rxq->rx_refill_buffer) {
1570 "Failed to allocate memory for Rx refill buffer\n");
1571 rte_free(rxq->rx_buffer_info);
1572 rxq->rx_buffer_info = NULL;
1576 rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1577 sizeof(uint16_t) * nb_desc,
1578 RTE_CACHE_LINE_SIZE,
1580 if (!rxq->empty_rx_reqs) {
1582 "Failed to allocate memory for empty Rx requests\n");
1583 rte_free(rxq->rx_buffer_info);
1584 rxq->rx_buffer_info = NULL;
1585 rte_free(rxq->rx_refill_buffer);
1586 rxq->rx_refill_buffer = NULL;
1590 for (i = 0; i < nb_desc; i++)
1591 rxq->empty_rx_reqs[i] = i;
1593 rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1595 if (rx_conf->rx_free_thresh != 0) {
1596 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1598 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1599 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1600 (uint16_t)(ENA_REFILL_THRESH_PACKET));
1603 /* Store pointer to this queue in upper layer */
1604 rxq->configured = 1;
1605 dev->data->rx_queues[queue_idx] = rxq;
1610 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1611 struct rte_mbuf *mbuf, uint16_t id)
1613 struct ena_com_buf ebuf;
1616 /* prepare physical address for DMA transaction */
1617 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1618 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1620 /* pass resource to device */
1621 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1622 if (unlikely(rc != 0))
1623 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1628 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1632 uint16_t next_to_use = rxq->next_to_use;
1634 #ifdef RTE_ETHDEV_DEBUG_RX
1637 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1639 if (unlikely(!count))
1642 #ifdef RTE_ETHDEV_DEBUG_RX
1643 in_use = rxq->ring_size - 1 -
1644 ena_com_free_q_entries(rxq->ena_com_io_sq);
1645 if (unlikely((in_use + count) >= rxq->ring_size))
1646 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1649 /* get resources for incoming packets */
1650 rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1651 if (unlikely(rc < 0)) {
1652 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1653 ++rxq->rx_stats.mbuf_alloc_fail;
1654 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1658 for (i = 0; i < count; i++) {
1659 struct rte_mbuf *mbuf = mbufs[i];
1660 struct ena_rx_buffer *rx_info;
1662 if (likely((i + 4) < count))
1663 rte_prefetch0(mbufs[i + 4]);
1665 req_id = rxq->empty_rx_reqs[next_to_use];
1666 rx_info = &rxq->rx_buffer_info[req_id];
1668 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1669 if (unlikely(rc != 0))
1672 rx_info->mbuf = mbuf;
1673 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1676 if (unlikely(i < count)) {
1678 "Refilled Rx queue[%d] with only %d/%d buffers\n",
1680 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1681 ++rxq->rx_stats.refill_partial;
1684 /* When we submitted free resources to device... */
1685 if (likely(i > 0)) {
1686 /* ...let HW know that it can fill buffers with data. */
1687 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1689 rxq->next_to_use = next_to_use;
1695 static int ena_device_init(struct ena_adapter *adapter,
1696 struct rte_pci_device *pdev,
1697 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1699 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1700 uint32_t aenq_groups;
1702 bool readless_supported;
1704 /* Initialize mmio registers */
1705 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1707 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1711 /* The PCIe configuration space revision id indicate if mmio reg
1714 readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1715 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1718 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1720 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1721 goto err_mmio_read_less;
1724 /* check FW version */
1725 rc = ena_com_validate_version(ena_dev);
1727 PMD_DRV_LOG(ERR, "Device version is too low\n");
1728 goto err_mmio_read_less;
1731 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1733 /* ENA device administration layer init */
1734 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1737 "Cannot initialize ENA admin queue\n");
1738 goto err_mmio_read_less;
1741 /* To enable the msix interrupts the driver needs to know the number
1742 * of queues. So the driver uses polling mode to retrieve this
1745 ena_com_set_admin_polling_mode(ena_dev, true);
1747 ena_config_host_info(ena_dev);
1749 /* Get Device Attributes and features */
1750 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1753 "Cannot get attribute for ENA device, rc: %d\n", rc);
1754 goto err_admin_init;
1757 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1758 BIT(ENA_ADMIN_NOTIFICATION) |
1759 BIT(ENA_ADMIN_KEEP_ALIVE) |
1760 BIT(ENA_ADMIN_FATAL_ERROR) |
1761 BIT(ENA_ADMIN_WARNING);
1763 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1765 adapter->all_aenq_groups = aenq_groups;
1770 ena_com_admin_destroy(ena_dev);
1773 ena_com_mmio_reg_read_request_destroy(ena_dev);
1778 static void ena_interrupt_handler_rte(void *cb_arg)
1780 struct rte_eth_dev *dev = cb_arg;
1781 struct ena_adapter *adapter = dev->data->dev_private;
1782 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1784 ena_com_admin_q_comp_intr_handler(ena_dev);
1785 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1786 ena_com_aenq_intr_handler(ena_dev, dev);
1789 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1791 if (!(adapter->active_aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)))
1794 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1797 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1798 adapter->keep_alive_timeout)) {
1799 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1800 ena_trigger_reset(adapter, ENA_REGS_RESET_KEEP_ALIVE_TO);
1801 ++adapter->dev_stats.wd_expired;
1805 /* Check if admin queue is enabled */
1806 static void check_for_admin_com_state(struct ena_adapter *adapter)
1808 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1809 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1810 ena_trigger_reset(adapter, ENA_REGS_RESET_ADMIN_TO);
1814 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1815 struct ena_ring *tx_ring)
1817 struct ena_tx_buffer *tx_buf;
1819 uint64_t completion_delay;
1820 uint32_t missed_tx = 0;
1824 for (i = 0; i < tx_ring->ring_size; ++i) {
1825 tx_buf = &tx_ring->tx_buffer_info[i];
1826 timestamp = tx_buf->timestamp;
1831 completion_delay = rte_get_timer_cycles() - timestamp;
1832 if (completion_delay > adapter->missing_tx_completion_to) {
1833 if (unlikely(!tx_buf->print_once)) {
1835 "Found a Tx that wasn't completed on time, qid %d, index %d. "
1836 "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1837 tx_ring->id, i, completion_delay /
1838 rte_get_timer_hz() * 1000);
1839 tx_buf->print_once = true;
1845 if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1847 "The number of lost Tx completions is above the threshold (%d > %d). "
1848 "Trigger the device reset.\n",
1850 tx_ring->missing_tx_completion_threshold);
1851 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1852 adapter->trigger_reset = true;
1856 tx_ring->tx_stats.missed_tx += missed_tx;
1861 static void check_for_tx_completions(struct ena_adapter *adapter)
1863 struct ena_ring *tx_ring;
1864 uint64_t tx_cleanup_delay;
1867 uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1869 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1872 nb_tx_queues = adapter->edev_data->nb_tx_queues;
1873 budget = adapter->missing_tx_completion_budget;
1875 qid = adapter->last_tx_comp_qid;
1876 while (budget-- > 0) {
1877 tx_ring = &adapter->tx_ring[qid];
1879 /* Tx cleanup is called only by the burst function and can be
1880 * called dynamically by the application. Also cleanup is
1881 * limited by the threshold. To avoid false detection of the
1882 * missing HW Tx completion, get the delay since last cleanup
1883 * function was called.
1885 tx_cleanup_delay = rte_get_timer_cycles() -
1886 tx_ring->last_cleanup_ticks;
1887 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1888 check_for_tx_completion_in_queue(adapter, tx_ring);
1889 qid = (qid + 1) % nb_tx_queues;
1892 adapter->last_tx_comp_qid = qid;
1895 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1898 struct rte_eth_dev *dev = arg;
1899 struct ena_adapter *adapter = dev->data->dev_private;
1901 if (unlikely(adapter->trigger_reset))
1904 check_for_missing_keep_alive(adapter);
1905 check_for_admin_com_state(adapter);
1906 check_for_tx_completions(adapter);
1908 if (unlikely(adapter->trigger_reset)) {
1909 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1910 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1916 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1917 struct ena_admin_feature_llq_desc *llq,
1918 bool use_large_llq_hdr)
1920 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1921 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1922 llq_config->llq_num_decs_before_header =
1923 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1925 if (use_large_llq_hdr &&
1926 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1927 llq_config->llq_ring_entry_size =
1928 ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1929 llq_config->llq_ring_entry_size_value = 256;
1931 llq_config->llq_ring_entry_size =
1932 ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1933 llq_config->llq_ring_entry_size_value = 128;
1938 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1939 struct ena_com_dev *ena_dev,
1940 struct ena_admin_feature_llq_desc *llq,
1941 struct ena_llq_configurations *llq_default_configurations)
1944 u32 llq_feature_mask;
1946 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1947 if (!(ena_dev->supported_features & llq_feature_mask)) {
1949 "LLQ is not supported. Fallback to host mode policy.\n");
1950 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1954 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1956 PMD_INIT_LOG(WARNING,
1957 "Failed to config dev mode. Fallback to host mode policy.\n");
1958 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1962 /* Nothing to config, exit */
1963 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1966 if (!adapter->dev_mem_base) {
1968 "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1969 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1973 ena_dev->mem_bar = adapter->dev_mem_base;
1978 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1979 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1981 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1983 /* Regular queues capabilities */
1984 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1985 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1986 &get_feat_ctx->max_queue_ext.max_queue_ext;
1987 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1988 max_queue_ext->max_rx_cq_num);
1989 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1990 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1992 struct ena_admin_queue_feature_desc *max_queues =
1993 &get_feat_ctx->max_queues;
1994 io_tx_sq_num = max_queues->max_sq_num;
1995 io_tx_cq_num = max_queues->max_cq_num;
1996 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1999 /* In case of LLQ use the llq number in the get feature cmd */
2000 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
2001 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
2003 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
2004 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
2005 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
2007 if (unlikely(max_num_io_queues == 0)) {
2008 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
2012 return max_num_io_queues;
2016 ena_set_offloads(struct ena_offloads *offloads,
2017 struct ena_admin_feature_offload_desc *offload_desc)
2019 if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2020 offloads->tx_offloads |= ENA_IPV4_TSO;
2022 /* Tx IPv4 checksum offloads */
2023 if (offload_desc->tx &
2024 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
2025 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
2026 if (offload_desc->tx &
2027 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
2028 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
2029 if (offload_desc->tx &
2030 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2031 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
2033 /* Tx IPv6 checksum offloads */
2034 if (offload_desc->tx &
2035 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
2036 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
2037 if (offload_desc->tx &
2038 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2039 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
2041 /* Rx IPv4 checksum offloads */
2042 if (offload_desc->rx_supported &
2043 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
2044 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
2045 if (offload_desc->rx_supported &
2046 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2047 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
2049 /* Rx IPv6 checksum offloads */
2050 if (offload_desc->rx_supported &
2051 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2052 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
2054 if (offload_desc->rx_supported &
2055 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
2056 offloads->rx_offloads |= ENA_RX_RSS_HASH;
2059 static int ena_init_once(void)
2061 static bool init_done;
2066 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2067 /* Init timer subsystem for the ENA timer service. */
2068 rte_timer_subsystem_init();
2069 /* Register handler for requests from secondary processes. */
2070 rte_mp_action_register(ENA_MP_NAME, ena_mp_primary_handle);
2077 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
2079 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
2080 struct rte_pci_device *pci_dev;
2081 struct rte_intr_handle *intr_handle;
2082 struct ena_adapter *adapter = eth_dev->data->dev_private;
2083 struct ena_com_dev *ena_dev = &adapter->ena_dev;
2084 struct ena_com_dev_get_features_ctx get_feat_ctx;
2085 struct ena_llq_configurations llq_config;
2086 const char *queue_type_str;
2087 uint32_t max_num_io_queues;
2089 static int adapters_found;
2090 bool disable_meta_caching;
2092 eth_dev->dev_ops = &ena_dev_ops;
2093 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
2094 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
2095 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
2097 rc = ena_init_once();
2101 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2104 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2106 memset(adapter, 0, sizeof(struct ena_adapter));
2107 ena_dev = &adapter->ena_dev;
2109 adapter->edev_data = eth_dev->data;
2111 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2113 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
2114 pci_dev->addr.domain,
2116 pci_dev->addr.devid,
2117 pci_dev->addr.function);
2119 intr_handle = pci_dev->intr_handle;
2121 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
2122 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
2124 if (!adapter->regs) {
2125 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
2130 ena_dev->reg_bar = adapter->regs;
2131 /* Pass device data as a pointer which can be passed to the IO functions
2132 * by the ena_com (for example - the memory allocation).
2134 ena_dev->dmadev = eth_dev->data;
2136 adapter->id_number = adapters_found;
2138 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
2139 adapter->id_number);
2141 adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2143 rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
2145 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
2149 /* device specific initialization routine */
2150 rc = ena_device_init(adapter, pci_dev, &get_feat_ctx);
2152 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
2156 /* Check if device supports LSC */
2157 if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE)))
2158 adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
2160 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
2161 adapter->use_large_llq_hdr);
2162 rc = ena_set_queues_placement_policy(adapter, ena_dev,
2163 &get_feat_ctx.llq, &llq_config);
2165 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
2169 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
2170 queue_type_str = "Regular";
2172 queue_type_str = "Low latency";
2173 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
2175 calc_queue_ctx.ena_dev = ena_dev;
2176 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
2178 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
2179 rc = ena_calc_io_queue_size(&calc_queue_ctx,
2180 adapter->use_large_llq_hdr);
2181 if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
2183 goto err_device_destroy;
2186 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
2187 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
2188 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
2189 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
2190 adapter->max_num_io_queues = max_num_io_queues;
2192 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2193 disable_meta_caching =
2194 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
2195 BIT(ENA_ADMIN_DISABLE_META_CACHING));
2197 disable_meta_caching = false;
2200 /* prepare ring structures */
2201 ena_init_rings(adapter, disable_meta_caching);
2203 ena_config_debug_area(adapter);
2205 /* Set max MTU for this device */
2206 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
2208 ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
2210 /* Copy MAC address and point DPDK to it */
2211 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
2212 rte_ether_addr_copy((struct rte_ether_addr *)
2213 get_feat_ctx.dev_attr.mac_addr,
2214 (struct rte_ether_addr *)adapter->mac_addr);
2216 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2217 if (unlikely(rc != 0)) {
2218 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
2219 goto err_delete_debug_area;
2222 adapter->drv_stats = rte_zmalloc("adapter stats",
2223 sizeof(*adapter->drv_stats),
2224 RTE_CACHE_LINE_SIZE);
2225 if (!adapter->drv_stats) {
2227 "Failed to allocate memory for adapter statistics\n");
2229 goto err_rss_destroy;
2232 rte_spinlock_init(&adapter->admin_lock);
2234 rte_intr_callback_register(intr_handle,
2235 ena_interrupt_handler_rte,
2237 rte_intr_enable(intr_handle);
2238 ena_com_set_admin_polling_mode(ena_dev, false);
2239 ena_com_admin_aenq_enable(ena_dev);
2241 rte_timer_init(&adapter->timer_wd);
2244 adapter->state = ENA_ADAPTER_STATE_INIT;
2249 ena_com_rss_destroy(ena_dev);
2250 err_delete_debug_area:
2251 ena_com_delete_debug_area(ena_dev);
2254 ena_com_delete_host_info(ena_dev);
2255 ena_com_admin_destroy(ena_dev);
2261 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
2263 struct ena_adapter *adapter = eth_dev->data->dev_private;
2264 struct ena_com_dev *ena_dev = &adapter->ena_dev;
2266 if (adapter->state == ENA_ADAPTER_STATE_FREE)
2269 ena_com_set_admin_running_state(ena_dev, false);
2271 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
2274 ena_com_rss_destroy(ena_dev);
2276 ena_com_delete_debug_area(ena_dev);
2277 ena_com_delete_host_info(ena_dev);
2279 ena_com_abort_admin_commands(ena_dev);
2280 ena_com_wait_for_abort_completion(ena_dev);
2281 ena_com_admin_destroy(ena_dev);
2282 ena_com_mmio_reg_read_request_destroy(ena_dev);
2284 adapter->state = ENA_ADAPTER_STATE_FREE;
2287 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
2289 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2292 ena_destroy_device(eth_dev);
2297 static int ena_dev_configure(struct rte_eth_dev *dev)
2299 struct ena_adapter *adapter = dev->data->dev_private;
2302 adapter->state = ENA_ADAPTER_STATE_CONFIG;
2304 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2305 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2306 dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2308 /* Scattered Rx cannot be turned off in the HW, so this capability must
2311 dev->data->scattered_rx = 1;
2313 adapter->last_tx_comp_qid = 0;
2315 adapter->missing_tx_completion_budget =
2316 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2318 /* To avoid detection of the spurious Tx completion timeout due to
2319 * application not calling the Tx cleanup function, set timeout for the
2320 * Tx queue which should be half of the missing completion timeout for a
2321 * safety. If there will be a lot of missing Tx completions in the
2322 * queue, they will be detected sooner or later.
2324 adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2326 rc = ena_configure_aenq(adapter);
2331 static void ena_init_rings(struct ena_adapter *adapter,
2332 bool disable_meta_caching)
2336 for (i = 0; i < adapter->max_num_io_queues; i++) {
2337 struct ena_ring *ring = &adapter->tx_ring[i];
2339 ring->configured = 0;
2340 ring->type = ENA_RING_TYPE_TX;
2341 ring->adapter = adapter;
2343 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2344 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2345 ring->sgl_size = adapter->max_tx_sgl_size;
2346 ring->disable_meta_caching = disable_meta_caching;
2349 for (i = 0; i < adapter->max_num_io_queues; i++) {
2350 struct ena_ring *ring = &adapter->rx_ring[i];
2352 ring->configured = 0;
2353 ring->type = ENA_RING_TYPE_RX;
2354 ring->adapter = adapter;
2356 ring->sgl_size = adapter->max_rx_sgl_size;
2360 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2362 uint64_t port_offloads = 0;
2364 if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2365 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2367 if (adapter->offloads.rx_offloads &
2368 (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2370 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2372 if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2373 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2375 port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2377 return port_offloads;
2380 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2382 uint64_t port_offloads = 0;
2384 if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2385 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2387 if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2388 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2389 if (adapter->offloads.tx_offloads &
2390 (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2391 ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2393 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2395 port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2397 return port_offloads;
2400 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2402 RTE_SET_USED(adapter);
2407 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2409 RTE_SET_USED(adapter);
2414 static int ena_infos_get(struct rte_eth_dev *dev,
2415 struct rte_eth_dev_info *dev_info)
2417 struct ena_adapter *adapter;
2418 struct ena_com_dev *ena_dev;
2420 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2421 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2422 adapter = dev->data->dev_private;
2424 ena_dev = &adapter->ena_dev;
2425 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2427 dev_info->speed_capa =
2428 RTE_ETH_LINK_SPEED_1G |
2429 RTE_ETH_LINK_SPEED_2_5G |
2430 RTE_ETH_LINK_SPEED_5G |
2431 RTE_ETH_LINK_SPEED_10G |
2432 RTE_ETH_LINK_SPEED_25G |
2433 RTE_ETH_LINK_SPEED_40G |
2434 RTE_ETH_LINK_SPEED_50G |
2435 RTE_ETH_LINK_SPEED_100G;
2437 /* Inform framework about available features */
2438 dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2439 dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2440 dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2441 dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2443 dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2444 dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2446 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2447 dev_info->max_rx_pktlen = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2449 dev_info->min_mtu = ENA_MIN_MTU;
2450 dev_info->max_mtu = adapter->max_mtu;
2451 dev_info->max_mac_addrs = 1;
2453 dev_info->max_rx_queues = adapter->max_num_io_queues;
2454 dev_info->max_tx_queues = adapter->max_num_io_queues;
2455 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2457 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2458 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2459 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2460 adapter->max_rx_sgl_size);
2461 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2462 adapter->max_rx_sgl_size);
2464 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2465 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2466 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2467 adapter->max_tx_sgl_size);
2468 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2469 adapter->max_tx_sgl_size);
2471 dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2472 dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2477 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2479 mbuf->data_len = len;
2480 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2485 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2486 struct ena_com_rx_buf_info *ena_bufs,
2488 uint16_t *next_to_clean,
2491 struct rte_mbuf *mbuf;
2492 struct rte_mbuf *mbuf_head;
2493 struct ena_rx_buffer *rx_info;
2495 uint16_t ntc, len, req_id, buf = 0;
2497 if (unlikely(descs == 0))
2500 ntc = *next_to_clean;
2502 len = ena_bufs[buf].len;
2503 req_id = ena_bufs[buf].req_id;
2505 rx_info = &rx_ring->rx_buffer_info[req_id];
2507 mbuf = rx_info->mbuf;
2508 RTE_ASSERT(mbuf != NULL);
2510 ena_init_rx_mbuf(mbuf, len);
2512 /* Fill the mbuf head with the data specific for 1st segment. */
2514 mbuf_head->nb_segs = descs;
2515 mbuf_head->port = rx_ring->port_id;
2516 mbuf_head->pkt_len = len;
2517 mbuf_head->data_off += offset;
2519 rx_info->mbuf = NULL;
2520 rx_ring->empty_rx_reqs[ntc] = req_id;
2521 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2525 len = ena_bufs[buf].len;
2526 req_id = ena_bufs[buf].req_id;
2528 rx_info = &rx_ring->rx_buffer_info[req_id];
2529 RTE_ASSERT(rx_info->mbuf != NULL);
2531 if (unlikely(len == 0)) {
2533 * Some devices can pass descriptor with the length 0.
2534 * To avoid confusion, the PMD is simply putting the
2535 * descriptor back, as it was never used. We'll avoid
2536 * mbuf allocation that way.
2538 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2539 rx_info->mbuf, req_id);
2540 if (unlikely(rc != 0)) {
2541 /* Free the mbuf in case of an error. */
2542 rte_mbuf_raw_free(rx_info->mbuf);
2545 * If there was no error, just exit the loop as
2546 * 0 length descriptor is always the last one.
2551 /* Create an mbuf chain. */
2552 mbuf->next = rx_info->mbuf;
2555 ena_init_rx_mbuf(mbuf, len);
2556 mbuf_head->pkt_len += len;
2560 * Mark the descriptor as depleted and perform necessary
2562 * This code will execute in two cases:
2563 * 1. Descriptor len was greater than 0 - normal situation.
2564 * 2. Descriptor len was 0 and we failed to add the descriptor
2565 * to the device. In that situation, we should try to add
2566 * the mbuf again in the populate routine and mark the
2567 * descriptor as used up by the device.
2569 rx_info->mbuf = NULL;
2570 rx_ring->empty_rx_reqs[ntc] = req_id;
2571 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2574 *next_to_clean = ntc;
2579 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2582 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2583 unsigned int free_queue_entries;
2584 uint16_t next_to_clean = rx_ring->next_to_clean;
2585 uint16_t descs_in_use;
2586 struct rte_mbuf *mbuf;
2588 struct ena_com_rx_ctx ena_rx_ctx;
2592 #ifdef RTE_ETHDEV_DEBUG_RX
2593 /* Check adapter state */
2594 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2596 "Trying to receive pkts while device is NOT running\n");
2601 fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2603 descs_in_use = rx_ring->ring_size -
2604 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2605 nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2607 for (completed = 0; completed < nb_pkts; completed++) {
2608 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2609 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2610 ena_rx_ctx.descs = 0;
2611 ena_rx_ctx.pkt_offset = 0;
2612 /* receive packet context */
2613 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2614 rx_ring->ena_com_io_sq,
2618 "Failed to get the packet from the device, rc: %d\n",
2620 if (rc == ENA_COM_NO_SPACE) {
2621 ++rx_ring->rx_stats.bad_desc_num;
2622 ena_trigger_reset(rx_ring->adapter,
2623 ENA_REGS_RESET_TOO_MANY_RX_DESCS);
2625 ++rx_ring->rx_stats.bad_req_id;
2626 ena_trigger_reset(rx_ring->adapter,
2627 ENA_REGS_RESET_INV_RX_REQ_ID);
2632 mbuf = ena_rx_mbuf(rx_ring,
2633 ena_rx_ctx.ena_bufs,
2636 ena_rx_ctx.pkt_offset);
2637 if (unlikely(mbuf == NULL)) {
2638 for (i = 0; i < ena_rx_ctx.descs; ++i) {
2639 rx_ring->empty_rx_reqs[next_to_clean] =
2640 rx_ring->ena_bufs[i].req_id;
2641 next_to_clean = ENA_IDX_NEXT_MASKED(
2642 next_to_clean, rx_ring->size_mask);
2647 /* fill mbuf attributes if any */
2648 ena_rx_mbuf_prepare(rx_ring, mbuf, &ena_rx_ctx, fill_hash);
2650 if (unlikely(mbuf->ol_flags &
2651 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD)))
2652 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2654 rx_pkts[completed] = mbuf;
2655 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2658 rx_ring->rx_stats.cnt += completed;
2659 rx_ring->next_to_clean = next_to_clean;
2661 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2663 /* Burst refill to save doorbells, memory barriers, const interval */
2664 if (free_queue_entries >= rx_ring->rx_free_thresh) {
2665 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2666 ena_populate_rx_queue(rx_ring, free_queue_entries);
2673 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2679 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2680 struct ena_adapter *adapter = tx_ring->adapter;
2681 struct rte_ipv4_hdr *ip_hdr;
2683 uint64_t l4_csum_flag;
2684 uint64_t dev_offload_capa;
2685 uint16_t frag_field;
2686 bool need_pseudo_csum;
2688 dev_offload_capa = adapter->offloads.tx_offloads;
2689 for (i = 0; i != nb_pkts; i++) {
2691 ol_flags = m->ol_flags;
2693 /* Check if any offload flag was set */
2697 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2698 /* SCTP checksum offload is not supported by the ENA. */
2699 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2700 l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2702 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2704 rte_errno = ENOTSUP;
2708 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2709 !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2710 m->nb_segs == tx_ring->sgl_size &&
2711 m->data_len < tx_ring->tx_max_header_size))) {
2713 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2719 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2720 /* Check if requested offload is also enabled for the queue */
2721 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2722 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2723 (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2724 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2725 (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2726 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2728 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2729 i, m->nb_segs, tx_ring->id);
2734 /* The caller is obligated to set l2 and l3 len if any cksum
2735 * offload is enabled.
2737 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2738 (m->l2_len == 0 || m->l3_len == 0))) {
2740 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2745 ret = rte_validate_tx_offload(m);
2752 /* Verify HW support for requested offloads and determine if
2753 * pseudo header checksum is needed.
2755 need_pseudo_csum = false;
2756 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2757 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2758 !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2759 rte_errno = ENOTSUP;
2763 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2764 !(dev_offload_capa & ENA_IPV4_TSO)) {
2765 rte_errno = ENOTSUP;
2769 /* Check HW capabilities and if pseudo csum is needed
2772 if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2773 !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2774 if (dev_offload_capa &
2775 ENA_L4_IPV4_CSUM_PARTIAL) {
2776 need_pseudo_csum = true;
2778 rte_errno = ENOTSUP;
2783 /* Parse the DF flag */
2784 ip_hdr = rte_pktmbuf_mtod_offset(m,
2785 struct rte_ipv4_hdr *, m->l2_len);
2786 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2787 if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2788 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2789 } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2790 /* In case we are supposed to TSO and have DF
2791 * not set (DF=0) hardware must be provided with
2794 need_pseudo_csum = true;
2796 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2797 /* There is no support for IPv6 TSO as for now. */
2798 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2799 rte_errno = ENOTSUP;
2803 /* Check HW capabilities and if pseudo csum is needed */
2804 if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2805 !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2806 if (dev_offload_capa &
2807 ENA_L4_IPV6_CSUM_PARTIAL) {
2808 need_pseudo_csum = true;
2810 rte_errno = ENOTSUP;
2816 if (need_pseudo_csum) {
2817 ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2828 static void ena_update_hints(struct ena_adapter *adapter,
2829 struct ena_admin_ena_hw_hints *hints)
2831 if (hints->admin_completion_tx_timeout)
2832 adapter->ena_dev.admin_queue.completion_timeout =
2833 hints->admin_completion_tx_timeout * 1000;
2835 if (hints->mmio_read_timeout)
2836 /* convert to usec */
2837 adapter->ena_dev.mmio_read.reg_read_to =
2838 hints->mmio_read_timeout * 1000;
2840 if (hints->driver_watchdog_timeout) {
2841 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2842 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2844 // Convert msecs to ticks
2845 adapter->keep_alive_timeout =
2846 (hints->driver_watchdog_timeout *
2847 rte_get_timer_hz()) / 1000;
2851 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2852 struct ena_tx_buffer *tx_info,
2853 struct rte_mbuf *mbuf,
2855 uint16_t *header_len)
2857 struct ena_com_buf *ena_buf;
2858 uint16_t delta, seg_len, push_len;
2861 seg_len = mbuf->data_len;
2863 tx_info->mbuf = mbuf;
2864 ena_buf = tx_info->bufs;
2866 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2868 * Tx header might be (and will be in most cases) smaller than
2869 * tx_max_header_size. But it's not an issue to send more data
2870 * to the device, than actually needed if the mbuf size is
2871 * greater than tx_max_header_size.
2873 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2874 *header_len = push_len;
2876 if (likely(push_len <= seg_len)) {
2877 /* If the push header is in the single segment, then
2878 * just point it to the 1st mbuf data.
2880 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2882 /* If the push header lays in the several segments, copy
2883 * it to the intermediate buffer.
2885 rte_pktmbuf_read(mbuf, 0, push_len,
2886 tx_ring->push_buf_intermediate_buf);
2887 *push_header = tx_ring->push_buf_intermediate_buf;
2888 delta = push_len - seg_len;
2891 *push_header = NULL;
2896 /* Process first segment taking into consideration pushed header */
2897 if (seg_len > push_len) {
2898 ena_buf->paddr = mbuf->buf_iova +
2901 ena_buf->len = seg_len - push_len;
2903 tx_info->num_of_bufs++;
2906 while ((mbuf = mbuf->next) != NULL) {
2907 seg_len = mbuf->data_len;
2909 /* Skip mbufs if whole data is pushed as a header */
2910 if (unlikely(delta > seg_len)) {
2915 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2916 ena_buf->len = seg_len - delta;
2918 tx_info->num_of_bufs++;
2924 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2926 struct ena_tx_buffer *tx_info;
2927 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2928 uint16_t next_to_use;
2929 uint16_t header_len;
2935 /* Checking for space for 2 additional metadata descriptors due to
2936 * possible header split and metadata descriptor
2938 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2939 mbuf->nb_segs + 2)) {
2940 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2941 return ENA_COM_NO_MEM;
2944 next_to_use = tx_ring->next_to_use;
2946 req_id = tx_ring->empty_tx_reqs[next_to_use];
2947 tx_info = &tx_ring->tx_buffer_info[req_id];
2948 tx_info->num_of_bufs = 0;
2949 RTE_ASSERT(tx_info->mbuf == NULL);
2951 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2953 ena_tx_ctx.ena_bufs = tx_info->bufs;
2954 ena_tx_ctx.push_header = push_header;
2955 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2956 ena_tx_ctx.req_id = req_id;
2957 ena_tx_ctx.header_len = header_len;
2959 /* Set Tx offloads flags, if applicable */
2960 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2961 tx_ring->disable_meta_caching);
2963 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2966 "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2968 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2969 tx_ring->tx_stats.doorbells++;
2970 tx_ring->pkts_without_db = false;
2973 /* prepare the packet's descriptors to dma engine */
2974 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2977 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2978 ++tx_ring->tx_stats.prepare_ctx_err;
2979 ena_trigger_reset(tx_ring->adapter,
2980 ENA_REGS_RESET_DRIVER_INVALID_STATE);
2984 tx_info->tx_descs = nb_hw_desc;
2985 tx_info->timestamp = rte_get_timer_cycles();
2987 tx_ring->tx_stats.cnt++;
2988 tx_ring->tx_stats.bytes += mbuf->pkt_len;
2990 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2991 tx_ring->size_mask);
2996 static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt)
2998 struct ena_ring *tx_ring = (struct ena_ring *)txp;
2999 unsigned int total_tx_descs = 0;
3000 unsigned int total_tx_pkts = 0;
3001 uint16_t cleanup_budget;
3002 uint16_t next_to_clean = tx_ring->next_to_clean;
3005 * If free_pkt_cnt is equal to 0, it means that the user requested
3006 * full cleanup, so attempt to release all Tx descriptors
3007 * (ring_size - 1 -> size_mask)
3009 cleanup_budget = (free_pkt_cnt == 0) ? tx_ring->size_mask : free_pkt_cnt;
3011 while (likely(total_tx_pkts < cleanup_budget)) {
3012 struct rte_mbuf *mbuf;
3013 struct ena_tx_buffer *tx_info;
3016 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
3019 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
3022 /* Get Tx info & store how many descs were processed */
3023 tx_info = &tx_ring->tx_buffer_info[req_id];
3024 tx_info->timestamp = 0;
3026 mbuf = tx_info->mbuf;
3027 rte_pktmbuf_free(mbuf);
3029 tx_info->mbuf = NULL;
3030 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
3032 total_tx_descs += tx_info->tx_descs;
3035 /* Put back descriptor to the ring for reuse */
3036 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
3037 tx_ring->size_mask);
3040 if (likely(total_tx_descs > 0)) {
3041 /* acknowledge completion of sent packets */
3042 tx_ring->next_to_clean = next_to_clean;
3043 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
3044 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
3047 /* Notify completion handler that full cleanup was performed */
3048 if (free_pkt_cnt == 0 || total_tx_pkts < cleanup_budget)
3049 tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
3051 return total_tx_pkts;
3054 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
3057 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
3059 uint16_t sent_idx = 0;
3061 #ifdef RTE_ETHDEV_DEBUG_TX
3062 /* Check adapter state */
3063 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
3065 "Trying to xmit pkts while device is NOT running\n");
3070 available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3071 if (available_desc < tx_ring->tx_free_thresh)
3072 ena_tx_cleanup((void *)tx_ring, 0);
3074 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
3075 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
3077 tx_ring->pkts_without_db = true;
3078 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
3079 tx_ring->size_mask)]);
3082 /* If there are ready packets to be xmitted... */
3083 if (likely(tx_ring->pkts_without_db)) {
3084 /* ...let HW do its best :-) */
3085 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
3086 tx_ring->tx_stats.doorbells++;
3087 tx_ring->pkts_without_db = false;
3090 tx_ring->tx_stats.available_desc =
3091 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3092 tx_ring->tx_stats.tx_poll++;
3097 int ena_copy_eni_stats(struct ena_adapter *adapter, struct ena_stats_eni *stats)
3101 rte_spinlock_lock(&adapter->admin_lock);
3102 /* Retrieve and store the latest statistics from the AQ. This ensures
3103 * that previous value is returned in case of a com error.
3105 rc = ENA_PROXY(adapter, ena_com_get_eni_stats, &adapter->ena_dev,
3106 (struct ena_admin_eni_stats *)stats);
3107 rte_spinlock_unlock(&adapter->admin_lock);
3109 if (rc == ENA_COM_UNSUPPORTED) {
3111 "Retrieving ENI metrics is not supported\n");
3113 PMD_DRV_LOG(WARNING,
3114 "Failed to get ENI metrics, rc: %d\n", rc);
3123 * DPDK callback to retrieve names of extended device statistics
3126 * Pointer to Ethernet device structure.
3127 * @param[out] xstats_names
3128 * Buffer to insert names into.
3133 * Number of xstats names.
3135 static int ena_xstats_get_names(struct rte_eth_dev *dev,
3136 struct rte_eth_xstat_name *xstats_names,
3139 unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3140 unsigned int stat, i, count = 0;
3142 if (n < xstats_count || !xstats_names)
3143 return xstats_count;
3145 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
3146 strcpy(xstats_names[count].name,
3147 ena_stats_global_strings[stat].name);
3149 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
3150 strcpy(xstats_names[count].name,
3151 ena_stats_eni_strings[stat].name);
3153 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
3154 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
3155 snprintf(xstats_names[count].name,
3156 sizeof(xstats_names[count].name),
3158 ena_stats_rx_strings[stat].name);
3160 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
3161 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
3162 snprintf(xstats_names[count].name,
3163 sizeof(xstats_names[count].name),
3165 ena_stats_tx_strings[stat].name);
3167 return xstats_count;
3171 * DPDK callback to retrieve names of extended device statistics for the given
3175 * Pointer to Ethernet device structure.
3176 * @param[out] xstats_names
3177 * Buffer to insert names into.
3179 * IDs array for which the names should be retrieved.
3184 * Positive value: number of xstats names. Negative value: error code.
3186 static int ena_xstats_get_names_by_id(struct rte_eth_dev *dev,
3187 const uint64_t *ids,
3188 struct rte_eth_xstat_name *xstats_names,
3191 uint64_t xstats_count = ena_xstats_calc_num(dev->data);
3195 if (xstats_names == NULL)
3196 return xstats_count;
3198 for (i = 0; i < size; ++i) {
3200 if (id > xstats_count) {
3202 "ID value out of range: id=%" PRIu64 ", xstats_num=%" PRIu64 "\n",
3207 if (id < ENA_STATS_ARRAY_GLOBAL) {
3208 strcpy(xstats_names[i].name,
3209 ena_stats_global_strings[id].name);
3213 id -= ENA_STATS_ARRAY_GLOBAL;
3214 if (id < ENA_STATS_ARRAY_ENI) {
3215 strcpy(xstats_names[i].name,
3216 ena_stats_eni_strings[id].name);
3220 id -= ENA_STATS_ARRAY_ENI;
3221 if (id < ENA_STATS_ARRAY_RX) {
3222 qid = id / dev->data->nb_rx_queues;
3223 id %= dev->data->nb_rx_queues;
3224 snprintf(xstats_names[i].name,
3225 sizeof(xstats_names[i].name),
3226 "rx_q%" PRIu64 "d_%s",
3227 qid, ena_stats_rx_strings[id].name);
3231 id -= ENA_STATS_ARRAY_RX;
3232 /* Although this condition is not needed, it was added for
3233 * compatibility if new xstat structure would be ever added.
3235 if (id < ENA_STATS_ARRAY_TX) {
3236 qid = id / dev->data->nb_tx_queues;
3237 id %= dev->data->nb_tx_queues;
3238 snprintf(xstats_names[i].name,
3239 sizeof(xstats_names[i].name),
3240 "tx_q%" PRIu64 "_%s",
3241 qid, ena_stats_tx_strings[id].name);
3250 * DPDK callback to get extended device statistics.
3253 * Pointer to Ethernet device structure.
3255 * Stats table output buffer.
3257 * The size of the stats table.
3260 * Number of xstats on success, negative on failure.
3262 static int ena_xstats_get(struct rte_eth_dev *dev,
3263 struct rte_eth_xstat *xstats,
3266 struct ena_adapter *adapter = dev->data->dev_private;
3267 unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3268 struct ena_stats_eni eni_stats;
3269 unsigned int stat, i, count = 0;
3273 if (n < xstats_count)
3274 return xstats_count;
3279 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
3280 stat_offset = ena_stats_global_strings[stat].stat_offset;
3281 stats_begin = &adapter->dev_stats;
3283 xstats[count].id = count;
3284 xstats[count].value = *((uint64_t *)
3285 ((char *)stats_begin + stat_offset));
3288 /* Even if the function below fails, we should copy previous (or initial
3289 * values) to keep structure of rte_eth_xstat consistent.
3291 ena_copy_eni_stats(adapter, &eni_stats);
3292 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
3293 stat_offset = ena_stats_eni_strings[stat].stat_offset;
3294 stats_begin = &eni_stats;
3296 xstats[count].id = count;
3297 xstats[count].value = *((uint64_t *)
3298 ((char *)stats_begin + stat_offset));
3301 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
3302 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
3303 stat_offset = ena_stats_rx_strings[stat].stat_offset;
3304 stats_begin = &adapter->rx_ring[i].rx_stats;
3306 xstats[count].id = count;
3307 xstats[count].value = *((uint64_t *)
3308 ((char *)stats_begin + stat_offset));
3312 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
3313 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
3314 stat_offset = ena_stats_tx_strings[stat].stat_offset;
3315 stats_begin = &adapter->tx_ring[i].rx_stats;
3317 xstats[count].id = count;
3318 xstats[count].value = *((uint64_t *)
3319 ((char *)stats_begin + stat_offset));
3326 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
3327 const uint64_t *ids,
3331 struct ena_adapter *adapter = dev->data->dev_private;
3332 struct ena_stats_eni eni_stats;
3334 uint64_t rx_entries, tx_entries;
3338 bool was_eni_copied = false;
3340 for (i = 0; i < n; ++i) {
3342 /* Check if id belongs to global statistics */
3343 if (id < ENA_STATS_ARRAY_GLOBAL) {
3344 values[i] = *((uint64_t *)&adapter->dev_stats + id);
3349 /* Check if id belongs to ENI statistics */
3350 id -= ENA_STATS_ARRAY_GLOBAL;
3351 if (id < ENA_STATS_ARRAY_ENI) {
3352 /* Avoid reading ENI stats multiple times in a single
3353 * function call, as it requires communication with the
3356 if (!was_eni_copied) {
3357 was_eni_copied = true;
3358 ena_copy_eni_stats(adapter, &eni_stats);
3360 values[i] = *((uint64_t *)&eni_stats + id);
3365 /* Check if id belongs to rx queue statistics */
3366 id -= ENA_STATS_ARRAY_ENI;
3367 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
3368 if (id < rx_entries) {
3369 qid = id % dev->data->nb_rx_queues;
3370 id /= dev->data->nb_rx_queues;
3371 values[i] = *((uint64_t *)
3372 &adapter->rx_ring[qid].rx_stats + id);
3376 /* Check if id belongs to rx queue statistics */
3378 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
3379 if (id < tx_entries) {
3380 qid = id % dev->data->nb_tx_queues;
3381 id /= dev->data->nb_tx_queues;
3382 values[i] = *((uint64_t *)
3383 &adapter->tx_ring[qid].tx_stats + id);
3392 static int ena_process_uint_devarg(const char *key,
3396 struct ena_adapter *adapter = opaque;
3398 uint64_t uint_value;
3400 uint_value = strtoull(value, &str_end, 10);
3401 if (value == str_end) {
3403 "Invalid value for key '%s'. Only uint values are accepted.\n",
3408 if (strcmp(key, ENA_DEVARG_MISS_TXC_TO) == 0) {
3409 if (uint_value > ENA_MAX_TX_TIMEOUT_SECONDS) {
3411 "Tx timeout too high: %" PRIu64 " sec. Maximum allowed: %d sec.\n",
3412 uint_value, ENA_MAX_TX_TIMEOUT_SECONDS);
3414 } else if (uint_value == 0) {
3416 "Check for missing Tx completions has been disabled.\n");
3417 adapter->missing_tx_completion_to =
3418 ENA_HW_HINTS_NO_TIMEOUT;
3421 "Tx packet completion timeout set to %" PRIu64 " seconds.\n",
3423 adapter->missing_tx_completion_to =
3424 uint_value * rte_get_timer_hz();
3431 static int ena_process_bool_devarg(const char *key,
3435 struct ena_adapter *adapter = opaque;
3438 /* Parse the value. */
3439 if (strcmp(value, "1") == 0) {
3441 } else if (strcmp(value, "0") == 0) {
3445 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3450 /* Now, assign it to the proper adapter field. */
3451 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3452 adapter->use_large_llq_hdr = bool_value;
3457 static int ena_parse_devargs(struct ena_adapter *adapter,
3458 struct rte_devargs *devargs)
3460 static const char * const allowed_args[] = {
3461 ENA_DEVARG_LARGE_LLQ_HDR,
3462 ENA_DEVARG_MISS_TXC_TO,
3465 struct rte_kvargs *kvlist;
3468 if (devargs == NULL)
3471 kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3472 if (kvlist == NULL) {
3473 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3478 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3479 ena_process_bool_devarg, adapter);
3482 rc = rte_kvargs_process(kvlist, ENA_DEVARG_MISS_TXC_TO,
3483 ena_process_uint_devarg, adapter);
3486 rte_kvargs_free(kvlist);
3491 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3493 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3494 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3496 uint16_t vectors_nb, i;
3497 bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3499 if (!rx_intr_requested)
3502 if (!rte_intr_cap_multiple(intr_handle)) {
3504 "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3508 /* Disable interrupt mapping before the configuration starts. */
3509 rte_intr_disable(intr_handle);
3511 /* Verify if there are enough vectors available. */
3512 vectors_nb = dev->data->nb_rx_queues;
3513 if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3515 "Too many Rx interrupts requested, maximum number: %d\n",
3516 RTE_MAX_RXTX_INTR_VEC_ID);
3521 /* Allocate the vector list */
3522 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3523 dev->data->nb_rx_queues)) {
3525 "Failed to allocate interrupt vector for %d queues\n",
3526 dev->data->nb_rx_queues);
3531 rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3535 if (!rte_intr_allow_others(intr_handle)) {
3537 "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3538 goto disable_intr_efd;
3541 for (i = 0; i < vectors_nb; ++i)
3542 if (rte_intr_vec_list_index_set(intr_handle, i,
3543 RTE_INTR_VEC_RXTX_OFFSET + i))
3544 goto disable_intr_efd;
3546 rte_intr_enable(intr_handle);
3550 rte_intr_efd_disable(intr_handle);
3552 rte_intr_vec_list_free(intr_handle);
3554 rte_intr_enable(intr_handle);
3558 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3562 struct ena_adapter *adapter = dev->data->dev_private;
3563 struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3564 struct ena_eth_io_intr_reg intr_reg;
3566 ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3567 ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3570 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3573 ena_rx_queue_intr_set(dev, queue_id, true);
3578 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3581 ena_rx_queue_intr_set(dev, queue_id, false);
3586 static int ena_configure_aenq(struct ena_adapter *adapter)
3588 uint32_t aenq_groups = adapter->all_aenq_groups;
3591 /* All_aenq_groups holds all AENQ functions supported by the device and
3592 * the HW, so at first we need to be sure the LSC request is valid.
3594 if (adapter->edev_data->dev_conf.intr_conf.lsc != 0) {
3595 if (!(aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) {
3597 "LSC requested, but it's not supported by the AENQ\n");
3601 /* If LSC wasn't enabled by the app, let's enable all supported
3602 * AENQ procedures except the LSC.
3604 aenq_groups &= ~BIT(ENA_ADMIN_LINK_CHANGE);
3607 rc = ena_com_set_aenq_config(&adapter->ena_dev, aenq_groups);
3609 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc=%d\n", rc);
3613 adapter->active_aenq_groups = aenq_groups;
3618 int ena_mp_indirect_table_set(struct ena_adapter *adapter)
3620 return ENA_PROXY(adapter, ena_com_indirect_table_set, &adapter->ena_dev);
3623 int ena_mp_indirect_table_get(struct ena_adapter *adapter,
3624 uint32_t *indirect_table)
3626 return ENA_PROXY(adapter, ena_com_indirect_table_get, &adapter->ena_dev,
3630 /*********************************************************************
3631 * ena_plat_dpdk.h functions implementations
3632 *********************************************************************/
3634 const struct rte_memzone *
3635 ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size,
3636 int socket_id, unsigned int alignment, void **virt_addr,
3637 dma_addr_t *phys_addr)
3639 char z_name[RTE_MEMZONE_NAMESIZE];
3640 struct ena_adapter *adapter = data->dev_private;
3641 const struct rte_memzone *memzone;
3644 rc = snprintf(z_name, RTE_MEMZONE_NAMESIZE, "ena_p%d_mz%" PRIu64 "",
3645 data->port_id, adapter->memzone_cnt);
3646 if (rc >= RTE_MEMZONE_NAMESIZE) {
3648 "Name for the ena_com memzone is too long. Port: %d, mz_num: %" PRIu64 "\n",
3649 data->port_id, adapter->memzone_cnt);
3652 adapter->memzone_cnt++;
3654 memzone = rte_memzone_reserve_aligned(z_name, size, socket_id,
3655 RTE_MEMZONE_IOVA_CONTIG, alignment);
3656 if (memzone == NULL) {
3657 PMD_DRV_LOG(ERR, "Failed to allocate ena_com memzone: %s\n",
3662 memset(memzone->addr, 0, size);
3663 *virt_addr = memzone->addr;
3664 *phys_addr = memzone->iova;
3676 /*********************************************************************
3678 *********************************************************************/
3679 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3680 struct rte_pci_device *pci_dev)
3682 return rte_eth_dev_pci_generic_probe(pci_dev,
3683 sizeof(struct ena_adapter), eth_ena_dev_init);
3686 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3688 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3691 static struct rte_pci_driver rte_ena_pmd = {
3692 .id_table = pci_id_ena_map,
3693 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3694 RTE_PCI_DRV_WC_ACTIVATE,
3695 .probe = eth_ena_pci_probe,
3696 .remove = eth_ena_pci_remove,
3699 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3700 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3701 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3702 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3703 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3704 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3705 #ifdef RTE_ETHDEV_DEBUG_RX
3706 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3708 #ifdef RTE_ETHDEV_DEBUG_TX
3709 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3711 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3713 /******************************************************************************
3714 ******************************** AENQ Handlers *******************************
3715 *****************************************************************************/
3716 static void ena_update_on_link_change(void *adapter_data,
3717 struct ena_admin_aenq_entry *aenq_e)
3719 struct rte_eth_dev *eth_dev = adapter_data;
3720 struct ena_adapter *adapter = eth_dev->data->dev_private;
3721 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3724 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3726 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3727 adapter->link_status = status;
3729 ena_link_update(eth_dev, 0);
3730 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3733 static void ena_notification(void *adapter_data,
3734 struct ena_admin_aenq_entry *aenq_e)
3736 struct rte_eth_dev *eth_dev = adapter_data;
3737 struct ena_adapter *adapter = eth_dev->data->dev_private;
3738 struct ena_admin_ena_hw_hints *hints;
3740 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3741 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3742 aenq_e->aenq_common_desc.group,
3743 ENA_ADMIN_NOTIFICATION);
3745 switch (aenq_e->aenq_common_desc.syndrome) {
3746 case ENA_ADMIN_UPDATE_HINTS:
3747 hints = (struct ena_admin_ena_hw_hints *)
3748 (&aenq_e->inline_data_w4);
3749 ena_update_hints(adapter, hints);
3752 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3753 aenq_e->aenq_common_desc.syndrome);
3757 static void ena_keep_alive(void *adapter_data,
3758 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3760 struct rte_eth_dev *eth_dev = adapter_data;
3761 struct ena_adapter *adapter = eth_dev->data->dev_private;
3762 struct ena_admin_aenq_keep_alive_desc *desc;
3766 adapter->timestamp_wd = rte_get_timer_cycles();
3768 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3769 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3770 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3772 adapter->drv_stats->rx_drops = rx_drops;
3773 adapter->dev_stats.tx_drops = tx_drops;
3777 * This handler will called for unknown event group or unimplemented handlers
3779 static void unimplemented_aenq_handler(__rte_unused void *data,
3780 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3783 "Unknown event was received or event with unimplemented handler\n");
3786 static struct ena_aenq_handlers aenq_handlers = {
3788 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3789 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3790 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3792 .unimplemented_handler = unimplemented_aenq_handler
3795 /*********************************************************************
3796 * Multi-Process communication request handling (in primary)
3797 *********************************************************************/
3799 ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)
3801 const struct ena_mp_body *req =
3802 (const struct ena_mp_body *)mp_msg->param;
3803 struct ena_adapter *adapter;
3804 struct ena_com_dev *ena_dev;
3805 struct ena_mp_body *rsp;
3806 struct rte_mp_msg mp_rsp;
3807 struct rte_eth_dev *dev;
3810 rsp = (struct ena_mp_body *)&mp_rsp.param;
3811 mp_msg_init(&mp_rsp, req->type, req->port_id);
3813 if (!rte_eth_dev_is_valid_port(req->port_id)) {
3816 PMD_DRV_LOG(ERR, "Unknown port %d in request %d\n",
3817 req->port_id, req->type);
3820 dev = &rte_eth_devices[req->port_id];
3821 adapter = dev->data->dev_private;
3822 ena_dev = &adapter->ena_dev;
3824 switch (req->type) {
3825 case ENA_MP_DEV_STATS_GET:
3826 res = ena_com_get_dev_basic_stats(ena_dev,
3827 &adapter->basic_stats);
3829 case ENA_MP_ENI_STATS_GET:
3830 res = ena_com_get_eni_stats(ena_dev,
3831 (struct ena_admin_eni_stats *)&adapter->eni_stats);
3833 case ENA_MP_MTU_SET:
3834 res = ena_com_set_dev_mtu(ena_dev, req->args.mtu);
3836 case ENA_MP_IND_TBL_GET:
3837 res = ena_com_indirect_table_get(ena_dev,
3838 adapter->indirect_table);
3840 case ENA_MP_IND_TBL_SET:
3841 res = ena_com_indirect_table_set(ena_dev);
3844 PMD_DRV_LOG(ERR, "Unknown request type %d\n", req->type);
3850 /* Save processing result in the reply */
3852 /* Return just IPC processing status */
3853 return rte_mp_reply(&mp_rsp, peer);