drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    5
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 struct ena_stats {
  42         char name[ETH_GSTRING_LEN];
  43         int stat_offset;
  44 };
  45
  46 #define ENA_STAT_ENTRY(stat, stat_type) { \
  47         .name = #stat, \
  48         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  49 }
  50
  51 #define ENA_STAT_RX_ENTRY(stat) \
  52         ENA_STAT_ENTRY(stat, rx)
  53
  54 #define ENA_STAT_TX_ENTRY(stat) \
  55         ENA_STAT_ENTRY(stat, tx)
  56
  57 #define ENA_STAT_ENI_ENTRY(stat) \
  58         ENA_STAT_ENTRY(stat, eni)
  59
  60 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  61         ENA_STAT_ENTRY(stat, dev)
  62
  63 /* Device arguments */
  64 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  65
  66 /*
  67  * Each rte_memzone should have unique name.
  68  * To satisfy it, count number of allocation and add it to name.
  69  */
  70 rte_atomic64_t ena_alloc_cnt;
  71
  72 static const struct ena_stats ena_stats_global_strings[] = {
  73         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  74         ENA_STAT_GLOBAL_ENTRY(dev_start),
  75         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  76         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  77 };
  78
  79 static const struct ena_stats ena_stats_eni_strings[] = {
  80         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  81         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  82         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  83         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  84         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  85 };
  86
  87 static const struct ena_stats ena_stats_tx_strings[] = {
  88         ENA_STAT_TX_ENTRY(cnt),
  89         ENA_STAT_TX_ENTRY(bytes),
  90         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  91         ENA_STAT_TX_ENTRY(tx_poll),
  92         ENA_STAT_TX_ENTRY(doorbells),
  93         ENA_STAT_TX_ENTRY(bad_req_id),
  94         ENA_STAT_TX_ENTRY(available_desc),
  95         ENA_STAT_TX_ENTRY(missed_tx),
  96 };
  97
  98 static const struct ena_stats ena_stats_rx_strings[] = {
  99         ENA_STAT_RX_ENTRY(cnt),
 100         ENA_STAT_RX_ENTRY(bytes),
 101         ENA_STAT_RX_ENTRY(refill_partial),
 102         ENA_STAT_RX_ENTRY(l3_csum_bad),
 103         ENA_STAT_RX_ENTRY(l4_csum_bad),
 104         ENA_STAT_RX_ENTRY(l4_csum_good),
 105         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 106         ENA_STAT_RX_ENTRY(bad_desc_num),
 107         ENA_STAT_RX_ENTRY(bad_req_id),
 108 };
 109
 110 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 111 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 112 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 113 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 114
 115 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
 116                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
 117                         RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
 118                         RTE_ETH_TX_OFFLOAD_TCP_TSO)
 119 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
 120                        RTE_MBUF_F_TX_IP_CKSUM |\
 121                        RTE_MBUF_F_TX_TCP_SEG)
 122
 123 /** Vendor ID used by Amazon devices */
 124 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 125 /** Amazon devices */
 126 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 127 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 128
 129 #define ENA_TX_OFFLOAD_MASK     (RTE_MBUF_F_TX_L4_MASK |         \
 130         RTE_MBUF_F_TX_IPV6 |            \
 131         RTE_MBUF_F_TX_IPV4 |            \
 132         RTE_MBUF_F_TX_IP_CKSUM |        \
 133         RTE_MBUF_F_TX_TCP_SEG)
 134
 135 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 136         (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 137
 138 /** HW specific offloads capabilities. */
 139 /* IPv4 checksum offload. */
 140 #define ENA_L3_IPV4_CSUM                0x0001
 141 /* TCP/UDP checksum offload for IPv4 packets. */
 142 #define ENA_L4_IPV4_CSUM                0x0002
 143 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 144 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 145 /* TCP/UDP checksum offload for IPv6 packets. */
 146 #define ENA_L4_IPV6_CSUM                0x0008
 147 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 148 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 149 /* TSO support for IPv4 packets. */
 150 #define ENA_IPV4_TSO                    0x0020
 151
 152 /* Device supports setting RSS hash. */
 153 #define ENA_RX_RSS_HASH                 0x0040
 154
 155 static const struct rte_pci_id pci_id_ena_map[] = {
 156         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 157         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 158         { .device_id = 0 },
 159 };
 160
 161 static struct ena_aenq_handlers aenq_handlers;
 162
 163 static int ena_device_init(struct ena_adapter *adapter,
 164                            struct rte_pci_device *pdev,
 165                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 166 static int ena_dev_configure(struct rte_eth_dev *dev);
 167 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 168         struct ena_tx_buffer *tx_info,
 169         struct rte_mbuf *mbuf,
 170         void **push_header,
 171         uint16_t *header_len);
 172 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 173 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 174 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 175                                   uint16_t nb_pkts);
 176 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 177                 uint16_t nb_pkts);
 178 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 179                               uint16_t nb_desc, unsigned int socket_id,
 180                               const struct rte_eth_txconf *tx_conf);
 181 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 182                               uint16_t nb_desc, unsigned int socket_id,
 183                               const struct rte_eth_rxconf *rx_conf,
 184                               struct rte_mempool *mp);
 185 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 186 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 187                                     struct ena_com_rx_buf_info *ena_bufs,
 188                                     uint32_t descs,
 189                                     uint16_t *next_to_clean,
 190                                     uint8_t offset);
 191 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 192                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 193 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 194                                   struct rte_mbuf *mbuf, uint16_t id);
 195 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 196 static void ena_init_rings(struct ena_adapter *adapter,
 197                            bool disable_meta_caching);
 198 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 199 static int ena_start(struct rte_eth_dev *dev);
 200 static int ena_stop(struct rte_eth_dev *dev);
 201 static int ena_close(struct rte_eth_dev *dev);
 202 static int ena_dev_reset(struct rte_eth_dev *dev);
 203 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 204 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 205 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 206 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 207 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 208 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 209 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 210 static int ena_link_update(struct rte_eth_dev *dev,
 211                            int wait_to_complete);
 212 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 213 static void ena_queue_stop(struct ena_ring *ring);
 214 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 215                               enum ena_ring_type ring_type);
 216 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 217 static int ena_queue_start_all(struct rte_eth_dev *dev,
 218                                enum ena_ring_type ring_type);
 219 static void ena_stats_restart(struct rte_eth_dev *dev);
 220 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
 221 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
 222 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
 223 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
 224 static int ena_infos_get(struct rte_eth_dev *dev,
 225                          struct rte_eth_dev_info *dev_info);
 226 static void ena_interrupt_handler_rte(void *cb_arg);
 227 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 228 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 229 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 230 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 231                                 struct rte_eth_xstat_name *xstats_names,
 232                                 unsigned int n);
 233 static int ena_xstats_get(struct rte_eth_dev *dev,
 234                           struct rte_eth_xstat *stats,
 235                           unsigned int n);
 236 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 237                                 const uint64_t *ids,
 238                                 uint64_t *values,
 239                                 unsigned int n);
 240 static int ena_process_bool_devarg(const char *key,
 241                                    const char *value,
 242                                    void *opaque);
 243 static int ena_parse_devargs(struct ena_adapter *adapter,
 244                              struct rte_devargs *devargs);
 245 static int ena_copy_eni_stats(struct ena_adapter *adapter,
 246                               struct ena_stats_eni *stats);
 247 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 248 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                     uint16_t queue_id);
 250 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                      uint16_t queue_id);
 252 static int ena_configure_aenq(struct ena_adapter *adapter);
 253 static int ena_mp_primary_handle(const struct rte_mp_msg *mp_msg,
 254                                  const void *peer);
 255
 256 static const struct eth_dev_ops ena_dev_ops = {
 257         .dev_configure        = ena_dev_configure,
 258         .dev_infos_get        = ena_infos_get,
 259         .rx_queue_setup       = ena_rx_queue_setup,
 260         .tx_queue_setup       = ena_tx_queue_setup,
 261         .dev_start            = ena_start,
 262         .dev_stop             = ena_stop,
 263         .link_update          = ena_link_update,
 264         .stats_get            = ena_stats_get,
 265         .xstats_get_names     = ena_xstats_get_names,
 266         .xstats_get           = ena_xstats_get,
 267         .xstats_get_by_id     = ena_xstats_get_by_id,
 268         .mtu_set              = ena_mtu_set,
 269         .rx_queue_release     = ena_rx_queue_release,
 270         .tx_queue_release     = ena_tx_queue_release,
 271         .dev_close            = ena_close,
 272         .dev_reset            = ena_dev_reset,
 273         .reta_update          = ena_rss_reta_update,
 274         .reta_query           = ena_rss_reta_query,
 275         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 276         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 277         .rss_hash_update      = ena_rss_hash_update,
 278         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 279 };
 280
 281 /*********************************************************************
 282  *  Multi-Process communication bits
 283  *********************************************************************/
 284 /* rte_mp IPC message name */
 285 #define ENA_MP_NAME     "net_ena_mp"
 286 /* Request timeout in seconds */
 287 #define ENA_MP_REQ_TMO  5
 288
 289 /** Proxy request type */
 290 enum ena_mp_req {
 291         ENA_MP_DEV_STATS_GET,
 292         ENA_MP_ENI_STATS_GET,
 293         ENA_MP_MTU_SET,
 294         ENA_MP_IND_TBL_GET,
 295         ENA_MP_IND_TBL_SET
 296 };
 297
 298 /** Proxy message body. Shared between requests and responses. */
 299 struct ena_mp_body {
 300         /* Message type */
 301         enum ena_mp_req type;
 302         int port_id;
 303         /* Processing result. Set in replies. 0 if message succeeded, negative
 304          * error code otherwise.
 305          */
 306         int result;
 307         union {
 308                 int mtu; /* For ENA_MP_MTU_SET */
 309         } args;
 310 };
 311
 312 /**
 313  * Initialize IPC message.
 314  *
 315  * @param[out] msg
 316  *   Pointer to the message to initialize.
 317  * @param[in] type
 318  *   Message type.
 319  * @param[in] port_id
 320  *   Port ID of target device.
 321  *
 322  */
 323 static void
 324 mp_msg_init(struct rte_mp_msg *msg, enum ena_mp_req type, int port_id)
 325 {
 326         struct ena_mp_body *body = (struct ena_mp_body *)&msg->param;
 327
 328         memset(msg, 0, sizeof(*msg));
 329         strlcpy(msg->name, ENA_MP_NAME, sizeof(msg->name));
 330         msg->len_param = sizeof(*body);
 331         body->type = type;
 332         body->port_id = port_id;
 333 }
 334
 335 /*********************************************************************
 336  *  Multi-Process communication PMD API
 337  *********************************************************************/
 338 /**
 339  * Define proxy request descriptor
 340  *
 341  * Used to define all structures and functions required for proxying a given
 342  * function to the primary process including the code to perform to prepare the
 343  * request and process the response.
 344  *
 345  * @param[in] f
 346  *   Name of the function to proxy
 347  * @param[in] t
 348  *   Message type to use
 349  * @param[in] prep
 350  *   Body of a function to prepare the request in form of a statement
 351  *   expression. It is passed all the original function arguments along with two
 352  *   extra ones:
 353  *   - struct ena_adapter *adapter - PMD data of the device calling the proxy.
 354  *   - struct ena_mp_body *req - body of a request to prepare.
 355  * @param[in] proc
 356  *   Body of a function to process the response in form of a statement
 357  *   expression. It is passed all the original function arguments along with two
 358  *   extra ones:
 359  *   - struct ena_adapter *adapter - PMD data of the device calling the proxy.
 360  *   - struct ena_mp_body *rsp - body of a response to process.
 361  * @param ...
 362  *   Proxied function's arguments
 363  *
 364  * @note Inside prep and proc any parameters which aren't used should be marked
 365  *       as such (with ENA_TOUCH or __rte_unused).
 366  */
 367 #define ENA_PROXY_DESC(f, t, prep, proc, ...)                   \
 368         static const enum ena_mp_req mp_type_ ## f =  t;        \
 369         static const char *mp_name_ ## f = #t;                  \
 370         static void mp_prep_ ## f(struct ena_adapter *adapter,  \
 371                                   struct ena_mp_body *req,      \
 372                                   __VA_ARGS__)                  \
 373         {                                                       \
 374                 prep;                                           \
 375         }                                                       \
 376         static void mp_proc_ ## f(struct ena_adapter *adapter,  \
 377                                   struct ena_mp_body *rsp,      \
 378                                   __VA_ARGS__)                  \
 379         {                                                       \
 380                 proc;                                           \
 381         }
 382
 383 /**
 384  * Proxy wrapper for calling primary functions in a secondary process.
 385  *
 386  * Depending on whether called in primary or secondary process, calls the
 387  * @p func directly or proxies the call to the primary process via rte_mp IPC.
 388  * This macro requires a proxy request descriptor to be defined for @p func
 389  * using ENA_PROXY_DESC() macro.
 390  *
 391  * @param[in/out] a
 392  *   Device PMD data. Used for sending the message and sharing message results
 393  *   between primary and secondary.
 394  * @param[in] f
 395  *   Function to proxy.
 396  * @param ...
 397  *   Arguments of @p func.
 398  *
 399  * @return
 400  *   - 0: Processing succeeded and response handler was called.
 401  *   - -EPERM: IPC is unavailable on this platform. This means only primary
 402  *             process may call the proxied function.
 403  *   - -EIO:   IPC returned error on request send. Inspect rte_errno detailed
 404  *             error code.
 405  *   - Negative error code from the proxied function.
 406  *
 407  * @note This mechanism is geared towards control-path tasks. Avoid calling it
 408  *       in fast-path unless unbound delays are allowed. This is due to the IPC
 409  *       mechanism itself (socket based).
 410  * @note Due to IPC parameter size limitations the proxy logic shares call
 411  *       results through the struct ena_adapter shared memory. This makes the
 412  *       proxy mechanism strictly single-threaded. Therefore be sure to make all
 413  *       calls to the same proxied function under the same lock.
 414  */
 415 #define ENA_PROXY(a, f, ...)                                            \
 416 ({                                                                      \
 417         struct ena_adapter *_a = (a);                                   \
 418         struct timespec ts = { .tv_sec = ENA_MP_REQ_TMO };              \
 419         struct ena_mp_body *req, *rsp;                                  \
 420         struct rte_mp_reply mp_rep;                                     \
 421         struct rte_mp_msg mp_req;                                       \
 422         int ret;                                                        \
 423                                                                         \
 424         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {               \
 425                 ret = f(__VA_ARGS__);                                   \
 426         } else {                                                        \
 427                 /* Prepare and send request */                          \
 428                 req = (struct ena_mp_body *)&mp_req.param;              \
 429                 mp_msg_init(&mp_req, mp_type_ ## f, _a->edev_data->port_id); \
 430                 mp_prep_ ## f(_a, req, ## __VA_ARGS__);                 \
 431                                                                         \
 432                 ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);       \
 433                 if (likely(!ret)) {                                     \
 434                         RTE_ASSERT(mp_rep.nb_received == 1);            \
 435                         rsp = (struct ena_mp_body *)&mp_rep.msgs[0].param; \
 436                         ret = rsp->result;                              \
 437                         if (ret == 0) {                                 \
 438                                 mp_proc_##f(_a, rsp, ## __VA_ARGS__);   \
 439                         } else {                                        \
 440                                 PMD_DRV_LOG(ERR,                        \
 441                                             "%s returned error: %d\n",  \
 442                                             mp_name_ ## f, rsp->result);\
 443                         }                                               \
 444                         free(mp_rep.msgs);                              \
 445                 } else if (rte_errno == ENOTSUP) {                      \
 446                         PMD_DRV_LOG(ERR,                                \
 447                                     "No IPC, can't proxy to primary\n");\
 448                         ret = -rte_errno;                               \
 449                 } else {                                                \
 450                         PMD_DRV_LOG(ERR, "Request %s failed: %s\n",     \
 451                                     mp_name_ ## f,                      \
 452                                     rte_strerror(rte_errno));           \
 453                         ret = -EIO;                                     \
 454                 }                                                       \
 455         }                                                               \
 456         ret;                                                            \
 457 })
 458
 459 /*********************************************************************
 460  *  Multi-Process communication request descriptors
 461  *********************************************************************/
 462
 463 ENA_PROXY_DESC(ena_com_get_dev_basic_stats, ENA_MP_DEV_STATS_GET,
 464 ({
 465         ENA_TOUCH(adapter);
 466         ENA_TOUCH(req);
 467         ENA_TOUCH(ena_dev);
 468         ENA_TOUCH(stats);
 469 }),
 470 ({
 471         ENA_TOUCH(rsp);
 472         ENA_TOUCH(ena_dev);
 473         if (stats != &adapter->basic_stats)
 474                 rte_memcpy(stats, &adapter->basic_stats, sizeof(*stats));
 475 }),
 476         struct ena_com_dev *ena_dev, struct ena_admin_basic_stats *stats);
 477
 478 ENA_PROXY_DESC(ena_com_get_eni_stats, ENA_MP_ENI_STATS_GET,
 479 ({
 480         ENA_TOUCH(adapter);
 481         ENA_TOUCH(req);
 482         ENA_TOUCH(ena_dev);
 483         ENA_TOUCH(stats);
 484 }),
 485 ({
 486         ENA_TOUCH(rsp);
 487         ENA_TOUCH(ena_dev);
 488         if (stats != (struct ena_admin_eni_stats *)&adapter->eni_stats)
 489                 rte_memcpy(stats, &adapter->eni_stats, sizeof(*stats));
 490 }),
 491         struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats);
 492
 493 ENA_PROXY_DESC(ena_com_set_dev_mtu, ENA_MP_MTU_SET,
 494 ({
 495         ENA_TOUCH(adapter);
 496         ENA_TOUCH(ena_dev);
 497         req->args.mtu = mtu;
 498 }),
 499 ({
 500         ENA_TOUCH(adapter);
 501         ENA_TOUCH(rsp);
 502         ENA_TOUCH(ena_dev);
 503         ENA_TOUCH(mtu);
 504 }),
 505         struct ena_com_dev *ena_dev, int mtu);
 506
 507 ENA_PROXY_DESC(ena_com_indirect_table_set, ENA_MP_IND_TBL_SET,
 508 ({
 509         ENA_TOUCH(adapter);
 510         ENA_TOUCH(req);
 511         ENA_TOUCH(ena_dev);
 512 }),
 513 ({
 514         ENA_TOUCH(adapter);
 515         ENA_TOUCH(rsp);
 516         ENA_TOUCH(ena_dev);
 517 }),
 518         struct ena_com_dev *ena_dev);
 519
 520 ENA_PROXY_DESC(ena_com_indirect_table_get, ENA_MP_IND_TBL_GET,
 521 ({
 522         ENA_TOUCH(adapter);
 523         ENA_TOUCH(req);
 524         ENA_TOUCH(ena_dev);
 525         ENA_TOUCH(ind_tbl);
 526 }),
 527 ({
 528         ENA_TOUCH(rsp);
 529         ENA_TOUCH(ena_dev);
 530         if (ind_tbl != adapter->indirect_table)
 531                 rte_memcpy(ind_tbl, adapter->indirect_table,
 532                            sizeof(adapter->indirect_table));
 533 }),
 534         struct ena_com_dev *ena_dev, u32 *ind_tbl);
 535
 536 static inline void ena_rx_mbuf_prepare(struct ena_ring *rx_ring,
 537                                        struct rte_mbuf *mbuf,
 538                                        struct ena_com_rx_ctx *ena_rx_ctx,
 539                                        bool fill_hash)
 540 {
 541         struct ena_stats_rx *rx_stats = &rx_ring->rx_stats;
 542         uint64_t ol_flags = 0;
 543         uint32_t packet_type = 0;
 544
 545         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 546                 packet_type |= RTE_PTYPE_L4_TCP;
 547         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 548                 packet_type |= RTE_PTYPE_L4_UDP;
 549
 550         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 551                 packet_type |= RTE_PTYPE_L3_IPV4;
 552                 if (unlikely(ena_rx_ctx->l3_csum_err)) {
 553                         ++rx_stats->l3_csum_bad;
 554                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 555                 } else {
 556                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 557                 }
 558         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 559                 packet_type |= RTE_PTYPE_L3_IPV6;
 560         }
 561
 562         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) {
 563                 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
 564         } else {
 565                 if (unlikely(ena_rx_ctx->l4_csum_err)) {
 566                         ++rx_stats->l4_csum_bad;
 567                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 568                 } else {
 569                         ++rx_stats->l4_csum_good;
 570                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 571                 }
 572         }
 573
 574         if (fill_hash &&
 575             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 576                 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 577                 mbuf->hash.rss = ena_rx_ctx->hash;
 578         }
 579
 580         mbuf->ol_flags = ol_flags;
 581         mbuf->packet_type = packet_type;
 582 }
 583
 584 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 585                                        struct ena_com_tx_ctx *ena_tx_ctx,
 586                                        uint64_t queue_offloads,
 587                                        bool disable_meta_caching)
 588 {
 589         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 590
 591         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 592             (queue_offloads & QUEUE_OFFLOADS)) {
 593                 /* check if TSO is required */
 594                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
 595                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
 596                         ena_tx_ctx->tso_enable = true;
 597
 598                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 599                 }
 600
 601                 /* check if L3 checksum is needed */
 602                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
 603                     (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
 604                         ena_tx_ctx->l3_csum_enable = true;
 605
 606                 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
 607                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 608                 } else {
 609                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 610
 611                         /* set don't fragment (DF) flag */
 612                         if (mbuf->packet_type &
 613                                 (RTE_PTYPE_L4_NONFRAG
 614                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 615                                 ena_tx_ctx->df = true;
 616                 }
 617
 618                 /* check if L4 checksum is needed */
 619                 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
 620                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
 621                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 622                         ena_tx_ctx->l4_csum_enable = true;
 623                 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
 624                                 RTE_MBUF_F_TX_UDP_CKSUM) &&
 625                                 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
 626                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 627                         ena_tx_ctx->l4_csum_enable = true;
 628                 } else {
 629                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 630                         ena_tx_ctx->l4_csum_enable = false;
 631                 }
 632
 633                 ena_meta->mss = mbuf->tso_segsz;
 634                 ena_meta->l3_hdr_len = mbuf->l3_len;
 635                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 636
 637                 ena_tx_ctx->meta_valid = true;
 638         } else if (disable_meta_caching) {
 639                 memset(ena_meta, 0, sizeof(*ena_meta));
 640                 ena_tx_ctx->meta_valid = true;
 641         } else {
 642                 ena_tx_ctx->meta_valid = false;
 643         }
 644 }
 645
 646 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 647 {
 648         struct ena_tx_buffer *tx_info = NULL;
 649
 650         if (likely(req_id < tx_ring->ring_size)) {
 651                 tx_info = &tx_ring->tx_buffer_info[req_id];
 652                 if (likely(tx_info->mbuf))
 653                         return 0;
 654         }
 655
 656         if (tx_info)
 657                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 658         else
 659                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 660
 661         /* Trigger device reset */
 662         ++tx_ring->tx_stats.bad_req_id;
 663         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 664         tx_ring->adapter->trigger_reset = true;
 665         return -EFAULT;
 666 }
 667
 668 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 669 {
 670         struct ena_admin_host_info *host_info;
 671         int rc;
 672
 673         /* Allocate only the host info */
 674         rc = ena_com_allocate_host_info(ena_dev);
 675         if (rc) {
 676                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 677                 return;
 678         }
 679
 680         host_info = ena_dev->host_attr.host_info;
 681
 682         host_info->os_type = ENA_ADMIN_OS_DPDK;
 683         host_info->kernel_ver = RTE_VERSION;
 684         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 685                 sizeof(host_info->kernel_ver_str));
 686         host_info->os_dist = RTE_VERSION;
 687         strlcpy((char *)host_info->os_dist_str, rte_version(),
 688                 sizeof(host_info->os_dist_str));
 689         host_info->driver_version =
 690                 (DRV_MODULE_VER_MAJOR) |
 691                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 692                 (DRV_MODULE_VER_SUBMINOR <<
 693                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 694         host_info->num_cpus = rte_lcore_count();
 695
 696         host_info->driver_supported_features =
 697                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 698                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 699
 700         rc = ena_com_set_host_attributes(ena_dev);
 701         if (rc) {
 702                 if (rc == -ENA_COM_UNSUPPORTED)
 703                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 704                 else
 705                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 706
 707                 goto err;
 708         }
 709
 710         return;
 711
 712 err:
 713         ena_com_delete_host_info(ena_dev);
 714 }
 715
 716 /* This function calculates the number of xstats based on the current config */
 717 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 718 {
 719         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 720                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 721                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 722 }
 723
 724 static void ena_config_debug_area(struct ena_adapter *adapter)
 725 {
 726         u32 debug_area_size;
 727         int rc, ss_count;
 728
 729         ss_count = ena_xstats_calc_num(adapter->edev_data);
 730
 731         /* allocate 32 bytes for each string and 64bit for the value */
 732         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 733
 734         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 735         if (rc) {
 736                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 737                 return;
 738         }
 739
 740         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 741         if (rc) {
 742                 if (rc == -ENA_COM_UNSUPPORTED)
 743                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 744                 else
 745                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 746
 747                 goto err;
 748         }
 749
 750         return;
 751 err:
 752         ena_com_delete_debug_area(&adapter->ena_dev);
 753 }
 754
 755 static int ena_close(struct rte_eth_dev *dev)
 756 {
 757         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 758         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 759         struct ena_adapter *adapter = dev->data->dev_private;
 760         int ret = 0;
 761
 762         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 763                 return 0;
 764
 765         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 766                 ret = ena_stop(dev);
 767         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 768
 769         ena_rx_queue_release_all(dev);
 770         ena_tx_queue_release_all(dev);
 771
 772         rte_free(adapter->drv_stats);
 773         adapter->drv_stats = NULL;
 774
 775         rte_intr_disable(intr_handle);
 776         rte_intr_callback_unregister(intr_handle,
 777                                      ena_interrupt_handler_rte,
 778                                      dev);
 779
 780         /*
 781          * MAC is not allocated dynamically. Setting NULL should prevent from
 782          * release of the resource in the rte_eth_dev_release_port().
 783          */
 784         dev->data->mac_addrs = NULL;
 785
 786         return ret;
 787 }
 788
 789 static int
 790 ena_dev_reset(struct rte_eth_dev *dev)
 791 {
 792         int rc = 0;
 793
 794         /* Cannot release memory in secondary process */
 795         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 796                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 797                 return -EPERM;
 798         }
 799
 800         ena_destroy_device(dev);
 801         rc = eth_ena_dev_init(dev);
 802         if (rc)
 803                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 804
 805         return rc;
 806 }
 807
 808 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 809 {
 810         int nb_queues = dev->data->nb_rx_queues;
 811         int i;
 812
 813         for (i = 0; i < nb_queues; i++)
 814                 ena_rx_queue_release(dev, i);
 815 }
 816
 817 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 818 {
 819         int nb_queues = dev->data->nb_tx_queues;
 820         int i;
 821
 822         for (i = 0; i < nb_queues; i++)
 823                 ena_tx_queue_release(dev, i);
 824 }
 825
 826 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 827 {
 828         struct ena_ring *ring = dev->data->rx_queues[qid];
 829
 830         /* Free ring resources */
 831         rte_free(ring->rx_buffer_info);
 832         ring->rx_buffer_info = NULL;
 833
 834         rte_free(ring->rx_refill_buffer);
 835         ring->rx_refill_buffer = NULL;
 836
 837         rte_free(ring->empty_rx_reqs);
 838         ring->empty_rx_reqs = NULL;
 839
 840         ring->configured = 0;
 841
 842         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 843                 ring->port_id, ring->id);
 844 }
 845
 846 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 847 {
 848         struct ena_ring *ring = dev->data->tx_queues[qid];
 849
 850         /* Free ring resources */
 851         rte_free(ring->push_buf_intermediate_buf);
 852
 853         rte_free(ring->tx_buffer_info);
 854
 855         rte_free(ring->empty_tx_reqs);
 856
 857         ring->empty_tx_reqs = NULL;
 858         ring->tx_buffer_info = NULL;
 859         ring->push_buf_intermediate_buf = NULL;
 860
 861         ring->configured = 0;
 862
 863         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 864                 ring->port_id, ring->id);
 865 }
 866
 867 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 868 {
 869         unsigned int i;
 870
 871         for (i = 0; i < ring->ring_size; ++i) {
 872                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 873                 if (rx_info->mbuf) {
 874                         rte_mbuf_raw_free(rx_info->mbuf);
 875                         rx_info->mbuf = NULL;
 876                 }
 877         }
 878 }
 879
 880 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 881 {
 882         unsigned int i;
 883
 884         for (i = 0; i < ring->ring_size; ++i) {
 885                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 886
 887                 if (tx_buf->mbuf) {
 888                         rte_pktmbuf_free(tx_buf->mbuf);
 889                         tx_buf->mbuf = NULL;
 890                 }
 891         }
 892 }
 893
 894 static int ena_link_update(struct rte_eth_dev *dev,
 895                            __rte_unused int wait_to_complete)
 896 {
 897         struct rte_eth_link *link = &dev->data->dev_link;
 898         struct ena_adapter *adapter = dev->data->dev_private;
 899
 900         link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
 901         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
 902         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 903
 904         return 0;
 905 }
 906
 907 static int ena_queue_start_all(struct rte_eth_dev *dev,
 908                                enum ena_ring_type ring_type)
 909 {
 910         struct ena_adapter *adapter = dev->data->dev_private;
 911         struct ena_ring *queues = NULL;
 912         int nb_queues;
 913         int i = 0;
 914         int rc = 0;
 915
 916         if (ring_type == ENA_RING_TYPE_RX) {
 917                 queues = adapter->rx_ring;
 918                 nb_queues = dev->data->nb_rx_queues;
 919         } else {
 920                 queues = adapter->tx_ring;
 921                 nb_queues = dev->data->nb_tx_queues;
 922         }
 923         for (i = 0; i < nb_queues; i++) {
 924                 if (queues[i].configured) {
 925                         if (ring_type == ENA_RING_TYPE_RX) {
 926                                 ena_assert_msg(
 927                                         dev->data->rx_queues[i] == &queues[i],
 928                                         "Inconsistent state of Rx queues\n");
 929                         } else {
 930                                 ena_assert_msg(
 931                                         dev->data->tx_queues[i] == &queues[i],
 932                                         "Inconsistent state of Tx queues\n");
 933                         }
 934
 935                         rc = ena_queue_start(dev, &queues[i]);
 936
 937                         if (rc) {
 938                                 PMD_INIT_LOG(ERR,
 939                                         "Failed to start queue[%d] of type(%d)\n",
 940                                         i, ring_type);
 941                                 goto err;
 942                         }
 943                 }
 944         }
 945
 946         return 0;
 947
 948 err:
 949         while (i--)
 950                 if (queues[i].configured)
 951                         ena_queue_stop(&queues[i]);
 952
 953         return rc;
 954 }
 955
 956 static int ena_check_valid_conf(struct ena_adapter *adapter)
 957 {
 958         uint32_t mtu = adapter->edev_data->mtu;
 959
 960         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 961                 PMD_INIT_LOG(ERR,
 962                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 963                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 964                 return ENA_COM_UNSUPPORTED;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int
 971 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 972                        bool use_large_llq_hdr)
 973 {
 974         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 975         struct ena_com_dev *ena_dev = ctx->ena_dev;
 976         uint32_t max_tx_queue_size;
 977         uint32_t max_rx_queue_size;
 978
 979         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 980                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 981                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 982                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 983                         max_queue_ext->max_rx_sq_depth);
 984                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 985
 986                 if (ena_dev->tx_mem_queue_type ==
 987                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 988                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 989                                 llq->max_llq_depth);
 990                 } else {
 991                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 992                                 max_queue_ext->max_tx_sq_depth);
 993                 }
 994
 995                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 996                         max_queue_ext->max_per_packet_rx_descs);
 997                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 998                         max_queue_ext->max_per_packet_tx_descs);
 999         } else {
1000                 struct ena_admin_queue_feature_desc *max_queues =
1001                         &ctx->get_feat_ctx->max_queues;
1002                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
1003                         max_queues->max_sq_depth);
1004                 max_tx_queue_size = max_queues->max_cq_depth;
1005
1006                 if (ena_dev->tx_mem_queue_type ==
1007                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1008                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1009                                 llq->max_llq_depth);
1010                 } else {
1011                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1012                                 max_queues->max_sq_depth);
1013                 }
1014
1015                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1016                         max_queues->max_packet_rx_descs);
1017                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1018                         max_queues->max_packet_tx_descs);
1019         }
1020
1021         /* Round down to the nearest power of 2 */
1022         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
1023         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
1024
1025         if (use_large_llq_hdr) {
1026                 if ((llq->entry_size_ctrl_supported &
1027                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
1028                     (ena_dev->tx_mem_queue_type ==
1029                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
1030                         max_tx_queue_size /= 2;
1031                         PMD_INIT_LOG(INFO,
1032                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
1033                                 max_tx_queue_size);
1034                 } else {
1035                         PMD_INIT_LOG(ERR,
1036                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
1037                 }
1038         }
1039
1040         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
1041                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
1042                 return -EFAULT;
1043         }
1044
1045         ctx->max_tx_queue_size = max_tx_queue_size;
1046         ctx->max_rx_queue_size = max_rx_queue_size;
1047
1048         return 0;
1049 }
1050
1051 static void ena_stats_restart(struct rte_eth_dev *dev)
1052 {
1053         struct ena_adapter *adapter = dev->data->dev_private;
1054
1055         rte_atomic64_init(&adapter->drv_stats->ierrors);
1056         rte_atomic64_init(&adapter->drv_stats->oerrors);
1057         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
1058         adapter->drv_stats->rx_drops = 0;
1059 }
1060
1061 static int ena_stats_get(struct rte_eth_dev *dev,
1062                           struct rte_eth_stats *stats)
1063 {
1064         struct ena_admin_basic_stats ena_stats;
1065         struct ena_adapter *adapter = dev->data->dev_private;
1066         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1067         int rc;
1068         int i;
1069         int max_rings_stats;
1070
1071         memset(&ena_stats, 0, sizeof(ena_stats));
1072
1073         rte_spinlock_lock(&adapter->admin_lock);
1074         rc = ENA_PROXY(adapter, ena_com_get_dev_basic_stats, ena_dev,
1075                        &ena_stats);
1076         rte_spinlock_unlock(&adapter->admin_lock);
1077         if (unlikely(rc)) {
1078                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
1079                 return rc;
1080         }
1081
1082         /* Set of basic statistics from ENA */
1083         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1084                                           ena_stats.rx_pkts_low);
1085         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1086                                           ena_stats.tx_pkts_low);
1087         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1088                                         ena_stats.rx_bytes_low);
1089         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1090                                         ena_stats.tx_bytes_low);
1091
1092         /* Driver related stats */
1093         stats->imissed = adapter->drv_stats->rx_drops;
1094         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1095         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1096         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1097
1098         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1099                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1100         for (i = 0; i < max_rings_stats; ++i) {
1101                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1102
1103                 stats->q_ibytes[i] = rx_stats->bytes;
1104                 stats->q_ipackets[i] = rx_stats->cnt;
1105                 stats->q_errors[i] = rx_stats->bad_desc_num +
1106                         rx_stats->bad_req_id;
1107         }
1108
1109         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1110                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1111         for (i = 0; i < max_rings_stats; ++i) {
1112                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1113
1114                 stats->q_obytes[i] = tx_stats->bytes;
1115                 stats->q_opackets[i] = tx_stats->cnt;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1122 {
1123         struct ena_adapter *adapter;
1124         struct ena_com_dev *ena_dev;
1125         int rc = 0;
1126
1127         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1128         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1129         adapter = dev->data->dev_private;
1130
1131         ena_dev = &adapter->ena_dev;
1132         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1133
1134         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
1135                 PMD_DRV_LOG(ERR,
1136                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
1137                         mtu, adapter->max_mtu, ENA_MIN_MTU);
1138                 return -EINVAL;
1139         }
1140
1141         rc = ENA_PROXY(adapter, ena_com_set_dev_mtu, ena_dev, mtu);
1142         if (rc)
1143                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1144         else
1145                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
1146
1147         return rc;
1148 }
1149
1150 static int ena_start(struct rte_eth_dev *dev)
1151 {
1152         struct ena_adapter *adapter = dev->data->dev_private;
1153         uint64_t ticks;
1154         int rc = 0;
1155
1156         /* Cannot allocate memory in secondary process */
1157         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1158                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
1159                 return -EPERM;
1160         }
1161
1162         rc = ena_check_valid_conf(adapter);
1163         if (rc)
1164                 return rc;
1165
1166         rc = ena_setup_rx_intr(dev);
1167         if (rc)
1168                 return rc;
1169
1170         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1171         if (rc)
1172                 return rc;
1173
1174         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1175         if (rc)
1176                 goto err_start_tx;
1177
1178         if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
1179                 rc = ena_rss_configure(adapter);
1180                 if (rc)
1181                         goto err_rss_init;
1182         }
1183
1184         ena_stats_restart(dev);
1185
1186         adapter->timestamp_wd = rte_get_timer_cycles();
1187         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1188
1189         ticks = rte_get_timer_hz();
1190         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1191                         ena_timer_wd_callback, dev);
1192
1193         ++adapter->dev_stats.dev_start;
1194         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1195
1196         return 0;
1197
1198 err_rss_init:
1199         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1200 err_start_tx:
1201         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1202         return rc;
1203 }
1204
1205 static int ena_stop(struct rte_eth_dev *dev)
1206 {
1207         struct ena_adapter *adapter = dev->data->dev_private;
1208         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1209         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1210         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1211         int rc;
1212
1213         /* Cannot free memory in secondary process */
1214         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1215                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
1216                 return -EPERM;
1217         }
1218
1219         rte_timer_stop_sync(&adapter->timer_wd);
1220         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1221         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1222
1223         if (adapter->trigger_reset) {
1224                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1225                 if (rc)
1226                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
1227         }
1228
1229         rte_intr_disable(intr_handle);
1230
1231         rte_intr_efd_disable(intr_handle);
1232
1233         /* Cleanup vector list */
1234         rte_intr_vec_list_free(intr_handle);
1235
1236         rte_intr_enable(intr_handle);
1237
1238         ++adapter->dev_stats.dev_stop;
1239         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1240         dev->data->dev_started = 0;
1241
1242         return 0;
1243 }
1244
1245 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
1246 {
1247         struct ena_adapter *adapter = ring->adapter;
1248         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1249         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1250         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1251         struct ena_com_create_io_ctx ctx =
1252                 /* policy set to _HOST just to satisfy icc compiler */
1253                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1254                   0, 0, 0, 0, 0 };
1255         uint16_t ena_qid;
1256         unsigned int i;
1257         int rc;
1258
1259         ctx.msix_vector = -1;
1260         if (ring->type == ENA_RING_TYPE_TX) {
1261                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1262                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1263                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1264                 for (i = 0; i < ring->ring_size; i++)
1265                         ring->empty_tx_reqs[i] = i;
1266         } else {
1267                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1268                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1269                 if (rte_intr_dp_is_en(intr_handle))
1270                         ctx.msix_vector =
1271                                 rte_intr_vec_list_index_get(intr_handle,
1272                                                                    ring->id);
1273
1274                 for (i = 0; i < ring->ring_size; i++)
1275                         ring->empty_rx_reqs[i] = i;
1276         }
1277         ctx.queue_size = ring->ring_size;
1278         ctx.qid = ena_qid;
1279         ctx.numa_node = ring->numa_socket_id;
1280
1281         rc = ena_com_create_io_queue(ena_dev, &ctx);
1282         if (rc) {
1283                 PMD_DRV_LOG(ERR,
1284                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1285                         ring->id, ena_qid, rc);
1286                 return rc;
1287         }
1288
1289         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1290                                      &ring->ena_com_io_sq,
1291                                      &ring->ena_com_io_cq);
1292         if (rc) {
1293                 PMD_DRV_LOG(ERR,
1294                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1295                         ring->id, rc);
1296                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1297                 return rc;
1298         }
1299
1300         if (ring->type == ENA_RING_TYPE_TX)
1301                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1302
1303         /* Start with Rx interrupts being masked. */
1304         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1305                 ena_rx_queue_intr_disable(dev, ring->id);
1306
1307         return 0;
1308 }
1309
1310 static void ena_queue_stop(struct ena_ring *ring)
1311 {
1312         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1313
1314         if (ring->type == ENA_RING_TYPE_RX) {
1315                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1316                 ena_rx_queue_release_bufs(ring);
1317         } else {
1318                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1319                 ena_tx_queue_release_bufs(ring);
1320         }
1321 }
1322
1323 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1324                               enum ena_ring_type ring_type)
1325 {
1326         struct ena_adapter *adapter = dev->data->dev_private;
1327         struct ena_ring *queues = NULL;
1328         uint16_t nb_queues, i;
1329
1330         if (ring_type == ENA_RING_TYPE_RX) {
1331                 queues = adapter->rx_ring;
1332                 nb_queues = dev->data->nb_rx_queues;
1333         } else {
1334                 queues = adapter->tx_ring;
1335                 nb_queues = dev->data->nb_tx_queues;
1336         }
1337
1338         for (i = 0; i < nb_queues; ++i)
1339                 if (queues[i].configured)
1340                         ena_queue_stop(&queues[i]);
1341 }
1342
1343 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1344 {
1345         int rc, bufs_num;
1346
1347         ena_assert_msg(ring->configured == 1,
1348                        "Trying to start unconfigured queue\n");
1349
1350         rc = ena_create_io_queue(dev, ring);
1351         if (rc) {
1352                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1353                 return rc;
1354         }
1355
1356         ring->next_to_clean = 0;
1357         ring->next_to_use = 0;
1358
1359         if (ring->type == ENA_RING_TYPE_TX) {
1360                 ring->tx_stats.available_desc =
1361                         ena_com_free_q_entries(ring->ena_com_io_sq);
1362                 return 0;
1363         }
1364
1365         bufs_num = ring->ring_size - 1;
1366         rc = ena_populate_rx_queue(ring, bufs_num);
1367         if (rc != bufs_num) {
1368                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1369                                          ENA_IO_RXQ_IDX(ring->id));
1370                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1371                 return ENA_COM_FAULT;
1372         }
1373         /* Flush per-core RX buffers pools cache as they can be used on other
1374          * cores as well.
1375          */
1376         rte_mempool_cache_flush(NULL, ring->mb_pool);
1377
1378         return 0;
1379 }
1380
1381 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1382                               uint16_t queue_idx,
1383                               uint16_t nb_desc,
1384                               unsigned int socket_id,
1385                               const struct rte_eth_txconf *tx_conf)
1386 {
1387         struct ena_ring *txq = NULL;
1388         struct ena_adapter *adapter = dev->data->dev_private;
1389         unsigned int i;
1390         uint16_t dyn_thresh;
1391
1392         txq = &adapter->tx_ring[queue_idx];
1393
1394         if (txq->configured) {
1395                 PMD_DRV_LOG(CRIT,
1396                         "API violation. Queue[%d] is already configured\n",
1397                         queue_idx);
1398                 return ENA_COM_FAULT;
1399         }
1400
1401         if (!rte_is_power_of_2(nb_desc)) {
1402                 PMD_DRV_LOG(ERR,
1403                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1404                         nb_desc);
1405                 return -EINVAL;
1406         }
1407
1408         if (nb_desc > adapter->max_tx_ring_size) {
1409                 PMD_DRV_LOG(ERR,
1410                         "Unsupported size of Tx queue (max size: %d)\n",
1411                         adapter->max_tx_ring_size);
1412                 return -EINVAL;
1413         }
1414
1415         txq->port_id = dev->data->port_id;
1416         txq->next_to_clean = 0;
1417         txq->next_to_use = 0;
1418         txq->ring_size = nb_desc;
1419         txq->size_mask = nb_desc - 1;
1420         txq->numa_socket_id = socket_id;
1421         txq->pkts_without_db = false;
1422         txq->last_cleanup_ticks = 0;
1423
1424         txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1425                 sizeof(struct ena_tx_buffer) * txq->ring_size,
1426                 RTE_CACHE_LINE_SIZE,
1427                 socket_id);
1428         if (!txq->tx_buffer_info) {
1429                 PMD_DRV_LOG(ERR,
1430                         "Failed to allocate memory for Tx buffer info\n");
1431                 return -ENOMEM;
1432         }
1433
1434         txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1435                 sizeof(uint16_t) * txq->ring_size,
1436                 RTE_CACHE_LINE_SIZE,
1437                 socket_id);
1438         if (!txq->empty_tx_reqs) {
1439                 PMD_DRV_LOG(ERR,
1440                         "Failed to allocate memory for empty Tx requests\n");
1441                 rte_free(txq->tx_buffer_info);
1442                 return -ENOMEM;
1443         }
1444
1445         txq->push_buf_intermediate_buf =
1446                 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1447                         txq->tx_max_header_size,
1448                         RTE_CACHE_LINE_SIZE,
1449                         socket_id);
1450         if (!txq->push_buf_intermediate_buf) {
1451                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1452                 rte_free(txq->tx_buffer_info);
1453                 rte_free(txq->empty_tx_reqs);
1454                 return -ENOMEM;
1455         }
1456
1457         for (i = 0; i < txq->ring_size; i++)
1458                 txq->empty_tx_reqs[i] = i;
1459
1460         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1461
1462         /* Check if caller provided the Tx cleanup threshold value. */
1463         if (tx_conf->tx_free_thresh != 0) {
1464                 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1465         } else {
1466                 dyn_thresh = txq->ring_size -
1467                         txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1468                 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1469                         txq->ring_size - ENA_REFILL_THRESH_PACKET);
1470         }
1471
1472         txq->missing_tx_completion_threshold =
1473                 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1474
1475         /* Store pointer to this queue in upper layer */
1476         txq->configured = 1;
1477         dev->data->tx_queues[queue_idx] = txq;
1478
1479         return 0;
1480 }
1481
1482 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1483                               uint16_t queue_idx,
1484                               uint16_t nb_desc,
1485                               unsigned int socket_id,
1486                               const struct rte_eth_rxconf *rx_conf,
1487                               struct rte_mempool *mp)
1488 {
1489         struct ena_adapter *adapter = dev->data->dev_private;
1490         struct ena_ring *rxq = NULL;
1491         size_t buffer_size;
1492         int i;
1493         uint16_t dyn_thresh;
1494
1495         rxq = &adapter->rx_ring[queue_idx];
1496         if (rxq->configured) {
1497                 PMD_DRV_LOG(CRIT,
1498                         "API violation. Queue[%d] is already configured\n",
1499                         queue_idx);
1500                 return ENA_COM_FAULT;
1501         }
1502
1503         if (!rte_is_power_of_2(nb_desc)) {
1504                 PMD_DRV_LOG(ERR,
1505                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1506                         nb_desc);
1507                 return -EINVAL;
1508         }
1509
1510         if (nb_desc > adapter->max_rx_ring_size) {
1511                 PMD_DRV_LOG(ERR,
1512                         "Unsupported size of Rx queue (max size: %d)\n",
1513                         adapter->max_rx_ring_size);
1514                 return -EINVAL;
1515         }
1516
1517         /* ENA isn't supporting buffers smaller than 1400 bytes */
1518         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1519         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1520                 PMD_DRV_LOG(ERR,
1521                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1522                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1523                 return -EINVAL;
1524         }
1525
1526         rxq->port_id = dev->data->port_id;
1527         rxq->next_to_clean = 0;
1528         rxq->next_to_use = 0;
1529         rxq->ring_size = nb_desc;
1530         rxq->size_mask = nb_desc - 1;
1531         rxq->numa_socket_id = socket_id;
1532         rxq->mb_pool = mp;
1533
1534         rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1535                 sizeof(struct ena_rx_buffer) * nb_desc,
1536                 RTE_CACHE_LINE_SIZE,
1537                 socket_id);
1538         if (!rxq->rx_buffer_info) {
1539                 PMD_DRV_LOG(ERR,
1540                         "Failed to allocate memory for Rx buffer info\n");
1541                 return -ENOMEM;
1542         }
1543
1544         rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1545                 sizeof(struct rte_mbuf *) * nb_desc,
1546                 RTE_CACHE_LINE_SIZE,
1547                 socket_id);
1548         if (!rxq->rx_refill_buffer) {
1549                 PMD_DRV_LOG(ERR,
1550                         "Failed to allocate memory for Rx refill buffer\n");
1551                 rte_free(rxq->rx_buffer_info);
1552                 rxq->rx_buffer_info = NULL;
1553                 return -ENOMEM;
1554         }
1555
1556         rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1557                 sizeof(uint16_t) * nb_desc,
1558                 RTE_CACHE_LINE_SIZE,
1559                 socket_id);
1560         if (!rxq->empty_rx_reqs) {
1561                 PMD_DRV_LOG(ERR,
1562                         "Failed to allocate memory for empty Rx requests\n");
1563                 rte_free(rxq->rx_buffer_info);
1564                 rxq->rx_buffer_info = NULL;
1565                 rte_free(rxq->rx_refill_buffer);
1566                 rxq->rx_refill_buffer = NULL;
1567                 return -ENOMEM;
1568         }
1569
1570         for (i = 0; i < nb_desc; i++)
1571                 rxq->empty_rx_reqs[i] = i;
1572
1573         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1574
1575         if (rx_conf->rx_free_thresh != 0) {
1576                 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1577         } else {
1578                 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1579                 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1580                         (uint16_t)(ENA_REFILL_THRESH_PACKET));
1581         }
1582
1583         /* Store pointer to this queue in upper layer */
1584         rxq->configured = 1;
1585         dev->data->rx_queues[queue_idx] = rxq;
1586
1587         return 0;
1588 }
1589
1590 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1591                                   struct rte_mbuf *mbuf, uint16_t id)
1592 {
1593         struct ena_com_buf ebuf;
1594         int rc;
1595
1596         /* prepare physical address for DMA transaction */
1597         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1598         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1599
1600         /* pass resource to device */
1601         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1602         if (unlikely(rc != 0))
1603                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1604
1605         return rc;
1606 }
1607
1608 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1609 {
1610         unsigned int i;
1611         int rc;
1612         uint16_t next_to_use = rxq->next_to_use;
1613         uint16_t req_id;
1614 #ifdef RTE_ETHDEV_DEBUG_RX
1615         uint16_t in_use;
1616 #endif
1617         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1618
1619         if (unlikely(!count))
1620                 return 0;
1621
1622 #ifdef RTE_ETHDEV_DEBUG_RX
1623         in_use = rxq->ring_size - 1 -
1624                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1625         if (unlikely((in_use + count) >= rxq->ring_size))
1626                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1627 #endif
1628
1629         /* get resources for incoming packets */
1630         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1631         if (unlikely(rc < 0)) {
1632                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1633                 ++rxq->rx_stats.mbuf_alloc_fail;
1634                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1635                 return 0;
1636         }
1637
1638         for (i = 0; i < count; i++) {
1639                 struct rte_mbuf *mbuf = mbufs[i];
1640                 struct ena_rx_buffer *rx_info;
1641
1642                 if (likely((i + 4) < count))
1643                         rte_prefetch0(mbufs[i + 4]);
1644
1645                 req_id = rxq->empty_rx_reqs[next_to_use];
1646                 rx_info = &rxq->rx_buffer_info[req_id];
1647
1648                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1649                 if (unlikely(rc != 0))
1650                         break;
1651
1652                 rx_info->mbuf = mbuf;
1653                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1654         }
1655
1656         if (unlikely(i < count)) {
1657                 PMD_RX_LOG(WARNING,
1658                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1659                         rxq->id, i, count);
1660                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1661                 ++rxq->rx_stats.refill_partial;
1662         }
1663
1664         /* When we submitted free resources to device... */
1665         if (likely(i > 0)) {
1666                 /* ...let HW know that it can fill buffers with data. */
1667                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1668
1669                 rxq->next_to_use = next_to_use;
1670         }
1671
1672         return i;
1673 }
1674
1675 static int ena_device_init(struct ena_adapter *adapter,
1676                            struct rte_pci_device *pdev,
1677                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1678 {
1679         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1680         uint32_t aenq_groups;
1681         int rc;
1682         bool readless_supported;
1683
1684         /* Initialize mmio registers */
1685         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1686         if (rc) {
1687                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1688                 return rc;
1689         }
1690
1691         /* The PCIe configuration space revision id indicate if mmio reg
1692          * read is disabled.
1693          */
1694         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1695         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1696
1697         /* reset device */
1698         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1699         if (rc) {
1700                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1701                 goto err_mmio_read_less;
1702         }
1703
1704         /* check FW version */
1705         rc = ena_com_validate_version(ena_dev);
1706         if (rc) {
1707                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1708                 goto err_mmio_read_less;
1709         }
1710
1711         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1712
1713         /* ENA device administration layer init */
1714         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1715         if (rc) {
1716                 PMD_DRV_LOG(ERR,
1717                         "Cannot initialize ENA admin queue\n");
1718                 goto err_mmio_read_less;
1719         }
1720
1721         /* To enable the msix interrupts the driver needs to know the number
1722          * of queues. So the driver uses polling mode to retrieve this
1723          * information.
1724          */
1725         ena_com_set_admin_polling_mode(ena_dev, true);
1726
1727         ena_config_host_info(ena_dev);
1728
1729         /* Get Device Attributes and features */
1730         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1731         if (rc) {
1732                 PMD_DRV_LOG(ERR,
1733                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1734                 goto err_admin_init;
1735         }
1736
1737         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1738                       BIT(ENA_ADMIN_NOTIFICATION) |
1739                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1740                       BIT(ENA_ADMIN_FATAL_ERROR) |
1741                       BIT(ENA_ADMIN_WARNING);
1742
1743         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1744
1745         adapter->all_aenq_groups = aenq_groups;
1746
1747         return 0;
1748
1749 err_admin_init:
1750         ena_com_admin_destroy(ena_dev);
1751
1752 err_mmio_read_less:
1753         ena_com_mmio_reg_read_request_destroy(ena_dev);
1754
1755         return rc;
1756 }
1757
1758 static void ena_interrupt_handler_rte(void *cb_arg)
1759 {
1760         struct rte_eth_dev *dev = cb_arg;
1761         struct ena_adapter *adapter = dev->data->dev_private;
1762         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1763
1764         ena_com_admin_q_comp_intr_handler(ena_dev);
1765         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1766                 ena_com_aenq_intr_handler(ena_dev, dev);
1767 }
1768
1769 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1770 {
1771         if (!(adapter->active_aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)))
1772                 return;
1773
1774         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1775                 return;
1776
1777         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1778             adapter->keep_alive_timeout)) {
1779                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1780                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1781                 adapter->trigger_reset = true;
1782                 ++adapter->dev_stats.wd_expired;
1783         }
1784 }
1785
1786 /* Check if admin queue is enabled */
1787 static void check_for_admin_com_state(struct ena_adapter *adapter)
1788 {
1789         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1790                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1791                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1792                 adapter->trigger_reset = true;
1793         }
1794 }
1795
1796 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1797                                             struct ena_ring *tx_ring)
1798 {
1799         struct ena_tx_buffer *tx_buf;
1800         uint64_t timestamp;
1801         uint64_t completion_delay;
1802         uint32_t missed_tx = 0;
1803         unsigned int i;
1804         int rc = 0;
1805
1806         for (i = 0; i < tx_ring->ring_size; ++i) {
1807                 tx_buf = &tx_ring->tx_buffer_info[i];
1808                 timestamp = tx_buf->timestamp;
1809
1810                 if (timestamp == 0)
1811                         continue;
1812
1813                 completion_delay = rte_get_timer_cycles() - timestamp;
1814                 if (completion_delay > adapter->missing_tx_completion_to) {
1815                         if (unlikely(!tx_buf->print_once)) {
1816                                 PMD_TX_LOG(WARNING,
1817                                         "Found a Tx that wasn't completed on time, qid %d, index %d. "
1818                                         "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1819                                         tx_ring->id, i, completion_delay /
1820                                         rte_get_timer_hz() * 1000);
1821                                 tx_buf->print_once = true;
1822                         }
1823                         ++missed_tx;
1824                 }
1825         }
1826
1827         if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1828                 PMD_DRV_LOG(ERR,
1829                         "The number of lost Tx completions is above the threshold (%d > %d). "
1830                         "Trigger the device reset.\n",
1831                         missed_tx,
1832                         tx_ring->missing_tx_completion_threshold);
1833                 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1834                 adapter->trigger_reset = true;
1835                 rc = -EIO;
1836         }
1837
1838         tx_ring->tx_stats.missed_tx += missed_tx;
1839
1840         return rc;
1841 }
1842
1843 static void check_for_tx_completions(struct ena_adapter *adapter)
1844 {
1845         struct ena_ring *tx_ring;
1846         uint64_t tx_cleanup_delay;
1847         size_t qid;
1848         int budget;
1849         uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1850
1851         if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1852                 return;
1853
1854         nb_tx_queues = adapter->edev_data->nb_tx_queues;
1855         budget = adapter->missing_tx_completion_budget;
1856
1857         qid = adapter->last_tx_comp_qid;
1858         while (budget-- > 0) {
1859                 tx_ring = &adapter->tx_ring[qid];
1860
1861                 /* Tx cleanup is called only by the burst function and can be
1862                  * called dynamically by the application. Also cleanup is
1863                  * limited by the threshold. To avoid false detection of the
1864                  * missing HW Tx completion, get the delay since last cleanup
1865                  * function was called.
1866                  */
1867                 tx_cleanup_delay = rte_get_timer_cycles() -
1868                         tx_ring->last_cleanup_ticks;
1869                 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1870                         check_for_tx_completion_in_queue(adapter, tx_ring);
1871                 qid = (qid + 1) % nb_tx_queues;
1872         }
1873
1874         adapter->last_tx_comp_qid = qid;
1875 }
1876
1877 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1878                                   void *arg)
1879 {
1880         struct rte_eth_dev *dev = arg;
1881         struct ena_adapter *adapter = dev->data->dev_private;
1882
1883         if (unlikely(adapter->trigger_reset))
1884                 return;
1885
1886         check_for_missing_keep_alive(adapter);
1887         check_for_admin_com_state(adapter);
1888         check_for_tx_completions(adapter);
1889
1890         if (unlikely(adapter->trigger_reset)) {
1891                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1892                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1893                         NULL);
1894         }
1895 }
1896
1897 static inline void
1898 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1899                                struct ena_admin_feature_llq_desc *llq,
1900                                bool use_large_llq_hdr)
1901 {
1902         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1903         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1904         llq_config->llq_num_decs_before_header =
1905                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1906
1907         if (use_large_llq_hdr &&
1908             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1909                 llq_config->llq_ring_entry_size =
1910                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1911                 llq_config->llq_ring_entry_size_value = 256;
1912         } else {
1913                 llq_config->llq_ring_entry_size =
1914                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1915                 llq_config->llq_ring_entry_size_value = 128;
1916         }
1917 }
1918
1919 static int
1920 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1921                                 struct ena_com_dev *ena_dev,
1922                                 struct ena_admin_feature_llq_desc *llq,
1923                                 struct ena_llq_configurations *llq_default_configurations)
1924 {
1925         int rc;
1926         u32 llq_feature_mask;
1927
1928         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1929         if (!(ena_dev->supported_features & llq_feature_mask)) {
1930                 PMD_DRV_LOG(INFO,
1931                         "LLQ is not supported. Fallback to host mode policy.\n");
1932                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1933                 return 0;
1934         }
1935
1936         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1937         if (unlikely(rc)) {
1938                 PMD_INIT_LOG(WARNING,
1939                         "Failed to config dev mode. Fallback to host mode policy.\n");
1940                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1941                 return 0;
1942         }
1943
1944         /* Nothing to config, exit */
1945         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1946                 return 0;
1947
1948         if (!adapter->dev_mem_base) {
1949                 PMD_DRV_LOG(ERR,
1950                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1951                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1952                 return 0;
1953         }
1954
1955         ena_dev->mem_bar = adapter->dev_mem_base;
1956
1957         return 0;
1958 }
1959
1960 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1961         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1962 {
1963         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1964
1965         /* Regular queues capabilities */
1966         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1967                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1968                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1969                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1970                                     max_queue_ext->max_rx_cq_num);
1971                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1972                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1973         } else {
1974                 struct ena_admin_queue_feature_desc *max_queues =
1975                         &get_feat_ctx->max_queues;
1976                 io_tx_sq_num = max_queues->max_sq_num;
1977                 io_tx_cq_num = max_queues->max_cq_num;
1978                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1979         }
1980
1981         /* In case of LLQ use the llq number in the get feature cmd */
1982         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1983                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1984
1985         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1986         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1987         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1988
1989         if (unlikely(max_num_io_queues == 0)) {
1990                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1991                 return -EFAULT;
1992         }
1993
1994         return max_num_io_queues;
1995 }
1996
1997 static void
1998 ena_set_offloads(struct ena_offloads *offloads,
1999                  struct ena_admin_feature_offload_desc *offload_desc)
2000 {
2001         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2002                 offloads->tx_offloads |= ENA_IPV4_TSO;
2003
2004         /* Tx IPv4 checksum offloads */
2005         if (offload_desc->tx &
2006             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
2007                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
2008         if (offload_desc->tx &
2009             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
2010                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
2011         if (offload_desc->tx &
2012             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2013                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
2014
2015         /* Tx IPv6 checksum offloads */
2016         if (offload_desc->tx &
2017             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
2018                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
2019         if (offload_desc->tx &
2020              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2021                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
2022
2023         /* Rx IPv4 checksum offloads */
2024         if (offload_desc->rx_supported &
2025             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
2026                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
2027         if (offload_desc->rx_supported &
2028             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2029                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
2030
2031         /* Rx IPv6 checksum offloads */
2032         if (offload_desc->rx_supported &
2033             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2034                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
2035
2036         if (offload_desc->rx_supported &
2037             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
2038                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
2039 }
2040
2041 static int ena_init_once(void)
2042 {
2043         static bool init_done;
2044
2045         if (init_done)
2046                 return 0;
2047
2048         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2049                 /* Init timer subsystem for the ENA timer service. */
2050                 rte_timer_subsystem_init();
2051                 /* Register handler for requests from secondary processes. */
2052                 rte_mp_action_register(ENA_MP_NAME, ena_mp_primary_handle);
2053         }
2054
2055         init_done = true;
2056         return 0;
2057 }
2058
2059 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
2060 {
2061         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
2062         struct rte_pci_device *pci_dev;
2063         struct rte_intr_handle *intr_handle;
2064         struct ena_adapter *adapter = eth_dev->data->dev_private;
2065         struct ena_com_dev *ena_dev = &adapter->ena_dev;
2066         struct ena_com_dev_get_features_ctx get_feat_ctx;
2067         struct ena_llq_configurations llq_config;
2068         const char *queue_type_str;
2069         uint32_t max_num_io_queues;
2070         int rc;
2071         static int adapters_found;
2072         bool disable_meta_caching;
2073
2074         eth_dev->dev_ops = &ena_dev_ops;
2075         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
2076         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
2077         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
2078
2079         rc = ena_init_once();
2080         if (rc != 0)
2081                 return rc;
2082
2083         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2084                 return 0;
2085
2086         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2087
2088         memset(adapter, 0, sizeof(struct ena_adapter));
2089         ena_dev = &adapter->ena_dev;
2090
2091         adapter->edev_data = eth_dev->data;
2092
2093         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2094
2095         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
2096                      pci_dev->addr.domain,
2097                      pci_dev->addr.bus,
2098                      pci_dev->addr.devid,
2099                      pci_dev->addr.function);
2100
2101         intr_handle = pci_dev->intr_handle;
2102
2103         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
2104         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
2105
2106         if (!adapter->regs) {
2107                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
2108                              ENA_REGS_BAR);
2109                 return -ENXIO;
2110         }
2111
2112         ena_dev->reg_bar = adapter->regs;
2113         /* This is a dummy pointer for ena_com functions. */
2114         ena_dev->dmadev = adapter;
2115
2116         adapter->id_number = adapters_found;
2117
2118         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
2119                  adapter->id_number);
2120
2121         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
2122         if (rc != 0) {
2123                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
2124                 goto err;
2125         }
2126
2127         /* device specific initialization routine */
2128         rc = ena_device_init(adapter, pci_dev, &get_feat_ctx);
2129         if (rc) {
2130                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
2131                 goto err;
2132         }
2133
2134         /* Check if device supports LSC */
2135         if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE)))
2136                 adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
2137
2138         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
2139                 adapter->use_large_llq_hdr);
2140         rc = ena_set_queues_placement_policy(adapter, ena_dev,
2141                                              &get_feat_ctx.llq, &llq_config);
2142         if (unlikely(rc)) {
2143                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
2144                 return rc;
2145         }
2146
2147         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
2148                 queue_type_str = "Regular";
2149         else
2150                 queue_type_str = "Low latency";
2151         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
2152
2153         calc_queue_ctx.ena_dev = ena_dev;
2154         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
2155
2156         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
2157         rc = ena_calc_io_queue_size(&calc_queue_ctx,
2158                 adapter->use_large_llq_hdr);
2159         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
2160                 rc = -EFAULT;
2161                 goto err_device_destroy;
2162         }
2163
2164         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
2165         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
2166         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
2167         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
2168         adapter->max_num_io_queues = max_num_io_queues;
2169
2170         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2171                 disable_meta_caching =
2172                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
2173                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
2174         } else {
2175                 disable_meta_caching = false;
2176         }
2177
2178         /* prepare ring structures */
2179         ena_init_rings(adapter, disable_meta_caching);
2180
2181         ena_config_debug_area(adapter);
2182
2183         /* Set max MTU for this device */
2184         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
2185
2186         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
2187
2188         /* Copy MAC address and point DPDK to it */
2189         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
2190         rte_ether_addr_copy((struct rte_ether_addr *)
2191                         get_feat_ctx.dev_attr.mac_addr,
2192                         (struct rte_ether_addr *)adapter->mac_addr);
2193
2194         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2195         if (unlikely(rc != 0)) {
2196                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
2197                 goto err_delete_debug_area;
2198         }
2199
2200         adapter->drv_stats = rte_zmalloc("adapter stats",
2201                                          sizeof(*adapter->drv_stats),
2202                                          RTE_CACHE_LINE_SIZE);
2203         if (!adapter->drv_stats) {
2204                 PMD_DRV_LOG(ERR,
2205                         "Failed to allocate memory for adapter statistics\n");
2206                 rc = -ENOMEM;
2207                 goto err_rss_destroy;
2208         }
2209
2210         rte_spinlock_init(&adapter->admin_lock);
2211
2212         rte_intr_callback_register(intr_handle,
2213                                    ena_interrupt_handler_rte,
2214                                    eth_dev);
2215         rte_intr_enable(intr_handle);
2216         ena_com_set_admin_polling_mode(ena_dev, false);
2217         ena_com_admin_aenq_enable(ena_dev);
2218
2219         rte_timer_init(&adapter->timer_wd);
2220
2221         adapters_found++;
2222         adapter->state = ENA_ADAPTER_STATE_INIT;
2223
2224         return 0;
2225
2226 err_rss_destroy:
2227         ena_com_rss_destroy(ena_dev);
2228 err_delete_debug_area:
2229         ena_com_delete_debug_area(ena_dev);
2230
2231 err_device_destroy:
2232         ena_com_delete_host_info(ena_dev);
2233         ena_com_admin_destroy(ena_dev);
2234
2235 err:
2236         return rc;
2237 }
2238
2239 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
2240 {
2241         struct ena_adapter *adapter = eth_dev->data->dev_private;
2242         struct ena_com_dev *ena_dev = &adapter->ena_dev;
2243
2244         if (adapter->state == ENA_ADAPTER_STATE_FREE)
2245                 return;
2246
2247         ena_com_set_admin_running_state(ena_dev, false);
2248
2249         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
2250                 ena_close(eth_dev);
2251
2252         ena_com_rss_destroy(ena_dev);
2253
2254         ena_com_delete_debug_area(ena_dev);
2255         ena_com_delete_host_info(ena_dev);
2256
2257         ena_com_abort_admin_commands(ena_dev);
2258         ena_com_wait_for_abort_completion(ena_dev);
2259         ena_com_admin_destroy(ena_dev);
2260         ena_com_mmio_reg_read_request_destroy(ena_dev);
2261
2262         adapter->state = ENA_ADAPTER_STATE_FREE;
2263 }
2264
2265 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
2266 {
2267         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2268                 return 0;
2269
2270         ena_destroy_device(eth_dev);
2271
2272         return 0;
2273 }
2274
2275 static int ena_dev_configure(struct rte_eth_dev *dev)
2276 {
2277         struct ena_adapter *adapter = dev->data->dev_private;
2278         int rc;
2279
2280         adapter->state = ENA_ADAPTER_STATE_CONFIG;
2281
2282         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2283                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2284         dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2285
2286         /* Scattered Rx cannot be turned off in the HW, so this capability must
2287          * be forced.
2288          */
2289         dev->data->scattered_rx = 1;
2290
2291         adapter->last_tx_comp_qid = 0;
2292
2293         adapter->missing_tx_completion_budget =
2294                 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2295
2296         adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2297         /* To avoid detection of the spurious Tx completion timeout due to
2298          * application not calling the Tx cleanup function, set timeout for the
2299          * Tx queue which should be half of the missing completion timeout for a
2300          * safety. If there will be a lot of missing Tx completions in the
2301          * queue, they will be detected sooner or later.
2302          */
2303         adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2304
2305         rc = ena_configure_aenq(adapter);
2306
2307         return rc;
2308 }
2309
2310 static void ena_init_rings(struct ena_adapter *adapter,
2311                            bool disable_meta_caching)
2312 {
2313         size_t i;
2314
2315         for (i = 0; i < adapter->max_num_io_queues; i++) {
2316                 struct ena_ring *ring = &adapter->tx_ring[i];
2317
2318                 ring->configured = 0;
2319                 ring->type = ENA_RING_TYPE_TX;
2320                 ring->adapter = adapter;
2321                 ring->id = i;
2322                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2323                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2324                 ring->sgl_size = adapter->max_tx_sgl_size;
2325                 ring->disable_meta_caching = disable_meta_caching;
2326         }
2327
2328         for (i = 0; i < adapter->max_num_io_queues; i++) {
2329                 struct ena_ring *ring = &adapter->rx_ring[i];
2330
2331                 ring->configured = 0;
2332                 ring->type = ENA_RING_TYPE_RX;
2333                 ring->adapter = adapter;
2334                 ring->id = i;
2335                 ring->sgl_size = adapter->max_rx_sgl_size;
2336         }
2337 }
2338
2339 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2340 {
2341         uint64_t port_offloads = 0;
2342
2343         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2344                 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2345
2346         if (adapter->offloads.rx_offloads &
2347             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2348                 port_offloads |=
2349                         RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2350
2351         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2352                 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2353
2354         port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2355
2356         return port_offloads;
2357 }
2358
2359 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2360 {
2361         uint64_t port_offloads = 0;
2362
2363         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2364                 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2365
2366         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2367                 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2368         if (adapter->offloads.tx_offloads &
2369             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2370              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2371                 port_offloads |=
2372                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2373
2374         port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2375
2376         return port_offloads;
2377 }
2378
2379 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2380 {
2381         RTE_SET_USED(adapter);
2382
2383         return 0;
2384 }
2385
2386 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2387 {
2388         RTE_SET_USED(adapter);
2389
2390         return 0;
2391 }
2392
2393 static int ena_infos_get(struct rte_eth_dev *dev,
2394                           struct rte_eth_dev_info *dev_info)
2395 {
2396         struct ena_adapter *adapter;
2397         struct ena_com_dev *ena_dev;
2398
2399         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2400         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2401         adapter = dev->data->dev_private;
2402
2403         ena_dev = &adapter->ena_dev;
2404         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2405
2406         dev_info->speed_capa =
2407                         RTE_ETH_LINK_SPEED_1G   |
2408                         RTE_ETH_LINK_SPEED_2_5G |
2409                         RTE_ETH_LINK_SPEED_5G   |
2410                         RTE_ETH_LINK_SPEED_10G  |
2411                         RTE_ETH_LINK_SPEED_25G  |
2412                         RTE_ETH_LINK_SPEED_40G  |
2413                         RTE_ETH_LINK_SPEED_50G  |
2414                         RTE_ETH_LINK_SPEED_100G;
2415
2416         /* Inform framework about available features */
2417         dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2418         dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2419         dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2420         dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2421
2422         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2423         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2424
2425         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2426         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2427                 RTE_ETHER_CRC_LEN;
2428         dev_info->min_mtu = ENA_MIN_MTU;
2429         dev_info->max_mtu = adapter->max_mtu;
2430         dev_info->max_mac_addrs = 1;
2431
2432         dev_info->max_rx_queues = adapter->max_num_io_queues;
2433         dev_info->max_tx_queues = adapter->max_num_io_queues;
2434         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2435
2436         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2437         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2438         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2439                                         adapter->max_rx_sgl_size);
2440         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2441                                         adapter->max_rx_sgl_size);
2442
2443         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2444         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2445         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2446                                         adapter->max_tx_sgl_size);
2447         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2448                                         adapter->max_tx_sgl_size);
2449
2450         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2451         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2452
2453         return 0;
2454 }
2455
2456 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2457 {
2458         mbuf->data_len = len;
2459         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2460         mbuf->refcnt = 1;
2461         mbuf->next = NULL;
2462 }
2463
2464 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2465                                     struct ena_com_rx_buf_info *ena_bufs,
2466                                     uint32_t descs,
2467                                     uint16_t *next_to_clean,
2468                                     uint8_t offset)
2469 {
2470         struct rte_mbuf *mbuf;
2471         struct rte_mbuf *mbuf_head;
2472         struct ena_rx_buffer *rx_info;
2473         int rc;
2474         uint16_t ntc, len, req_id, buf = 0;
2475
2476         if (unlikely(descs == 0))
2477                 return NULL;
2478
2479         ntc = *next_to_clean;
2480
2481         len = ena_bufs[buf].len;
2482         req_id = ena_bufs[buf].req_id;
2483
2484         rx_info = &rx_ring->rx_buffer_info[req_id];
2485
2486         mbuf = rx_info->mbuf;
2487         RTE_ASSERT(mbuf != NULL);
2488
2489         ena_init_rx_mbuf(mbuf, len);
2490
2491         /* Fill the mbuf head with the data specific for 1st segment. */
2492         mbuf_head = mbuf;
2493         mbuf_head->nb_segs = descs;
2494         mbuf_head->port = rx_ring->port_id;
2495         mbuf_head->pkt_len = len;
2496         mbuf_head->data_off += offset;
2497
2498         rx_info->mbuf = NULL;
2499         rx_ring->empty_rx_reqs[ntc] = req_id;
2500         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2501
2502         while (--descs) {
2503                 ++buf;
2504                 len = ena_bufs[buf].len;
2505                 req_id = ena_bufs[buf].req_id;
2506
2507                 rx_info = &rx_ring->rx_buffer_info[req_id];
2508                 RTE_ASSERT(rx_info->mbuf != NULL);
2509
2510                 if (unlikely(len == 0)) {
2511                         /*
2512                          * Some devices can pass descriptor with the length 0.
2513                          * To avoid confusion, the PMD is simply putting the
2514                          * descriptor back, as it was never used. We'll avoid
2515                          * mbuf allocation that way.
2516                          */
2517                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2518                                 rx_info->mbuf, req_id);
2519                         if (unlikely(rc != 0)) {
2520                                 /* Free the mbuf in case of an error. */
2521                                 rte_mbuf_raw_free(rx_info->mbuf);
2522                         } else {
2523                                 /*
2524                                  * If there was no error, just exit the loop as
2525                                  * 0 length descriptor is always the last one.
2526                                  */
2527                                 break;
2528                         }
2529                 } else {
2530                         /* Create an mbuf chain. */
2531                         mbuf->next = rx_info->mbuf;
2532                         mbuf = mbuf->next;
2533
2534                         ena_init_rx_mbuf(mbuf, len);
2535                         mbuf_head->pkt_len += len;
2536                 }
2537
2538                 /*
2539                  * Mark the descriptor as depleted and perform necessary
2540                  * cleanup.
2541                  * This code will execute in two cases:
2542                  *  1. Descriptor len was greater than 0 - normal situation.
2543                  *  2. Descriptor len was 0 and we failed to add the descriptor
2544                  *     to the device. In that situation, we should try to add
2545                  *     the mbuf again in the populate routine and mark the
2546                  *     descriptor as used up by the device.
2547                  */
2548                 rx_info->mbuf = NULL;
2549                 rx_ring->empty_rx_reqs[ntc] = req_id;
2550                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2551         }
2552
2553         *next_to_clean = ntc;
2554
2555         return mbuf_head;
2556 }
2557
2558 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2559                                   uint16_t nb_pkts)
2560 {
2561         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2562         unsigned int free_queue_entries;
2563         uint16_t next_to_clean = rx_ring->next_to_clean;
2564         uint16_t descs_in_use;
2565         struct rte_mbuf *mbuf;
2566         uint16_t completed;
2567         struct ena_com_rx_ctx ena_rx_ctx;
2568         int i, rc = 0;
2569         bool fill_hash;
2570
2571 #ifdef RTE_ETHDEV_DEBUG_RX
2572         /* Check adapter state */
2573         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2574                 PMD_RX_LOG(ALERT,
2575                         "Trying to receive pkts while device is NOT running\n");
2576                 return 0;
2577         }
2578 #endif
2579
2580         fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2581
2582         descs_in_use = rx_ring->ring_size -
2583                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2584         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2585
2586         for (completed = 0; completed < nb_pkts; completed++) {
2587                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2588                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2589                 ena_rx_ctx.descs = 0;
2590                 ena_rx_ctx.pkt_offset = 0;
2591                 /* receive packet context */
2592                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2593                                     rx_ring->ena_com_io_sq,
2594                                     &ena_rx_ctx);
2595                 if (unlikely(rc)) {
2596                         PMD_RX_LOG(ERR,
2597                                 "Failed to get the packet from the device, rc: %d\n",
2598                                 rc);
2599                         if (rc == ENA_COM_NO_SPACE) {
2600                                 ++rx_ring->rx_stats.bad_desc_num;
2601                                 rx_ring->adapter->reset_reason =
2602                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2603                         } else {
2604                                 ++rx_ring->rx_stats.bad_req_id;
2605                                 rx_ring->adapter->reset_reason =
2606                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2607                         }
2608                         rx_ring->adapter->trigger_reset = true;
2609                         return 0;
2610                 }
2611
2612                 mbuf = ena_rx_mbuf(rx_ring,
2613                         ena_rx_ctx.ena_bufs,
2614                         ena_rx_ctx.descs,
2615                         &next_to_clean,
2616                         ena_rx_ctx.pkt_offset);
2617                 if (unlikely(mbuf == NULL)) {
2618                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2619                                 rx_ring->empty_rx_reqs[next_to_clean] =
2620                                         rx_ring->ena_bufs[i].req_id;
2621                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2622                                         next_to_clean, rx_ring->size_mask);
2623                         }
2624                         break;
2625                 }
2626
2627                 /* fill mbuf attributes if any */
2628                 ena_rx_mbuf_prepare(rx_ring, mbuf, &ena_rx_ctx, fill_hash);
2629
2630                 if (unlikely(mbuf->ol_flags &
2631                                 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD)))
2632                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2633
2634                 rx_pkts[completed] = mbuf;
2635                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2636         }
2637
2638         rx_ring->rx_stats.cnt += completed;
2639         rx_ring->next_to_clean = next_to_clean;
2640
2641         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2642
2643         /* Burst refill to save doorbells, memory barriers, const interval */
2644         if (free_queue_entries >= rx_ring->rx_free_thresh) {
2645                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2646                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2647         }
2648
2649         return completed;
2650 }
2651
2652 static uint16_t
2653 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2654                 uint16_t nb_pkts)
2655 {
2656         int32_t ret;
2657         uint32_t i;
2658         struct rte_mbuf *m;
2659         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2660         struct ena_adapter *adapter = tx_ring->adapter;
2661         struct rte_ipv4_hdr *ip_hdr;
2662         uint64_t ol_flags;
2663         uint64_t l4_csum_flag;
2664         uint64_t dev_offload_capa;
2665         uint16_t frag_field;
2666         bool need_pseudo_csum;
2667
2668         dev_offload_capa = adapter->offloads.tx_offloads;
2669         for (i = 0; i != nb_pkts; i++) {
2670                 m = tx_pkts[i];
2671                 ol_flags = m->ol_flags;
2672
2673                 /* Check if any offload flag was set */
2674                 if (ol_flags == 0)
2675                         continue;
2676
2677                 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2678                 /* SCTP checksum offload is not supported by the ENA. */
2679                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2680                     l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2681                         PMD_TX_LOG(DEBUG,
2682                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2683                                 i, ol_flags);
2684                         rte_errno = ENOTSUP;
2685                         return i;
2686                 }
2687
2688                 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2689                     !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2690                       m->nb_segs == tx_ring->sgl_size &&
2691                       m->data_len < tx_ring->tx_max_header_size))) {
2692                         PMD_TX_LOG(DEBUG,
2693                                 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2694                                 i, m->nb_segs);
2695                         rte_errno = EINVAL;
2696                         return i;
2697                 }
2698
2699 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2700                 /* Check if requested offload is also enabled for the queue */
2701                 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2702                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2703                     (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2704                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2705                     (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2706                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2707                         PMD_TX_LOG(DEBUG,
2708                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2709                                 i, m->nb_segs, tx_ring->id);
2710                         rte_errno = EINVAL;
2711                         return i;
2712                 }
2713
2714                 /* The caller is obligated to set l2 and l3 len if any cksum
2715                  * offload is enabled.
2716                  */
2717                 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2718                     (m->l2_len == 0 || m->l3_len == 0))) {
2719                         PMD_TX_LOG(DEBUG,
2720                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2721                                 i);
2722                         rte_errno = EINVAL;
2723                         return i;
2724                 }
2725                 ret = rte_validate_tx_offload(m);
2726                 if (ret != 0) {
2727                         rte_errno = -ret;
2728                         return i;
2729                 }
2730 #endif
2731
2732                 /* Verify HW support for requested offloads and determine if
2733                  * pseudo header checksum is needed.
2734                  */
2735                 need_pseudo_csum = false;
2736                 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2737                         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2738                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2739                                 rte_errno = ENOTSUP;
2740                                 return i;
2741                         }
2742
2743                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2744                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2745                                 rte_errno = ENOTSUP;
2746                                 return i;
2747                         }
2748
2749                         /* Check HW capabilities and if pseudo csum is needed
2750                          * for L4 offloads.
2751                          */
2752                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2753                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2754                                 if (dev_offload_capa &
2755                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2756                                         need_pseudo_csum = true;
2757                                 } else {
2758                                         rte_errno = ENOTSUP;
2759                                         return i;
2760                                 }
2761                         }
2762
2763                         /* Parse the DF flag */
2764                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2765                                 struct rte_ipv4_hdr *, m->l2_len);
2766                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2767                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2768                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2769                         } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2770                                 /* In case we are supposed to TSO and have DF
2771                                  * not set (DF=0) hardware must be provided with
2772                                  * partial checksum.
2773                                  */
2774                                 need_pseudo_csum = true;
2775                         }
2776                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2777                         /* There is no support for IPv6 TSO as for now. */
2778                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2779                                 rte_errno = ENOTSUP;
2780                                 return i;
2781                         }
2782
2783                         /* Check HW capabilities and if pseudo csum is needed */
2784                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2785                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2786                                 if (dev_offload_capa &
2787                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2788                                         need_pseudo_csum = true;
2789                                 } else {
2790                                         rte_errno = ENOTSUP;
2791                                         return i;
2792                                 }
2793                         }
2794                 }
2795
2796                 if (need_pseudo_csum) {
2797                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2798                         if (ret != 0) {
2799                                 rte_errno = -ret;
2800                                 return i;
2801                         }
2802                 }
2803         }
2804
2805         return i;
2806 }
2807
2808 static void ena_update_hints(struct ena_adapter *adapter,
2809                              struct ena_admin_ena_hw_hints *hints)
2810 {
2811         if (hints->admin_completion_tx_timeout)
2812                 adapter->ena_dev.admin_queue.completion_timeout =
2813                         hints->admin_completion_tx_timeout * 1000;
2814
2815         if (hints->mmio_read_timeout)
2816                 /* convert to usec */
2817                 adapter->ena_dev.mmio_read.reg_read_to =
2818                         hints->mmio_read_timeout * 1000;
2819
2820         if (hints->missing_tx_completion_timeout) {
2821                 if (hints->missing_tx_completion_timeout ==
2822                     ENA_HW_HINTS_NO_TIMEOUT) {
2823                         adapter->missing_tx_completion_to =
2824                                 ENA_HW_HINTS_NO_TIMEOUT;
2825                 } else {
2826                         /* Convert from msecs to ticks */
2827                         adapter->missing_tx_completion_to = rte_get_timer_hz() *
2828                                 hints->missing_tx_completion_timeout / 1000;
2829                         adapter->tx_cleanup_stall_delay =
2830                                 adapter->missing_tx_completion_to / 2;
2831                 }
2832         }
2833
2834         if (hints->driver_watchdog_timeout) {
2835                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2836                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2837                 else
2838                         // Convert msecs to ticks
2839                         adapter->keep_alive_timeout =
2840                                 (hints->driver_watchdog_timeout *
2841                                 rte_get_timer_hz()) / 1000;
2842         }
2843 }
2844
2845 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2846         struct ena_tx_buffer *tx_info,
2847         struct rte_mbuf *mbuf,
2848         void **push_header,
2849         uint16_t *header_len)
2850 {
2851         struct ena_com_buf *ena_buf;
2852         uint16_t delta, seg_len, push_len;
2853
2854         delta = 0;
2855         seg_len = mbuf->data_len;
2856
2857         tx_info->mbuf = mbuf;
2858         ena_buf = tx_info->bufs;
2859
2860         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2861                 /*
2862                  * Tx header might be (and will be in most cases) smaller than
2863                  * tx_max_header_size. But it's not an issue to send more data
2864                  * to the device, than actually needed if the mbuf size is
2865                  * greater than tx_max_header_size.
2866                  */
2867                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2868                 *header_len = push_len;
2869
2870                 if (likely(push_len <= seg_len)) {
2871                         /* If the push header is in the single segment, then
2872                          * just point it to the 1st mbuf data.
2873                          */
2874                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2875                 } else {
2876                         /* If the push header lays in the several segments, copy
2877                          * it to the intermediate buffer.
2878                          */
2879                         rte_pktmbuf_read(mbuf, 0, push_len,
2880                                 tx_ring->push_buf_intermediate_buf);
2881                         *push_header = tx_ring->push_buf_intermediate_buf;
2882                         delta = push_len - seg_len;
2883                 }
2884         } else {
2885                 *push_header = NULL;
2886                 *header_len = 0;
2887                 push_len = 0;
2888         }
2889
2890         /* Process first segment taking into consideration pushed header */
2891         if (seg_len > push_len) {
2892                 ena_buf->paddr = mbuf->buf_iova +
2893                                 mbuf->data_off +
2894                                 push_len;
2895                 ena_buf->len = seg_len - push_len;
2896                 ena_buf++;
2897                 tx_info->num_of_bufs++;
2898         }
2899
2900         while ((mbuf = mbuf->next) != NULL) {
2901                 seg_len = mbuf->data_len;
2902
2903                 /* Skip mbufs if whole data is pushed as a header */
2904                 if (unlikely(delta > seg_len)) {
2905                         delta -= seg_len;
2906                         continue;
2907                 }
2908
2909                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2910                 ena_buf->len = seg_len - delta;
2911                 ena_buf++;
2912                 tx_info->num_of_bufs++;
2913
2914                 delta = 0;
2915         }
2916 }
2917
2918 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2919 {
2920         struct ena_tx_buffer *tx_info;
2921         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2922         uint16_t next_to_use;
2923         uint16_t header_len;
2924         uint16_t req_id;
2925         void *push_header;
2926         int nb_hw_desc;
2927         int rc;
2928
2929         /* Checking for space for 2 additional metadata descriptors due to
2930          * possible header split and metadata descriptor
2931          */
2932         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2933                                           mbuf->nb_segs + 2)) {
2934                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2935                 return ENA_COM_NO_MEM;
2936         }
2937
2938         next_to_use = tx_ring->next_to_use;
2939
2940         req_id = tx_ring->empty_tx_reqs[next_to_use];
2941         tx_info = &tx_ring->tx_buffer_info[req_id];
2942         tx_info->num_of_bufs = 0;
2943         RTE_ASSERT(tx_info->mbuf == NULL);
2944
2945         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2946
2947         ena_tx_ctx.ena_bufs = tx_info->bufs;
2948         ena_tx_ctx.push_header = push_header;
2949         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2950         ena_tx_ctx.req_id = req_id;
2951         ena_tx_ctx.header_len = header_len;
2952
2953         /* Set Tx offloads flags, if applicable */
2954         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2955                 tx_ring->disable_meta_caching);
2956
2957         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2958                         &ena_tx_ctx))) {
2959                 PMD_TX_LOG(DEBUG,
2960                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2961                         tx_ring->id);
2962                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2963                 tx_ring->tx_stats.doorbells++;
2964                 tx_ring->pkts_without_db = false;
2965         }
2966
2967         /* prepare the packet's descriptors to dma engine */
2968         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2969                 &nb_hw_desc);
2970         if (unlikely(rc)) {
2971                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2972                 ++tx_ring->tx_stats.prepare_ctx_err;
2973                 tx_ring->adapter->reset_reason =
2974                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2975                 tx_ring->adapter->trigger_reset = true;
2976                 return rc;
2977         }
2978
2979         tx_info->tx_descs = nb_hw_desc;
2980         tx_info->timestamp = rte_get_timer_cycles();
2981
2982         tx_ring->tx_stats.cnt++;
2983         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2984
2985         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2986                 tx_ring->size_mask);
2987
2988         return 0;
2989 }
2990
2991 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2992 {
2993         unsigned int total_tx_descs = 0;
2994         uint16_t cleanup_budget;
2995         uint16_t next_to_clean = tx_ring->next_to_clean;
2996
2997         /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
2998         cleanup_budget = tx_ring->size_mask;
2999
3000         while (likely(total_tx_descs < cleanup_budget)) {
3001                 struct rte_mbuf *mbuf;
3002                 struct ena_tx_buffer *tx_info;
3003                 uint16_t req_id;
3004
3005                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
3006                         break;
3007
3008                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
3009                         break;
3010
3011                 /* Get Tx info & store how many descs were processed  */
3012                 tx_info = &tx_ring->tx_buffer_info[req_id];
3013                 tx_info->timestamp = 0;
3014
3015                 mbuf = tx_info->mbuf;
3016                 rte_pktmbuf_free(mbuf);
3017
3018                 tx_info->mbuf = NULL;
3019                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
3020
3021                 total_tx_descs += tx_info->tx_descs;
3022
3023                 /* Put back descriptor to the ring for reuse */
3024                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
3025                         tx_ring->size_mask);
3026         }
3027
3028         if (likely(total_tx_descs > 0)) {
3029                 /* acknowledge completion of sent packets */
3030                 tx_ring->next_to_clean = next_to_clean;
3031                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
3032                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
3033         }
3034
3035         /* Notify completion handler that the cleanup was just called */
3036         tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
3037 }
3038
3039 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
3040                                   uint16_t nb_pkts)
3041 {
3042         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
3043         int available_desc;
3044         uint16_t sent_idx = 0;
3045
3046 #ifdef RTE_ETHDEV_DEBUG_TX
3047         /* Check adapter state */
3048         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
3049                 PMD_TX_LOG(ALERT,
3050                         "Trying to xmit pkts while device is NOT running\n");
3051                 return 0;
3052         }
3053 #endif
3054
3055         available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3056         if (available_desc < tx_ring->tx_free_thresh)
3057                 ena_tx_cleanup(tx_ring);
3058
3059         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
3060                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
3061                         break;
3062                 tx_ring->pkts_without_db = true;
3063                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
3064                         tx_ring->size_mask)]);
3065         }
3066
3067         /* If there are ready packets to be xmitted... */
3068         if (likely(tx_ring->pkts_without_db)) {
3069                 /* ...let HW do its best :-) */
3070                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
3071                 tx_ring->tx_stats.doorbells++;
3072                 tx_ring->pkts_without_db = false;
3073         }
3074
3075         tx_ring->tx_stats.available_desc =
3076                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3077         tx_ring->tx_stats.tx_poll++;
3078
3079         return sent_idx;
3080 }
3081
3082 int ena_copy_eni_stats(struct ena_adapter *adapter, struct ena_stats_eni *stats)
3083 {
3084         int rc;
3085
3086         rte_spinlock_lock(&adapter->admin_lock);
3087         /* Retrieve and store the latest statistics from the AQ. This ensures
3088          * that previous value is returned in case of a com error.
3089          */
3090         rc = ENA_PROXY(adapter, ena_com_get_eni_stats, &adapter->ena_dev,
3091                 (struct ena_admin_eni_stats *)stats);
3092         rte_spinlock_unlock(&adapter->admin_lock);
3093         if (rc != 0) {
3094                 if (rc == ENA_COM_UNSUPPORTED) {
3095                         PMD_DRV_LOG(DEBUG,
3096                                 "Retrieving ENI metrics is not supported\n");
3097                 } else {
3098                         PMD_DRV_LOG(WARNING,
3099                                 "Failed to get ENI metrics, rc: %d\n", rc);
3100                 }
3101                 return rc;
3102         }
3103
3104         return 0;
3105 }
3106
3107 /**
3108  * DPDK callback to retrieve names of extended device statistics
3109  *
3110  * @param dev
3111  *   Pointer to Ethernet device structure.
3112  * @param[out] xstats_names
3113  *   Buffer to insert names into.
3114  * @param n
3115  *   Number of names.
3116  *
3117  * @return
3118  *   Number of xstats names.
3119  */
3120 static int ena_xstats_get_names(struct rte_eth_dev *dev,
3121                                 struct rte_eth_xstat_name *xstats_names,
3122                                 unsigned int n)
3123 {
3124         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3125         unsigned int stat, i, count = 0;
3126
3127         if (n < xstats_count || !xstats_names)
3128                 return xstats_count;
3129
3130         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
3131                 strcpy(xstats_names[count].name,
3132                         ena_stats_global_strings[stat].name);
3133
3134         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
3135                 strcpy(xstats_names[count].name,
3136                         ena_stats_eni_strings[stat].name);
3137
3138         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
3139                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
3140                         snprintf(xstats_names[count].name,
3141                                 sizeof(xstats_names[count].name),
3142                                 "rx_q%d_%s", i,
3143                                 ena_stats_rx_strings[stat].name);
3144
3145         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
3146                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
3147                         snprintf(xstats_names[count].name,
3148                                 sizeof(xstats_names[count].name),
3149                                 "tx_q%d_%s", i,
3150                                 ena_stats_tx_strings[stat].name);
3151
3152         return xstats_count;
3153 }
3154
3155 /**
3156  * DPDK callback to get extended device statistics.
3157  *
3158  * @param dev
3159  *   Pointer to Ethernet device structure.
3160  * @param[out] stats
3161  *   Stats table output buffer.
3162  * @param n
3163  *   The size of the stats table.
3164  *
3165  * @return
3166  *   Number of xstats on success, negative on failure.
3167  */
3168 static int ena_xstats_get(struct rte_eth_dev *dev,
3169                           struct rte_eth_xstat *xstats,
3170                           unsigned int n)
3171 {
3172         struct ena_adapter *adapter = dev->data->dev_private;
3173         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3174         struct ena_stats_eni eni_stats;
3175         unsigned int stat, i, count = 0;
3176         int stat_offset;
3177         void *stats_begin;
3178
3179         if (n < xstats_count)
3180                 return xstats_count;
3181
3182         if (!xstats)
3183                 return 0;
3184
3185         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
3186                 stat_offset = ena_stats_global_strings[stat].stat_offset;
3187                 stats_begin = &adapter->dev_stats;
3188
3189                 xstats[count].id = count;
3190                 xstats[count].value = *((uint64_t *)
3191                         ((char *)stats_begin + stat_offset));
3192         }
3193
3194         /* Even if the function below fails, we should copy previous (or initial
3195          * values) to keep structure of rte_eth_xstat consistent.
3196          */
3197         ena_copy_eni_stats(adapter, &eni_stats);
3198         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
3199                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
3200                 stats_begin = &eni_stats;
3201
3202                 xstats[count].id = count;
3203                 xstats[count].value = *((uint64_t *)
3204                     ((char *)stats_begin + stat_offset));
3205         }
3206
3207         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
3208                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
3209                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
3210                         stats_begin = &adapter->rx_ring[i].rx_stats;
3211
3212                         xstats[count].id = count;
3213                         xstats[count].value = *((uint64_t *)
3214                                 ((char *)stats_begin + stat_offset));
3215                 }
3216         }
3217
3218         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
3219                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
3220                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
3221                         stats_begin = &adapter->tx_ring[i].rx_stats;
3222
3223                         xstats[count].id = count;
3224                         xstats[count].value = *((uint64_t *)
3225                                 ((char *)stats_begin + stat_offset));
3226                 }
3227         }
3228
3229         return count;
3230 }
3231
3232 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
3233                                 const uint64_t *ids,
3234                                 uint64_t *values,
3235                                 unsigned int n)
3236 {
3237         struct ena_adapter *adapter = dev->data->dev_private;
3238         struct ena_stats_eni eni_stats;
3239         uint64_t id;
3240         uint64_t rx_entries, tx_entries;
3241         unsigned int i;
3242         int qid;
3243         int valid = 0;
3244         bool was_eni_copied = false;
3245
3246         for (i = 0; i < n; ++i) {
3247                 id = ids[i];
3248                 /* Check if id belongs to global statistics */
3249                 if (id < ENA_STATS_ARRAY_GLOBAL) {
3250                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
3251                         ++valid;
3252                         continue;
3253                 }
3254
3255                 /* Check if id belongs to ENI statistics */
3256                 id -= ENA_STATS_ARRAY_GLOBAL;
3257                 if (id < ENA_STATS_ARRAY_ENI) {
3258                         /* Avoid reading ENI stats multiple times in a single
3259                          * function call, as it requires communication with the
3260                          * admin queue.
3261                          */
3262                         if (!was_eni_copied) {
3263                                 was_eni_copied = true;
3264                                 ena_copy_eni_stats(adapter, &eni_stats);
3265                         }
3266                         values[i] = *((uint64_t *)&eni_stats + id);
3267                         ++valid;
3268                         continue;
3269                 }
3270
3271                 /* Check if id belongs to rx queue statistics */
3272                 id -= ENA_STATS_ARRAY_ENI;
3273                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
3274                 if (id < rx_entries) {
3275                         qid = id % dev->data->nb_rx_queues;
3276                         id /= dev->data->nb_rx_queues;
3277                         values[i] = *((uint64_t *)
3278                                 &adapter->rx_ring[qid].rx_stats + id);
3279                         ++valid;
3280                         continue;
3281                 }
3282                                 /* Check if id belongs to rx queue statistics */
3283                 id -= rx_entries;
3284                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
3285                 if (id < tx_entries) {
3286                         qid = id % dev->data->nb_tx_queues;
3287                         id /= dev->data->nb_tx_queues;
3288                         values[i] = *((uint64_t *)
3289                                 &adapter->tx_ring[qid].tx_stats + id);
3290                         ++valid;
3291                         continue;
3292                 }
3293         }
3294
3295         return valid;
3296 }
3297
3298 static int ena_process_bool_devarg(const char *key,
3299                                    const char *value,
3300                                    void *opaque)
3301 {
3302         struct ena_adapter *adapter = opaque;
3303         bool bool_value;
3304
3305         /* Parse the value. */
3306         if (strcmp(value, "1") == 0) {
3307                 bool_value = true;
3308         } else if (strcmp(value, "0") == 0) {
3309                 bool_value = false;
3310         } else {
3311                 PMD_INIT_LOG(ERR,
3312                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3313                         value, key);
3314                 return -EINVAL;
3315         }
3316
3317         /* Now, assign it to the proper adapter field. */
3318         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3319                 adapter->use_large_llq_hdr = bool_value;
3320
3321         return 0;
3322 }
3323
3324 static int ena_parse_devargs(struct ena_adapter *adapter,
3325                              struct rte_devargs *devargs)
3326 {
3327         static const char * const allowed_args[] = {
3328                 ENA_DEVARG_LARGE_LLQ_HDR,
3329                 NULL,
3330         };
3331         struct rte_kvargs *kvlist;
3332         int rc;
3333
3334         if (devargs == NULL)
3335                 return 0;
3336
3337         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3338         if (kvlist == NULL) {
3339                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3340                         devargs->args);
3341                 return -EINVAL;
3342         }
3343
3344         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3345                 ena_process_bool_devarg, adapter);
3346
3347         rte_kvargs_free(kvlist);
3348
3349         return rc;
3350 }
3351
3352 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3353 {
3354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3355         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3356         int rc;
3357         uint16_t vectors_nb, i;
3358         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3359
3360         if (!rx_intr_requested)
3361                 return 0;
3362
3363         if (!rte_intr_cap_multiple(intr_handle)) {
3364                 PMD_DRV_LOG(ERR,
3365                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3366                 return -ENOTSUP;
3367         }
3368
3369         /* Disable interrupt mapping before the configuration starts. */
3370         rte_intr_disable(intr_handle);
3371
3372         /* Verify if there are enough vectors available. */
3373         vectors_nb = dev->data->nb_rx_queues;
3374         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3375                 PMD_DRV_LOG(ERR,
3376                         "Too many Rx interrupts requested, maximum number: %d\n",
3377                         RTE_MAX_RXTX_INTR_VEC_ID);
3378                 rc = -ENOTSUP;
3379                 goto enable_intr;
3380         }
3381
3382         /* Allocate the vector list */
3383         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3384                                            dev->data->nb_rx_queues)) {
3385                 PMD_DRV_LOG(ERR,
3386                         "Failed to allocate interrupt vector for %d queues\n",
3387                         dev->data->nb_rx_queues);
3388                 rc = -ENOMEM;
3389                 goto enable_intr;
3390         }
3391
3392         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3393         if (rc != 0)
3394                 goto free_intr_vec;
3395
3396         if (!rte_intr_allow_others(intr_handle)) {
3397                 PMD_DRV_LOG(ERR,
3398                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3399                 goto disable_intr_efd;
3400         }
3401
3402         for (i = 0; i < vectors_nb; ++i)
3403                 if (rte_intr_vec_list_index_set(intr_handle, i,
3404                                            RTE_INTR_VEC_RXTX_OFFSET + i))
3405                         goto disable_intr_efd;
3406
3407         rte_intr_enable(intr_handle);
3408         return 0;
3409
3410 disable_intr_efd:
3411         rte_intr_efd_disable(intr_handle);
3412 free_intr_vec:
3413         rte_intr_vec_list_free(intr_handle);
3414 enable_intr:
3415         rte_intr_enable(intr_handle);
3416         return rc;
3417 }
3418
3419 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3420                                  uint16_t queue_id,
3421                                  bool unmask)
3422 {
3423         struct ena_adapter *adapter = dev->data->dev_private;
3424         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3425         struct ena_eth_io_intr_reg intr_reg;
3426
3427         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3428         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3429 }
3430
3431 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3432                                     uint16_t queue_id)
3433 {
3434         ena_rx_queue_intr_set(dev, queue_id, true);
3435
3436         return 0;
3437 }
3438
3439 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3440                                      uint16_t queue_id)
3441 {
3442         ena_rx_queue_intr_set(dev, queue_id, false);
3443
3444         return 0;
3445 }
3446
3447 static int ena_configure_aenq(struct ena_adapter *adapter)
3448 {
3449         uint32_t aenq_groups = adapter->all_aenq_groups;
3450         int rc;
3451
3452         /* All_aenq_groups holds all AENQ functions supported by the device and
3453          * the HW, so at first we need to be sure the LSC request is valid.
3454          */
3455         if (adapter->edev_data->dev_conf.intr_conf.lsc != 0) {
3456                 if (!(aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) {
3457                         PMD_DRV_LOG(ERR,
3458                                 "LSC requested, but it's not supported by the AENQ\n");
3459                         return -EINVAL;
3460                 }
3461         } else {
3462                 /* If LSC wasn't enabled by the app, let's enable all supported
3463                  * AENQ procedures except the LSC.
3464                  */
3465                 aenq_groups &= ~BIT(ENA_ADMIN_LINK_CHANGE);
3466         }
3467
3468         rc = ena_com_set_aenq_config(&adapter->ena_dev, aenq_groups);
3469         if (rc != 0) {
3470                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc=%d\n", rc);
3471                 return rc;
3472         }
3473
3474         adapter->active_aenq_groups = aenq_groups;
3475
3476         return 0;
3477 }
3478
3479 int ena_mp_indirect_table_set(struct ena_adapter *adapter)
3480 {
3481         return ENA_PROXY(adapter, ena_com_indirect_table_set, &adapter->ena_dev);
3482 }
3483
3484 int ena_mp_indirect_table_get(struct ena_adapter *adapter,
3485                               uint32_t *indirect_table)
3486 {
3487         return ENA_PROXY(adapter, ena_com_indirect_table_get, &adapter->ena_dev,
3488                 indirect_table);
3489 }
3490
3491 /*********************************************************************
3492  *  PMD configuration
3493  *********************************************************************/
3494 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3495         struct rte_pci_device *pci_dev)
3496 {
3497         return rte_eth_dev_pci_generic_probe(pci_dev,
3498                 sizeof(struct ena_adapter), eth_ena_dev_init);
3499 }
3500
3501 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3502 {
3503         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3504 }
3505
3506 static struct rte_pci_driver rte_ena_pmd = {
3507         .id_table = pci_id_ena_map,
3508         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3509                      RTE_PCI_DRV_WC_ACTIVATE,
3510         .probe = eth_ena_pci_probe,
3511         .remove = eth_ena_pci_remove,
3512 };
3513
3514 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3515 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3516 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3517 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3518 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3519 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3520 #ifdef RTE_ETHDEV_DEBUG_RX
3521 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3522 #endif
3523 #ifdef RTE_ETHDEV_DEBUG_TX
3524 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3525 #endif
3526 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3527
3528 /******************************************************************************
3529  ******************************** AENQ Handlers *******************************
3530  *****************************************************************************/
3531 static void ena_update_on_link_change(void *adapter_data,
3532                                       struct ena_admin_aenq_entry *aenq_e)
3533 {
3534         struct rte_eth_dev *eth_dev = adapter_data;
3535         struct ena_adapter *adapter = eth_dev->data->dev_private;
3536         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3537         uint32_t status;
3538
3539         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3540
3541         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3542         adapter->link_status = status;
3543
3544         ena_link_update(eth_dev, 0);
3545         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3546 }
3547
3548 static void ena_notification(void *adapter_data,
3549                              struct ena_admin_aenq_entry *aenq_e)
3550 {
3551         struct rte_eth_dev *eth_dev = adapter_data;
3552         struct ena_adapter *adapter = eth_dev->data->dev_private;
3553         struct ena_admin_ena_hw_hints *hints;
3554
3555         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3556                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3557                         aenq_e->aenq_common_desc.group,
3558                         ENA_ADMIN_NOTIFICATION);
3559
3560         switch (aenq_e->aenq_common_desc.syndrome) {
3561         case ENA_ADMIN_UPDATE_HINTS:
3562                 hints = (struct ena_admin_ena_hw_hints *)
3563                         (&aenq_e->inline_data_w4);
3564                 ena_update_hints(adapter, hints);
3565                 break;
3566         default:
3567                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3568                         aenq_e->aenq_common_desc.syndrome);
3569         }
3570 }
3571
3572 static void ena_keep_alive(void *adapter_data,
3573                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3574 {
3575         struct rte_eth_dev *eth_dev = adapter_data;
3576         struct ena_adapter *adapter = eth_dev->data->dev_private;
3577         struct ena_admin_aenq_keep_alive_desc *desc;
3578         uint64_t rx_drops;
3579         uint64_t tx_drops;
3580
3581         adapter->timestamp_wd = rte_get_timer_cycles();
3582
3583         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3584         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3585         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3586
3587         adapter->drv_stats->rx_drops = rx_drops;
3588         adapter->dev_stats.tx_drops = tx_drops;
3589 }
3590
3591 /**
3592  * This handler will called for unknown event group or unimplemented handlers
3593  **/
3594 static void unimplemented_aenq_handler(__rte_unused void *data,
3595                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3596 {
3597         PMD_DRV_LOG(ERR,
3598                 "Unknown event was received or event with unimplemented handler\n");
3599 }
3600
3601 static struct ena_aenq_handlers aenq_handlers = {
3602         .handlers = {
3603                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3604                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3605                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3606         },
3607         .unimplemented_handler = unimplemented_aenq_handler
3608 };
3609
3610 /*********************************************************************
3611  *  Multi-Process communication request handling (in primary)
3612  *********************************************************************/
3613 static int
3614 ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)
3615 {
3616         const struct ena_mp_body *req =
3617                 (const struct ena_mp_body *)mp_msg->param;
3618         struct ena_adapter *adapter;
3619         struct ena_com_dev *ena_dev;
3620         struct ena_mp_body *rsp;
3621         struct rte_mp_msg mp_rsp;
3622         struct rte_eth_dev *dev;
3623         int res = 0;
3624
3625         rsp = (struct ena_mp_body *)&mp_rsp.param;
3626         mp_msg_init(&mp_rsp, req->type, req->port_id);
3627
3628         if (!rte_eth_dev_is_valid_port(req->port_id)) {
3629                 rte_errno = ENODEV;
3630                 res = -rte_errno;
3631                 PMD_DRV_LOG(ERR, "Unknown port %d in request %d\n",
3632                             req->port_id, req->type);
3633                 goto end;
3634         }
3635         dev = &rte_eth_devices[req->port_id];
3636         adapter = dev->data->dev_private;
3637         ena_dev = &adapter->ena_dev;
3638
3639         switch (req->type) {
3640         case ENA_MP_DEV_STATS_GET:
3641                 res = ena_com_get_dev_basic_stats(ena_dev,
3642                                                   &adapter->basic_stats);
3643                 break;
3644         case ENA_MP_ENI_STATS_GET:
3645                 res = ena_com_get_eni_stats(ena_dev,
3646                         (struct ena_admin_eni_stats *)&adapter->eni_stats);
3647                 break;
3648         case ENA_MP_MTU_SET:
3649                 res = ena_com_set_dev_mtu(ena_dev, req->args.mtu);
3650                 break;
3651         case ENA_MP_IND_TBL_GET:
3652                 res = ena_com_indirect_table_get(ena_dev,
3653                                                  adapter->indirect_table);
3654                 break;
3655         case ENA_MP_IND_TBL_SET:
3656                 res = ena_com_indirect_table_set(ena_dev);
3657                 break;
3658         default:
3659                 PMD_DRV_LOG(ERR, "Unknown request type %d\n", req->type);
3660                 res = -EINVAL;
3661                 break;
3662         }
3663
3664 end:
3665         /* Save processing result in the reply */
3666         rsp->result = res;
3667         /* Return just IPC processing status */
3668         return rte_mp_reply(&mp_rsp, peer);
3669 }