4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 0
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 enum ethtool_stringset {
94 char name[ETH_GSTRING_LEN];
98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
100 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
103 #define ENA_STAT_ENTRY(stat, stat_type) { \
105 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
108 #define ENA_STAT_RX_ENTRY(stat) \
109 ENA_STAT_ENTRY(stat, rx)
111 #define ENA_STAT_TX_ENTRY(stat) \
112 ENA_STAT_ENTRY(stat, tx)
114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
115 ENA_STAT_ENTRY(stat, dev)
118 * Each rte_memzone should have unique name.
119 * To satisfy it, count number of allocation and add it to name.
121 uint32_t ena_alloc_cnt;
123 static const struct ena_stats ena_stats_global_strings[] = {
124 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
125 ENA_STAT_GLOBAL_ENTRY(io_suspend),
126 ENA_STAT_GLOBAL_ENTRY(io_resume),
127 ENA_STAT_GLOBAL_ENTRY(wd_expired),
128 ENA_STAT_GLOBAL_ENTRY(interface_up),
129 ENA_STAT_GLOBAL_ENTRY(interface_down),
130 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
133 static const struct ena_stats ena_stats_tx_strings[] = {
134 ENA_STAT_TX_ENTRY(cnt),
135 ENA_STAT_TX_ENTRY(bytes),
136 ENA_STAT_TX_ENTRY(queue_stop),
137 ENA_STAT_TX_ENTRY(queue_wakeup),
138 ENA_STAT_TX_ENTRY(dma_mapping_err),
139 ENA_STAT_TX_ENTRY(linearize),
140 ENA_STAT_TX_ENTRY(linearize_failed),
141 ENA_STAT_TX_ENTRY(tx_poll),
142 ENA_STAT_TX_ENTRY(doorbells),
143 ENA_STAT_TX_ENTRY(prepare_ctx_err),
144 ENA_STAT_TX_ENTRY(missing_tx_comp),
145 ENA_STAT_TX_ENTRY(bad_req_id),
148 static const struct ena_stats ena_stats_rx_strings[] = {
149 ENA_STAT_RX_ENTRY(cnt),
150 ENA_STAT_RX_ENTRY(bytes),
151 ENA_STAT_RX_ENTRY(refil_partial),
152 ENA_STAT_RX_ENTRY(bad_csum),
153 ENA_STAT_RX_ENTRY(page_alloc_fail),
154 ENA_STAT_RX_ENTRY(skb_alloc_fail),
155 ENA_STAT_RX_ENTRY(dma_mapping_err),
156 ENA_STAT_RX_ENTRY(bad_desc_num),
157 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
160 static const struct ena_stats ena_stats_ena_com_strings[] = {
161 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
162 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
163 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
164 ENA_STAT_ENA_COM_ENTRY(out_of_space),
165 ENA_STAT_ENA_COM_ENTRY(no_completion),
168 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
169 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
170 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
174 DEV_TX_OFFLOAD_UDP_CKSUM |\
175 DEV_TX_OFFLOAD_IPV4_CKSUM |\
176 DEV_TX_OFFLOAD_TCP_TSO)
177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
181 /** Vendor ID used by Amazon devices */
182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
183 /** Amazon devices */
184 #define PCI_DEVICE_ID_ENA_VF 0xEC20
185 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
187 #define ENA_TX_OFFLOAD_MASK (\
192 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
193 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
195 int ena_logtype_init;
196 int ena_logtype_driver;
198 static const struct rte_pci_id pci_id_ena_map[] = {
199 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
200 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
204 static struct ena_aenq_handlers empty_aenq_handlers;
206 static int ena_device_init(struct ena_com_dev *ena_dev,
207 struct ena_com_dev_get_features_ctx *get_feat_ctx);
208 static int ena_dev_configure(struct rte_eth_dev *dev);
209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
214 uint16_t nb_desc, unsigned int socket_id,
215 const struct rte_eth_txconf *tx_conf);
216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
217 uint16_t nb_desc, unsigned int socket_id,
218 const struct rte_eth_rxconf *rx_conf,
219 struct rte_mempool *mp);
220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
221 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
223 static void ena_init_rings(struct ena_adapter *adapter);
224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
225 static int ena_start(struct rte_eth_dev *dev);
226 static void ena_close(struct rte_eth_dev *dev);
227 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
228 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
229 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
230 static void ena_rx_queue_release(void *queue);
231 static void ena_tx_queue_release(void *queue);
232 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
233 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
234 static int ena_link_update(struct rte_eth_dev *dev,
235 int wait_to_complete);
236 static int ena_queue_restart(struct ena_ring *ring);
237 static int ena_queue_restart_all(struct rte_eth_dev *dev,
238 enum ena_ring_type ring_type);
239 static void ena_stats_restart(struct rte_eth_dev *dev);
240 static void ena_infos_get(struct rte_eth_dev *dev,
241 struct rte_eth_dev_info *dev_info);
242 static int ena_rss_reta_update(struct rte_eth_dev *dev,
243 struct rte_eth_rss_reta_entry64 *reta_conf,
245 static int ena_rss_reta_query(struct rte_eth_dev *dev,
246 struct rte_eth_rss_reta_entry64 *reta_conf,
248 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
250 static const struct eth_dev_ops ena_dev_ops = {
251 .dev_configure = ena_dev_configure,
252 .dev_infos_get = ena_infos_get,
253 .rx_queue_setup = ena_rx_queue_setup,
254 .tx_queue_setup = ena_tx_queue_setup,
255 .dev_start = ena_start,
256 .link_update = ena_link_update,
257 .stats_get = ena_stats_get,
258 .mtu_set = ena_mtu_set,
259 .rx_queue_release = ena_rx_queue_release,
260 .tx_queue_release = ena_tx_queue_release,
261 .dev_close = ena_close,
262 .reta_update = ena_rss_reta_update,
263 .reta_query = ena_rss_reta_query,
266 #define NUMA_NO_NODE SOCKET_ID_ANY
268 static inline int ena_cpu_to_node(int cpu)
270 struct rte_config *config = rte_eal_get_configuration();
271 struct rte_fbarray *arr = &config->mem_config->memzones;
272 const struct rte_memzone *mz;
274 if (unlikely(cpu >= RTE_MAX_MEMZONE))
277 mz = rte_fbarray_get(arr, cpu);
279 return mz->socket_id;
282 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
283 struct ena_com_rx_ctx *ena_rx_ctx)
285 uint64_t ol_flags = 0;
286 uint32_t packet_type = 0;
288 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
289 packet_type |= RTE_PTYPE_L4_TCP;
290 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
291 packet_type |= RTE_PTYPE_L4_UDP;
293 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
294 packet_type |= RTE_PTYPE_L3_IPV4;
295 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
296 packet_type |= RTE_PTYPE_L3_IPV6;
298 if (unlikely(ena_rx_ctx->l4_csum_err))
299 ol_flags |= PKT_RX_L4_CKSUM_BAD;
300 if (unlikely(ena_rx_ctx->l3_csum_err))
301 ol_flags |= PKT_RX_IP_CKSUM_BAD;
303 mbuf->ol_flags = ol_flags;
304 mbuf->packet_type = packet_type;
307 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
308 struct ena_com_tx_ctx *ena_tx_ctx,
309 uint64_t queue_offloads)
311 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
313 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
314 (queue_offloads & QUEUE_OFFLOADS)) {
315 /* check if TSO is required */
316 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
317 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
318 ena_tx_ctx->tso_enable = true;
320 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
323 /* check if L3 checksum is needed */
324 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
325 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
326 ena_tx_ctx->l3_csum_enable = true;
328 if (mbuf->ol_flags & PKT_TX_IPV6) {
329 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
331 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
333 /* set don't fragment (DF) flag */
334 if (mbuf->packet_type &
335 (RTE_PTYPE_L4_NONFRAG
336 | RTE_PTYPE_INNER_L4_NONFRAG))
337 ena_tx_ctx->df = true;
340 /* check if L4 checksum is needed */
341 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
342 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
343 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
344 ena_tx_ctx->l4_csum_enable = true;
345 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
346 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
347 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
348 ena_tx_ctx->l4_csum_enable = true;
350 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
351 ena_tx_ctx->l4_csum_enable = false;
354 ena_meta->mss = mbuf->tso_segsz;
355 ena_meta->l3_hdr_len = mbuf->l3_len;
356 ena_meta->l3_hdr_offset = mbuf->l2_len;
358 ena_tx_ctx->meta_valid = true;
360 ena_tx_ctx->meta_valid = false;
364 static void ena_config_host_info(struct ena_com_dev *ena_dev)
366 struct ena_admin_host_info *host_info;
369 /* Allocate only the host info */
370 rc = ena_com_allocate_host_info(ena_dev);
372 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
376 host_info = ena_dev->host_attr.host_info;
378 host_info->os_type = ENA_ADMIN_OS_DPDK;
379 host_info->kernel_ver = RTE_VERSION;
380 snprintf((char *)host_info->kernel_ver_str,
381 sizeof(host_info->kernel_ver_str),
382 "%s", rte_version());
383 host_info->os_dist = RTE_VERSION;
384 snprintf((char *)host_info->os_dist_str,
385 sizeof(host_info->os_dist_str),
386 "%s", rte_version());
387 host_info->driver_version =
388 (DRV_MODULE_VER_MAJOR) |
389 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
390 (DRV_MODULE_VER_SUBMINOR <<
391 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
393 rc = ena_com_set_host_attributes(ena_dev);
395 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
396 if (rc != -ENA_COM_UNSUPPORTED)
403 ena_com_delete_host_info(ena_dev);
407 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
409 if (sset != ETH_SS_STATS)
412 /* Workaround for clang:
413 * touch internal structures to prevent
416 ENA_TOUCH(ena_stats_global_strings);
417 ENA_TOUCH(ena_stats_tx_strings);
418 ENA_TOUCH(ena_stats_rx_strings);
419 ENA_TOUCH(ena_stats_ena_com_strings);
421 return dev->data->nb_tx_queues *
422 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
423 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
426 static void ena_config_debug_area(struct ena_adapter *adapter)
431 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
433 RTE_LOG(ERR, PMD, "SS count is negative\n");
437 /* allocate 32 bytes for each string and 64bit for the value */
438 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
440 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
442 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
446 rc = ena_com_set_host_attributes(&adapter->ena_dev);
448 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
449 if (rc != -ENA_COM_UNSUPPORTED)
455 ena_com_delete_debug_area(&adapter->ena_dev);
458 static void ena_close(struct rte_eth_dev *dev)
460 struct ena_adapter *adapter =
461 (struct ena_adapter *)(dev->data->dev_private);
463 adapter->state = ENA_ADAPTER_STATE_STOPPED;
465 ena_rx_queue_release_all(dev);
466 ena_tx_queue_release_all(dev);
469 static int ena_rss_reta_update(struct rte_eth_dev *dev,
470 struct rte_eth_rss_reta_entry64 *reta_conf,
473 struct ena_adapter *adapter =
474 (struct ena_adapter *)(dev->data->dev_private);
475 struct ena_com_dev *ena_dev = &adapter->ena_dev;
481 if ((reta_size == 0) || (reta_conf == NULL))
484 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
485 RTE_LOG(WARNING, PMD,
486 "indirection table %d is bigger than supported (%d)\n",
487 reta_size, ENA_RX_RSS_TABLE_SIZE);
492 for (i = 0 ; i < reta_size ; i++) {
493 /* each reta_conf is for 64 entries.
494 * to support 128 we use 2 conf of 64
496 conf_idx = i / RTE_RETA_GROUP_SIZE;
497 idx = i % RTE_RETA_GROUP_SIZE;
498 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
500 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
501 ret = ena_com_indirect_table_fill_entry(ena_dev,
504 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
506 "Cannot fill indirect table\n");
513 ret = ena_com_indirect_table_set(ena_dev);
514 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
515 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
520 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
521 __func__, reta_size, adapter->rte_dev->data->port_id);
526 /* Query redirection table. */
527 static int ena_rss_reta_query(struct rte_eth_dev *dev,
528 struct rte_eth_rss_reta_entry64 *reta_conf,
531 struct ena_adapter *adapter =
532 (struct ena_adapter *)(dev->data->dev_private);
533 struct ena_com_dev *ena_dev = &adapter->ena_dev;
536 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
540 if (reta_size == 0 || reta_conf == NULL ||
541 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
544 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
545 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
546 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
551 for (i = 0 ; i < reta_size ; i++) {
552 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
553 reta_idx = i % RTE_RETA_GROUP_SIZE;
554 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
555 reta_conf[reta_conf_idx].reta[reta_idx] =
556 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
562 static int ena_rss_init_default(struct ena_adapter *adapter)
564 struct ena_com_dev *ena_dev = &adapter->ena_dev;
565 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
569 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
571 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
575 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
576 val = i % nb_rx_queues;
577 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
578 ENA_IO_RXQ_IDX(val));
579 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
580 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
585 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
586 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
587 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
588 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
592 rc = ena_com_set_default_hash_ctrl(ena_dev);
593 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
594 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
598 rc = ena_com_indirect_table_set(ena_dev);
599 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
600 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
603 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
604 adapter->rte_dev->data->port_id);
609 ena_com_rss_destroy(ena_dev);
615 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
617 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
618 int nb_queues = dev->data->nb_rx_queues;
621 for (i = 0; i < nb_queues; i++)
622 ena_rx_queue_release(queues[i]);
625 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
627 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
628 int nb_queues = dev->data->nb_tx_queues;
631 for (i = 0; i < nb_queues; i++)
632 ena_tx_queue_release(queues[i]);
635 static void ena_rx_queue_release(void *queue)
637 struct ena_ring *ring = (struct ena_ring *)queue;
638 struct ena_adapter *adapter = ring->adapter;
641 ena_assert_msg(ring->configured,
642 "API violation - releasing not configured queue");
643 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
646 /* Destroy HW queue */
647 ena_qid = ENA_IO_RXQ_IDX(ring->id);
648 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
651 ena_rx_queue_release_bufs(ring);
653 /* Free ring resources */
654 if (ring->rx_buffer_info)
655 rte_free(ring->rx_buffer_info);
656 ring->rx_buffer_info = NULL;
658 ring->configured = 0;
660 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
661 ring->port_id, ring->id);
664 static void ena_tx_queue_release(void *queue)
666 struct ena_ring *ring = (struct ena_ring *)queue;
667 struct ena_adapter *adapter = ring->adapter;
670 ena_assert_msg(ring->configured,
671 "API violation. Releasing not configured queue");
672 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
675 /* Destroy HW queue */
676 ena_qid = ENA_IO_TXQ_IDX(ring->id);
677 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
680 ena_tx_queue_release_bufs(ring);
682 /* Free ring resources */
683 if (ring->tx_buffer_info)
684 rte_free(ring->tx_buffer_info);
686 if (ring->empty_tx_reqs)
687 rte_free(ring->empty_tx_reqs);
689 ring->empty_tx_reqs = NULL;
690 ring->tx_buffer_info = NULL;
692 ring->configured = 0;
694 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
695 ring->port_id, ring->id);
698 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
700 unsigned int ring_mask = ring->ring_size - 1;
702 while (ring->next_to_clean != ring->next_to_use) {
704 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
707 rte_mbuf_raw_free(m);
709 ring->next_to_clean++;
713 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
717 for (i = 0; i < ring->ring_size; ++i) {
718 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
721 rte_pktmbuf_free(tx_buf->mbuf);
723 ring->next_to_clean++;
727 static int ena_link_update(struct rte_eth_dev *dev,
728 __rte_unused int wait_to_complete)
730 struct rte_eth_link *link = &dev->data->dev_link;
732 link->link_status = ETH_LINK_UP;
733 link->link_speed = ETH_SPEED_NUM_10G;
734 link->link_duplex = ETH_LINK_FULL_DUPLEX;
739 static int ena_queue_restart_all(struct rte_eth_dev *dev,
740 enum ena_ring_type ring_type)
742 struct ena_adapter *adapter =
743 (struct ena_adapter *)(dev->data->dev_private);
744 struct ena_ring *queues = NULL;
748 queues = (ring_type == ENA_RING_TYPE_RX) ?
749 adapter->rx_ring : adapter->tx_ring;
751 for (i = 0; i < adapter->num_queues; i++) {
752 if (queues[i].configured) {
753 if (ring_type == ENA_RING_TYPE_RX) {
755 dev->data->rx_queues[i] == &queues[i],
756 "Inconsistent state of rx queues\n");
759 dev->data->tx_queues[i] == &queues[i],
760 "Inconsistent state of tx queues\n");
763 rc = ena_queue_restart(&queues[i]);
767 "failed to restart queue %d type(%d)",
777 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
779 uint32_t max_frame_len = adapter->max_mtu;
781 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
782 DEV_RX_OFFLOAD_JUMBO_FRAME)
784 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
786 return max_frame_len;
789 static int ena_check_valid_conf(struct ena_adapter *adapter)
791 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
793 if (max_frame_len > adapter->max_mtu) {
794 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
802 ena_calc_queue_size(struct ena_com_dev *ena_dev,
803 struct ena_com_dev_get_features_ctx *get_feat_ctx)
805 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
807 queue_size = RTE_MIN(queue_size,
808 get_feat_ctx->max_queues.max_cq_depth);
809 queue_size = RTE_MIN(queue_size,
810 get_feat_ctx->max_queues.max_sq_depth);
812 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
813 queue_size = RTE_MIN(queue_size,
814 get_feat_ctx->max_queues.max_llq_depth);
816 /* Round down to power of 2 */
817 if (!rte_is_power_of_2(queue_size))
818 queue_size = rte_align32pow2(queue_size >> 1);
820 if (queue_size == 0) {
821 PMD_INIT_LOG(ERR, "Invalid queue size");
828 static void ena_stats_restart(struct rte_eth_dev *dev)
830 struct ena_adapter *adapter =
831 (struct ena_adapter *)(dev->data->dev_private);
833 rte_atomic64_init(&adapter->drv_stats->ierrors);
834 rte_atomic64_init(&adapter->drv_stats->oerrors);
835 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
838 static int ena_stats_get(struct rte_eth_dev *dev,
839 struct rte_eth_stats *stats)
841 struct ena_admin_basic_stats ena_stats;
842 struct ena_adapter *adapter =
843 (struct ena_adapter *)(dev->data->dev_private);
844 struct ena_com_dev *ena_dev = &adapter->ena_dev;
847 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
850 memset(&ena_stats, 0, sizeof(ena_stats));
851 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
853 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
857 /* Set of basic statistics from ENA */
858 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
859 ena_stats.rx_pkts_low);
860 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
861 ena_stats.tx_pkts_low);
862 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
863 ena_stats.rx_bytes_low);
864 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
865 ena_stats.tx_bytes_low);
866 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
867 ena_stats.rx_drops_low);
869 /* Driver related stats */
870 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
871 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
872 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
876 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
878 struct ena_adapter *adapter;
879 struct ena_com_dev *ena_dev;
882 ena_assert_msg(dev->data != NULL, "Uninitialized device");
883 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
884 adapter = (struct ena_adapter *)(dev->data->dev_private);
886 ena_dev = &adapter->ena_dev;
887 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
889 if (mtu > ena_get_mtu_conf(adapter)) {
891 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
892 mtu, ena_get_mtu_conf(adapter));
897 rc = ena_com_set_dev_mtu(ena_dev, mtu);
899 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
901 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
907 static int ena_start(struct rte_eth_dev *dev)
909 struct ena_adapter *adapter =
910 (struct ena_adapter *)(dev->data->dev_private);
913 if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
914 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
915 PMD_INIT_LOG(ERR, "API violation");
919 rc = ena_check_valid_conf(adapter);
923 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
927 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
931 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
932 ETH_MQ_RX_RSS_FLAG) {
933 rc = ena_rss_init_default(adapter);
938 ena_stats_restart(dev);
940 adapter->state = ENA_ADAPTER_STATE_RUNNING;
945 static int ena_queue_restart(struct ena_ring *ring)
949 ena_assert_msg(ring->configured == 1,
950 "Trying to restart unconfigured queue\n");
952 ring->next_to_clean = 0;
953 ring->next_to_use = 0;
955 if (ring->type == ENA_RING_TYPE_TX)
958 bufs_num = ring->ring_size - 1;
959 rc = ena_populate_rx_queue(ring, bufs_num);
960 if (rc != bufs_num) {
961 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
968 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
971 __rte_unused unsigned int socket_id,
972 const struct rte_eth_txconf *tx_conf)
974 struct ena_com_create_io_ctx ctx =
975 /* policy set to _HOST just to satisfy icc compiler */
976 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
977 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
978 struct ena_ring *txq = NULL;
979 struct ena_adapter *adapter =
980 (struct ena_adapter *)(dev->data->dev_private);
984 struct ena_com_dev *ena_dev = &adapter->ena_dev;
986 txq = &adapter->tx_ring[queue_idx];
988 if (txq->configured) {
990 "API violation. Queue %d is already configured\n",
995 if (!rte_is_power_of_2(nb_desc)) {
997 "Unsupported size of RX queue: %d is not a power of 2.",
1002 if (nb_desc > adapter->tx_ring_size) {
1004 "Unsupported size of TX queue (max size: %d)\n",
1005 adapter->tx_ring_size);
1009 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1011 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1013 ctx.msix_vector = -1; /* admin interrupts not used */
1014 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1015 ctx.queue_size = adapter->tx_ring_size;
1016 ctx.numa_node = ena_cpu_to_node(queue_idx);
1018 rc = ena_com_create_io_queue(ena_dev, &ctx);
1021 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1022 queue_idx, ena_qid, rc);
1024 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1025 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1027 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1028 &txq->ena_com_io_sq,
1029 &txq->ena_com_io_cq);
1032 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1034 ena_com_destroy_io_queue(ena_dev, ena_qid);
1038 txq->port_id = dev->data->port_id;
1039 txq->next_to_clean = 0;
1040 txq->next_to_use = 0;
1041 txq->ring_size = nb_desc;
1043 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1044 sizeof(struct ena_tx_buffer) *
1046 RTE_CACHE_LINE_SIZE);
1047 if (!txq->tx_buffer_info) {
1048 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1052 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1053 sizeof(u16) * txq->ring_size,
1054 RTE_CACHE_LINE_SIZE);
1055 if (!txq->empty_tx_reqs) {
1056 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1057 rte_free(txq->tx_buffer_info);
1060 for (i = 0; i < txq->ring_size; i++)
1061 txq->empty_tx_reqs[i] = i;
1063 txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1065 /* Store pointer to this queue in upper layer */
1066 txq->configured = 1;
1067 dev->data->tx_queues[queue_idx] = txq;
1072 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1075 __rte_unused unsigned int socket_id,
1076 __rte_unused const struct rte_eth_rxconf *rx_conf,
1077 struct rte_mempool *mp)
1079 struct ena_com_create_io_ctx ctx =
1080 /* policy set to _HOST just to satisfy icc compiler */
1081 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1082 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1083 struct ena_adapter *adapter =
1084 (struct ena_adapter *)(dev->data->dev_private);
1085 struct ena_ring *rxq = NULL;
1086 uint16_t ena_qid = 0;
1088 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1090 rxq = &adapter->rx_ring[queue_idx];
1091 if (rxq->configured) {
1093 "API violation. Queue %d is already configured\n",
1098 if (!rte_is_power_of_2(nb_desc)) {
1100 "Unsupported size of TX queue: %d is not a power of 2.",
1105 if (nb_desc > adapter->rx_ring_size) {
1107 "Unsupported size of RX queue (max size: %d)\n",
1108 adapter->rx_ring_size);
1112 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1115 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1116 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1117 ctx.msix_vector = -1; /* admin interrupts not used */
1118 ctx.queue_size = adapter->rx_ring_size;
1119 ctx.numa_node = ena_cpu_to_node(queue_idx);
1121 rc = ena_com_create_io_queue(ena_dev, &ctx);
1123 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1126 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1127 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1129 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1130 &rxq->ena_com_io_sq,
1131 &rxq->ena_com_io_cq);
1134 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1136 ena_com_destroy_io_queue(ena_dev, ena_qid);
1139 rxq->port_id = dev->data->port_id;
1140 rxq->next_to_clean = 0;
1141 rxq->next_to_use = 0;
1142 rxq->ring_size = nb_desc;
1145 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1146 sizeof(struct rte_mbuf *) * nb_desc,
1147 RTE_CACHE_LINE_SIZE);
1148 if (!rxq->rx_buffer_info) {
1149 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1153 /* Store pointer to this queue in upper layer */
1154 rxq->configured = 1;
1155 dev->data->rx_queues[queue_idx] = rxq;
1160 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1164 uint16_t ring_size = rxq->ring_size;
1165 uint16_t ring_mask = ring_size - 1;
1166 uint16_t next_to_use = rxq->next_to_use;
1168 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1170 if (unlikely(!count))
1173 in_use = rxq->next_to_use - rxq->next_to_clean;
1174 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1176 count = RTE_MIN(count,
1177 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1179 /* get resources for incoming packets */
1180 rc = rte_mempool_get_bulk(rxq->mb_pool,
1181 (void **)(&mbufs[next_to_use & ring_mask]),
1183 if (unlikely(rc < 0)) {
1184 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1185 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1189 for (i = 0; i < count; i++) {
1190 uint16_t next_to_use_masked = next_to_use & ring_mask;
1191 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1192 struct ena_com_buf ebuf;
1194 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1195 /* prepare physical address for DMA transaction */
1196 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1197 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1198 /* pass resource to device */
1199 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1200 &ebuf, next_to_use_masked);
1202 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1204 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1210 /* When we submitted free recources to device... */
1212 /* ...let HW know that it can fill buffers with data */
1214 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1216 rxq->next_to_use = next_to_use;
1222 static int ena_device_init(struct ena_com_dev *ena_dev,
1223 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1226 bool readless_supported;
1228 /* Initialize mmio registers */
1229 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1231 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1235 /* The PCIe configuration space revision id indicate if mmio reg
1238 readless_supported =
1239 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1240 & ENA_MMIO_DISABLE_REG_READ);
1241 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1244 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1246 RTE_LOG(ERR, PMD, "cannot reset device\n");
1247 goto err_mmio_read_less;
1250 /* check FW version */
1251 rc = ena_com_validate_version(ena_dev);
1253 RTE_LOG(ERR, PMD, "device version is too low\n");
1254 goto err_mmio_read_less;
1257 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1259 /* ENA device administration layer init */
1260 rc = ena_com_admin_init(ena_dev, &empty_aenq_handlers, true);
1263 "cannot initialize ena admin queue with device\n");
1264 goto err_mmio_read_less;
1267 /* To enable the msix interrupts the driver needs to know the number
1268 * of queues. So the driver uses polling mode to retrieve this
1271 ena_com_set_admin_polling_mode(ena_dev, true);
1273 ena_config_host_info(ena_dev);
1275 /* Get Device Attributes and features */
1276 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1279 "cannot get attribute for ena device rc= %d\n", rc);
1280 goto err_admin_init;
1286 ena_com_admin_destroy(ena_dev);
1289 ena_com_mmio_reg_read_request_destroy(ena_dev);
1294 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1296 struct rte_pci_device *pci_dev;
1297 struct ena_adapter *adapter =
1298 (struct ena_adapter *)(eth_dev->data->dev_private);
1299 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1300 struct ena_com_dev_get_features_ctx get_feat_ctx;
1303 static int adapters_found;
1305 memset(adapter, 0, sizeof(struct ena_adapter));
1306 ena_dev = &adapter->ena_dev;
1308 eth_dev->dev_ops = &ena_dev_ops;
1309 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1310 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1311 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1312 adapter->rte_eth_dev_data = eth_dev->data;
1313 adapter->rte_dev = eth_dev;
1315 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1318 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1319 adapter->pdev = pci_dev;
1321 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1322 pci_dev->addr.domain,
1324 pci_dev->addr.devid,
1325 pci_dev->addr.function);
1327 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1328 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1330 /* Present ENA_MEM_BAR indicates available LLQ mode.
1331 * Use corresponding policy
1333 if (adapter->dev_mem_base)
1334 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1335 else if (adapter->regs)
1336 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1338 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1341 ena_dev->reg_bar = adapter->regs;
1342 ena_dev->dmadev = adapter->pdev;
1344 adapter->id_number = adapters_found;
1346 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1347 adapter->id_number);
1349 /* device specific initialization routine */
1350 rc = ena_device_init(ena_dev, &get_feat_ctx);
1352 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1356 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1357 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1359 "Trying to use LLQ but llq_num is 0.\n"
1360 "Fall back into regular queues.");
1361 ena_dev->tx_mem_queue_type =
1362 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1363 adapter->num_queues =
1364 get_feat_ctx.max_queues.max_sq_num;
1366 adapter->num_queues =
1367 get_feat_ctx.max_queues.max_llq_num;
1370 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1373 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1374 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1377 adapter->tx_ring_size = queue_size;
1378 adapter->rx_ring_size = queue_size;
1380 /* prepare ring structures */
1381 ena_init_rings(adapter);
1383 ena_config_debug_area(adapter);
1385 /* Set max MTU for this device */
1386 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1388 /* set device support for TSO */
1389 adapter->tso4_supported = get_feat_ctx.offload.tx &
1390 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1392 /* Copy MAC address and point DPDK to it */
1393 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1394 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1395 (struct ether_addr *)adapter->mac_addr);
1397 adapter->drv_stats = rte_zmalloc("adapter stats",
1398 sizeof(*adapter->drv_stats),
1399 RTE_CACHE_LINE_SIZE);
1400 if (!adapter->drv_stats) {
1401 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1406 adapter->state = ENA_ADAPTER_STATE_INIT;
1411 static int ena_dev_configure(struct rte_eth_dev *dev)
1413 struct ena_adapter *adapter =
1414 (struct ena_adapter *)(dev->data->dev_private);
1416 if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1417 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1418 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1423 switch (adapter->state) {
1424 case ENA_ADAPTER_STATE_INIT:
1425 case ENA_ADAPTER_STATE_STOPPED:
1426 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1428 case ENA_ADAPTER_STATE_CONFIG:
1429 RTE_LOG(WARNING, PMD,
1430 "Ivalid driver state while trying to configure device\n");
1436 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1437 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1441 static void ena_init_rings(struct ena_adapter *adapter)
1445 for (i = 0; i < adapter->num_queues; i++) {
1446 struct ena_ring *ring = &adapter->tx_ring[i];
1448 ring->configured = 0;
1449 ring->type = ENA_RING_TYPE_TX;
1450 ring->adapter = adapter;
1452 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1453 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1456 for (i = 0; i < adapter->num_queues; i++) {
1457 struct ena_ring *ring = &adapter->rx_ring[i];
1459 ring->configured = 0;
1460 ring->type = ENA_RING_TYPE_RX;
1461 ring->adapter = adapter;
1466 static void ena_infos_get(struct rte_eth_dev *dev,
1467 struct rte_eth_dev_info *dev_info)
1469 struct ena_adapter *adapter;
1470 struct ena_com_dev *ena_dev;
1471 struct ena_com_dev_get_features_ctx feat;
1472 uint64_t rx_feat = 0, tx_feat = 0;
1475 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1476 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1477 adapter = (struct ena_adapter *)(dev->data->dev_private);
1479 ena_dev = &adapter->ena_dev;
1480 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1482 dev_info->speed_capa =
1484 ETH_LINK_SPEED_2_5G |
1486 ETH_LINK_SPEED_10G |
1487 ETH_LINK_SPEED_25G |
1488 ETH_LINK_SPEED_40G |
1489 ETH_LINK_SPEED_50G |
1490 ETH_LINK_SPEED_100G;
1492 /* Get supported features from HW */
1493 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1496 "Cannot get attribute for ena device rc= %d\n", rc);
1500 /* Set Tx & Rx features available for device */
1501 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1502 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1504 if (feat.offload.tx &
1505 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1506 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1507 DEV_TX_OFFLOAD_UDP_CKSUM |
1508 DEV_TX_OFFLOAD_TCP_CKSUM;
1510 if (feat.offload.rx_supported &
1511 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1512 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1513 DEV_RX_OFFLOAD_UDP_CKSUM |
1514 DEV_RX_OFFLOAD_TCP_CKSUM;
1516 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1518 /* Inform framework about available features */
1519 dev_info->rx_offload_capa = rx_feat;
1520 dev_info->rx_queue_offload_capa = rx_feat;
1521 dev_info->tx_offload_capa = tx_feat;
1522 dev_info->tx_queue_offload_capa = tx_feat;
1524 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1525 dev_info->max_rx_pktlen = adapter->max_mtu;
1526 dev_info->max_mac_addrs = 1;
1528 dev_info->max_rx_queues = adapter->num_queues;
1529 dev_info->max_tx_queues = adapter->num_queues;
1530 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1532 adapter->tx_supported_offloads = tx_feat;
1533 adapter->rx_supported_offloads = rx_feat;
1536 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1539 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1540 unsigned int ring_size = rx_ring->ring_size;
1541 unsigned int ring_mask = ring_size - 1;
1542 uint16_t next_to_clean = rx_ring->next_to_clean;
1543 uint16_t desc_in_use = 0;
1544 unsigned int recv_idx = 0;
1545 struct rte_mbuf *mbuf = NULL;
1546 struct rte_mbuf *mbuf_head = NULL;
1547 struct rte_mbuf *mbuf_prev = NULL;
1548 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1549 unsigned int completed;
1551 struct ena_com_rx_ctx ena_rx_ctx;
1554 /* Check adapter state */
1555 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1557 "Trying to receive pkts while device is NOT running\n");
1561 desc_in_use = rx_ring->next_to_use - next_to_clean;
1562 if (unlikely(nb_pkts > desc_in_use))
1563 nb_pkts = desc_in_use;
1565 for (completed = 0; completed < nb_pkts; completed++) {
1568 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1569 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1570 ena_rx_ctx.descs = 0;
1571 /* receive packet context */
1572 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1573 rx_ring->ena_com_io_sq,
1576 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1580 if (unlikely(ena_rx_ctx.descs == 0))
1583 while (segments < ena_rx_ctx.descs) {
1584 mbuf = rx_buff_info[next_to_clean & ring_mask];
1585 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1586 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1589 if (segments == 0) {
1590 mbuf->nb_segs = ena_rx_ctx.descs;
1591 mbuf->port = rx_ring->port_id;
1595 /* for multi-segment pkts create mbuf chain */
1596 mbuf_prev->next = mbuf;
1598 mbuf_head->pkt_len += mbuf->data_len;
1605 /* fill mbuf attributes if any */
1606 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1607 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1609 /* pass to DPDK application head mbuf */
1610 rx_pkts[recv_idx] = mbuf_head;
1614 rx_ring->next_to_clean = next_to_clean;
1616 desc_in_use = desc_in_use - completed + 1;
1617 /* Burst refill to save doorbells, memory barriers, const interval */
1618 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1619 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1625 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1631 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1632 struct ipv4_hdr *ip_hdr;
1634 uint16_t frag_field;
1636 for (i = 0; i != nb_pkts; i++) {
1638 ol_flags = m->ol_flags;
1640 if (!(ol_flags & PKT_TX_IPV4))
1643 /* If there was not L2 header length specified, assume it is
1644 * length of the ethernet header.
1646 if (unlikely(m->l2_len == 0))
1647 m->l2_len = sizeof(struct ether_hdr);
1649 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1651 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1653 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1654 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1656 /* If IPv4 header has DF flag enabled and TSO support is
1657 * disabled, partial chcecksum should not be calculated.
1659 if (!tx_ring->adapter->tso4_supported)
1663 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1664 (ol_flags & PKT_TX_L4_MASK) ==
1665 PKT_TX_SCTP_CKSUM) {
1666 rte_errno = -ENOTSUP;
1670 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1671 ret = rte_validate_tx_offload(m);
1678 /* In case we are supposed to TSO and have DF not set (DF=0)
1679 * hardware must be provided with partial checksum, otherwise
1680 * it will take care of necessary calculations.
1683 ret = rte_net_intel_cksum_flags_prepare(m,
1684 ol_flags & ~PKT_TX_TCP_SEG);
1694 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1697 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1698 uint16_t next_to_use = tx_ring->next_to_use;
1699 uint16_t next_to_clean = tx_ring->next_to_clean;
1700 struct rte_mbuf *mbuf;
1701 unsigned int ring_size = tx_ring->ring_size;
1702 unsigned int ring_mask = ring_size - 1;
1703 struct ena_com_tx_ctx ena_tx_ctx;
1704 struct ena_tx_buffer *tx_info;
1705 struct ena_com_buf *ebuf;
1706 uint16_t rc, req_id, total_tx_descs = 0;
1707 uint16_t sent_idx = 0, empty_tx_reqs;
1710 /* Check adapter state */
1711 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1713 "Trying to xmit pkts while device is NOT running\n");
1717 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1718 if (nb_pkts > empty_tx_reqs)
1719 nb_pkts = empty_tx_reqs;
1721 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1722 mbuf = tx_pkts[sent_idx];
1724 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1725 tx_info = &tx_ring->tx_buffer_info[req_id];
1726 tx_info->mbuf = mbuf;
1727 tx_info->num_of_bufs = 0;
1728 ebuf = tx_info->bufs;
1730 /* Prepare TX context */
1731 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1732 memset(&ena_tx_ctx.ena_meta, 0x0,
1733 sizeof(struct ena_com_tx_meta));
1734 ena_tx_ctx.ena_bufs = ebuf;
1735 ena_tx_ctx.req_id = req_id;
1736 if (tx_ring->tx_mem_queue_type ==
1737 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1738 /* prepare the push buffer with
1739 * virtual address of the data
1741 ena_tx_ctx.header_len =
1742 RTE_MIN(mbuf->data_len,
1743 tx_ring->tx_max_header_size);
1744 ena_tx_ctx.push_header =
1745 (void *)((char *)mbuf->buf_addr +
1747 } /* there's no else as we take advantage of memset zeroing */
1749 /* Set TX offloads flags, if applicable */
1750 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1752 if (unlikely(mbuf->ol_flags &
1753 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1754 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1756 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1758 /* Process first segment taking into
1759 * consideration pushed header
1761 if (mbuf->data_len > ena_tx_ctx.header_len) {
1762 ebuf->paddr = mbuf->buf_iova +
1764 ena_tx_ctx.header_len;
1765 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1767 tx_info->num_of_bufs++;
1770 while ((mbuf = mbuf->next) != NULL) {
1771 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1772 ebuf->len = mbuf->data_len;
1774 tx_info->num_of_bufs++;
1777 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1779 /* Write data to device */
1780 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1781 &ena_tx_ctx, &nb_hw_desc);
1785 tx_info->tx_descs = nb_hw_desc;
1790 /* If there are ready packets to be xmitted... */
1792 /* ...let HW do its best :-) */
1794 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1796 tx_ring->next_to_use = next_to_use;
1799 /* Clear complete packets */
1800 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1801 /* Get Tx info & store how many descs were processed */
1802 tx_info = &tx_ring->tx_buffer_info[req_id];
1803 total_tx_descs += tx_info->tx_descs;
1805 /* Free whole mbuf chain */
1806 mbuf = tx_info->mbuf;
1807 rte_pktmbuf_free(mbuf);
1808 tx_info->mbuf = NULL;
1810 /* Put back descriptor to the ring for reuse */
1811 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1814 /* If too many descs to clean, leave it for another run */
1815 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1819 if (total_tx_descs > 0) {
1820 /* acknowledge completion of sent packets */
1821 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1822 tx_ring->next_to_clean = next_to_clean;
1828 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1829 struct rte_pci_device *pci_dev)
1831 return rte_eth_dev_pci_generic_probe(pci_dev,
1832 sizeof(struct ena_adapter), eth_ena_dev_init);
1835 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1837 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1840 static struct rte_pci_driver rte_ena_pmd = {
1841 .id_table = pci_id_ena_map,
1842 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1843 .probe = eth_ena_pci_probe,
1844 .remove = eth_ena_pci_remove,
1847 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1848 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1849 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1851 RTE_INIT(ena_init_log);
1855 ena_logtype_init = rte_log_register("pmd.net.ena.init");
1856 if (ena_logtype_init >= 0)
1857 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1858 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
1859 if (ena_logtype_driver >= 0)
1860 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
1863 /******************************************************************************
1864 ******************************** AENQ Handlers *******************************
1865 *****************************************************************************/
1867 * This handler will called for unknown event group or unimplemented handlers
1869 static void unimplemented_aenq_handler(__rte_unused void *data,
1870 __rte_unused struct ena_admin_aenq_entry *aenq_e)
1872 // Unimplemented handler
1875 static struct ena_aenq_handlers empty_aenq_handlers = {
1877 [ENA_ADMIN_LINK_CHANGE] = unimplemented_aenq_handler,
1878 [ENA_ADMIN_NOTIFICATION] = unimplemented_aenq_handler,
1879 [ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler
1881 .unimplemented_handler = unimplemented_aenq_handler