4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 1
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 #define ENA_MIN_RING_DESC 128
90 enum ethtool_stringset {
96 char name[ETH_GSTRING_LEN];
100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
102 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
105 #define ENA_STAT_ENTRY(stat, stat_type) { \
107 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
110 #define ENA_STAT_RX_ENTRY(stat) \
111 ENA_STAT_ENTRY(stat, rx)
113 #define ENA_STAT_TX_ENTRY(stat) \
114 ENA_STAT_ENTRY(stat, tx)
116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
117 ENA_STAT_ENTRY(stat, dev)
119 #define ENA_MAX_RING_SIZE_RX 8192
120 #define ENA_MAX_RING_SIZE_TX 1024
123 * Each rte_memzone should have unique name.
124 * To satisfy it, count number of allocation and add it to name.
126 uint32_t ena_alloc_cnt;
128 static const struct ena_stats ena_stats_global_strings[] = {
129 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
130 ENA_STAT_GLOBAL_ENTRY(io_suspend),
131 ENA_STAT_GLOBAL_ENTRY(io_resume),
132 ENA_STAT_GLOBAL_ENTRY(wd_expired),
133 ENA_STAT_GLOBAL_ENTRY(interface_up),
134 ENA_STAT_GLOBAL_ENTRY(interface_down),
135 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
138 static const struct ena_stats ena_stats_tx_strings[] = {
139 ENA_STAT_TX_ENTRY(cnt),
140 ENA_STAT_TX_ENTRY(bytes),
141 ENA_STAT_TX_ENTRY(queue_stop),
142 ENA_STAT_TX_ENTRY(queue_wakeup),
143 ENA_STAT_TX_ENTRY(dma_mapping_err),
144 ENA_STAT_TX_ENTRY(linearize),
145 ENA_STAT_TX_ENTRY(linearize_failed),
146 ENA_STAT_TX_ENTRY(tx_poll),
147 ENA_STAT_TX_ENTRY(doorbells),
148 ENA_STAT_TX_ENTRY(prepare_ctx_err),
149 ENA_STAT_TX_ENTRY(missing_tx_comp),
150 ENA_STAT_TX_ENTRY(bad_req_id),
153 static const struct ena_stats ena_stats_rx_strings[] = {
154 ENA_STAT_RX_ENTRY(cnt),
155 ENA_STAT_RX_ENTRY(bytes),
156 ENA_STAT_RX_ENTRY(refil_partial),
157 ENA_STAT_RX_ENTRY(bad_csum),
158 ENA_STAT_RX_ENTRY(page_alloc_fail),
159 ENA_STAT_RX_ENTRY(skb_alloc_fail),
160 ENA_STAT_RX_ENTRY(dma_mapping_err),
161 ENA_STAT_RX_ENTRY(bad_desc_num),
162 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
163 ENA_STAT_TX_ENTRY(bad_req_id),
166 static const struct ena_stats ena_stats_ena_com_strings[] = {
167 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
168 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
169 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
170 ENA_STAT_ENA_COM_ENTRY(out_of_space),
171 ENA_STAT_ENA_COM_ENTRY(no_completion),
174 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
175 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
176 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
177 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
179 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
180 DEV_TX_OFFLOAD_UDP_CKSUM |\
181 DEV_TX_OFFLOAD_IPV4_CKSUM |\
182 DEV_TX_OFFLOAD_TCP_TSO)
183 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
187 /** Vendor ID used by Amazon devices */
188 #define PCI_VENDOR_ID_AMAZON 0x1D0F
189 /** Amazon devices */
190 #define PCI_DEVICE_ID_ENA_VF 0xEC20
191 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
193 #define ENA_TX_OFFLOAD_MASK (\
200 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
201 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
203 int ena_logtype_init;
204 int ena_logtype_driver;
206 static const struct rte_pci_id pci_id_ena_map[] = {
207 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
208 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
212 static struct ena_aenq_handlers aenq_handlers;
214 static int ena_device_init(struct ena_com_dev *ena_dev,
215 struct ena_com_dev_get_features_ctx *get_feat_ctx,
217 static int ena_dev_configure(struct rte_eth_dev *dev);
218 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
220 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
222 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
223 uint16_t nb_desc, unsigned int socket_id,
224 const struct rte_eth_txconf *tx_conf);
225 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
226 uint16_t nb_desc, unsigned int socket_id,
227 const struct rte_eth_rxconf *rx_conf,
228 struct rte_mempool *mp);
229 static uint16_t eth_ena_recv_pkts(void *rx_queue,
230 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
231 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
232 static void ena_init_rings(struct ena_adapter *adapter);
233 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
234 static int ena_start(struct rte_eth_dev *dev);
235 static void ena_stop(struct rte_eth_dev *dev);
236 static void ena_close(struct rte_eth_dev *dev);
237 static int ena_dev_reset(struct rte_eth_dev *dev);
238 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
239 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
240 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
241 static void ena_rx_queue_release(void *queue);
242 static void ena_tx_queue_release(void *queue);
243 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
244 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
245 static int ena_link_update(struct rte_eth_dev *dev,
246 int wait_to_complete);
247 static int ena_create_io_queue(struct ena_ring *ring);
248 static void ena_queue_stop(struct ena_ring *ring);
249 static void ena_queue_stop_all(struct rte_eth_dev *dev,
250 enum ena_ring_type ring_type);
251 static int ena_queue_start(struct ena_ring *ring);
252 static int ena_queue_start_all(struct rte_eth_dev *dev,
253 enum ena_ring_type ring_type);
254 static void ena_stats_restart(struct rte_eth_dev *dev);
255 static void ena_infos_get(struct rte_eth_dev *dev,
256 struct rte_eth_dev_info *dev_info);
257 static int ena_rss_reta_update(struct rte_eth_dev *dev,
258 struct rte_eth_rss_reta_entry64 *reta_conf,
260 static int ena_rss_reta_query(struct rte_eth_dev *dev,
261 struct rte_eth_rss_reta_entry64 *reta_conf,
263 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
264 static void ena_interrupt_handler_rte(void *cb_arg);
265 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
266 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
267 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
269 static const struct eth_dev_ops ena_dev_ops = {
270 .dev_configure = ena_dev_configure,
271 .dev_infos_get = ena_infos_get,
272 .rx_queue_setup = ena_rx_queue_setup,
273 .tx_queue_setup = ena_tx_queue_setup,
274 .dev_start = ena_start,
275 .dev_stop = ena_stop,
276 .link_update = ena_link_update,
277 .stats_get = ena_stats_get,
278 .mtu_set = ena_mtu_set,
279 .rx_queue_release = ena_rx_queue_release,
280 .tx_queue_release = ena_tx_queue_release,
281 .dev_close = ena_close,
282 .dev_reset = ena_dev_reset,
283 .reta_update = ena_rss_reta_update,
284 .reta_query = ena_rss_reta_query,
287 #define NUMA_NO_NODE SOCKET_ID_ANY
289 static inline int ena_cpu_to_node(int cpu)
291 struct rte_config *config = rte_eal_get_configuration();
292 struct rte_fbarray *arr = &config->mem_config->memzones;
293 const struct rte_memzone *mz;
295 if (unlikely(cpu >= RTE_MAX_MEMZONE))
298 mz = rte_fbarray_get(arr, cpu);
300 return mz->socket_id;
303 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
304 struct ena_com_rx_ctx *ena_rx_ctx)
306 uint64_t ol_flags = 0;
307 uint32_t packet_type = 0;
309 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
310 packet_type |= RTE_PTYPE_L4_TCP;
311 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
312 packet_type |= RTE_PTYPE_L4_UDP;
314 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
315 packet_type |= RTE_PTYPE_L3_IPV4;
316 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
317 packet_type |= RTE_PTYPE_L3_IPV6;
319 if (unlikely(ena_rx_ctx->l4_csum_err))
320 ol_flags |= PKT_RX_L4_CKSUM_BAD;
321 if (unlikely(ena_rx_ctx->l3_csum_err))
322 ol_flags |= PKT_RX_IP_CKSUM_BAD;
324 mbuf->ol_flags = ol_flags;
325 mbuf->packet_type = packet_type;
328 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
329 struct ena_com_tx_ctx *ena_tx_ctx,
330 uint64_t queue_offloads)
332 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
334 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
335 (queue_offloads & QUEUE_OFFLOADS)) {
336 /* check if TSO is required */
337 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
338 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
339 ena_tx_ctx->tso_enable = true;
341 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
344 /* check if L3 checksum is needed */
345 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
346 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
347 ena_tx_ctx->l3_csum_enable = true;
349 if (mbuf->ol_flags & PKT_TX_IPV6) {
350 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
352 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
354 /* set don't fragment (DF) flag */
355 if (mbuf->packet_type &
356 (RTE_PTYPE_L4_NONFRAG
357 | RTE_PTYPE_INNER_L4_NONFRAG))
358 ena_tx_ctx->df = true;
361 /* check if L4 checksum is needed */
362 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
363 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
364 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
365 ena_tx_ctx->l4_csum_enable = true;
366 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
367 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
368 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
369 ena_tx_ctx->l4_csum_enable = true;
371 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
372 ena_tx_ctx->l4_csum_enable = false;
375 ena_meta->mss = mbuf->tso_segsz;
376 ena_meta->l3_hdr_len = mbuf->l3_len;
377 ena_meta->l3_hdr_offset = mbuf->l2_len;
379 ena_tx_ctx->meta_valid = true;
381 ena_tx_ctx->meta_valid = false;
385 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
387 if (likely(req_id < rx_ring->ring_size))
390 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
392 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
393 rx_ring->adapter->trigger_reset = true;
394 ++rx_ring->rx_stats.bad_req_id;
399 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
401 struct ena_tx_buffer *tx_info = NULL;
403 if (likely(req_id < tx_ring->ring_size)) {
404 tx_info = &tx_ring->tx_buffer_info[req_id];
405 if (likely(tx_info->mbuf))
410 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
412 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
414 /* Trigger device reset */
415 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
416 tx_ring->adapter->trigger_reset = true;
420 static void ena_config_host_info(struct ena_com_dev *ena_dev)
422 struct ena_admin_host_info *host_info;
425 /* Allocate only the host info */
426 rc = ena_com_allocate_host_info(ena_dev);
428 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
432 host_info = ena_dev->host_attr.host_info;
434 host_info->os_type = ENA_ADMIN_OS_DPDK;
435 host_info->kernel_ver = RTE_VERSION;
436 snprintf((char *)host_info->kernel_ver_str,
437 sizeof(host_info->kernel_ver_str),
438 "%s", rte_version());
439 host_info->os_dist = RTE_VERSION;
440 snprintf((char *)host_info->os_dist_str,
441 sizeof(host_info->os_dist_str),
442 "%s", rte_version());
443 host_info->driver_version =
444 (DRV_MODULE_VER_MAJOR) |
445 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
446 (DRV_MODULE_VER_SUBMINOR <<
447 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
448 host_info->num_cpus = rte_lcore_count();
450 rc = ena_com_set_host_attributes(ena_dev);
452 if (rc == -ENA_COM_UNSUPPORTED)
453 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
455 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
463 ena_com_delete_host_info(ena_dev);
467 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
469 if (sset != ETH_SS_STATS)
472 /* Workaround for clang:
473 * touch internal structures to prevent
476 ENA_TOUCH(ena_stats_global_strings);
477 ENA_TOUCH(ena_stats_tx_strings);
478 ENA_TOUCH(ena_stats_rx_strings);
479 ENA_TOUCH(ena_stats_ena_com_strings);
481 return dev->data->nb_tx_queues *
482 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
483 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
486 static void ena_config_debug_area(struct ena_adapter *adapter)
491 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
493 RTE_LOG(ERR, PMD, "SS count is negative\n");
497 /* allocate 32 bytes for each string and 64bit for the value */
498 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
500 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
502 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
506 rc = ena_com_set_host_attributes(&adapter->ena_dev);
508 if (rc == -ENA_COM_UNSUPPORTED)
509 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
511 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
518 ena_com_delete_debug_area(&adapter->ena_dev);
521 static void ena_close(struct rte_eth_dev *dev)
523 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
524 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
525 struct ena_adapter *adapter =
526 (struct ena_adapter *)(dev->data->dev_private);
528 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
530 adapter->state = ENA_ADAPTER_STATE_CLOSED;
532 ena_rx_queue_release_all(dev);
533 ena_tx_queue_release_all(dev);
535 rte_free(adapter->drv_stats);
536 adapter->drv_stats = NULL;
538 rte_intr_disable(intr_handle);
539 rte_intr_callback_unregister(intr_handle,
540 ena_interrupt_handler_rte,
544 * MAC is not allocated dynamically. Setting NULL should prevent from
545 * release of the resource in the rte_eth_dev_release_port().
547 dev->data->mac_addrs = NULL;
551 ena_dev_reset(struct rte_eth_dev *dev)
555 ena_destroy_device(dev);
556 rc = eth_ena_dev_init(dev);
558 PMD_INIT_LOG(CRIT, "Cannot initialize device");
563 static int ena_rss_reta_update(struct rte_eth_dev *dev,
564 struct rte_eth_rss_reta_entry64 *reta_conf,
567 struct ena_adapter *adapter =
568 (struct ena_adapter *)(dev->data->dev_private);
569 struct ena_com_dev *ena_dev = &adapter->ena_dev;
575 if ((reta_size == 0) || (reta_conf == NULL))
578 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
579 RTE_LOG(WARNING, PMD,
580 "indirection table %d is bigger than supported (%d)\n",
581 reta_size, ENA_RX_RSS_TABLE_SIZE);
585 for (i = 0 ; i < reta_size ; i++) {
586 /* each reta_conf is for 64 entries.
587 * to support 128 we use 2 conf of 64
589 conf_idx = i / RTE_RETA_GROUP_SIZE;
590 idx = i % RTE_RETA_GROUP_SIZE;
591 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
593 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
595 rc = ena_com_indirect_table_fill_entry(ena_dev,
598 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
600 "Cannot fill indirect table\n");
606 rc = ena_com_indirect_table_set(ena_dev);
607 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
608 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
612 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
613 __func__, reta_size, adapter->rte_dev->data->port_id);
618 /* Query redirection table. */
619 static int ena_rss_reta_query(struct rte_eth_dev *dev,
620 struct rte_eth_rss_reta_entry64 *reta_conf,
623 struct ena_adapter *adapter =
624 (struct ena_adapter *)(dev->data->dev_private);
625 struct ena_com_dev *ena_dev = &adapter->ena_dev;
628 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
632 if (reta_size == 0 || reta_conf == NULL ||
633 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
636 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
637 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
638 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
642 for (i = 0 ; i < reta_size ; i++) {
643 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
644 reta_idx = i % RTE_RETA_GROUP_SIZE;
645 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
646 reta_conf[reta_conf_idx].reta[reta_idx] =
647 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
653 static int ena_rss_init_default(struct ena_adapter *adapter)
655 struct ena_com_dev *ena_dev = &adapter->ena_dev;
656 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
660 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
662 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
666 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
667 val = i % nb_rx_queues;
668 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
669 ENA_IO_RXQ_IDX(val));
670 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
671 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
676 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
677 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
678 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
679 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
683 rc = ena_com_set_default_hash_ctrl(ena_dev);
684 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
685 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
689 rc = ena_com_indirect_table_set(ena_dev);
690 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
691 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
694 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
695 adapter->rte_dev->data->port_id);
700 ena_com_rss_destroy(ena_dev);
706 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
708 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
709 int nb_queues = dev->data->nb_rx_queues;
712 for (i = 0; i < nb_queues; i++)
713 ena_rx_queue_release(queues[i]);
716 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
718 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
719 int nb_queues = dev->data->nb_tx_queues;
722 for (i = 0; i < nb_queues; i++)
723 ena_tx_queue_release(queues[i]);
726 static void ena_rx_queue_release(void *queue)
728 struct ena_ring *ring = (struct ena_ring *)queue;
730 /* Free ring resources */
731 if (ring->rx_buffer_info)
732 rte_free(ring->rx_buffer_info);
733 ring->rx_buffer_info = NULL;
735 if (ring->rx_refill_buffer)
736 rte_free(ring->rx_refill_buffer);
737 ring->rx_refill_buffer = NULL;
739 if (ring->empty_rx_reqs)
740 rte_free(ring->empty_rx_reqs);
741 ring->empty_rx_reqs = NULL;
743 ring->configured = 0;
745 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
746 ring->port_id, ring->id);
749 static void ena_tx_queue_release(void *queue)
751 struct ena_ring *ring = (struct ena_ring *)queue;
753 /* Free ring resources */
754 if (ring->push_buf_intermediate_buf)
755 rte_free(ring->push_buf_intermediate_buf);
757 if (ring->tx_buffer_info)
758 rte_free(ring->tx_buffer_info);
760 if (ring->empty_tx_reqs)
761 rte_free(ring->empty_tx_reqs);
763 ring->empty_tx_reqs = NULL;
764 ring->tx_buffer_info = NULL;
765 ring->push_buf_intermediate_buf = NULL;
767 ring->configured = 0;
769 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
770 ring->port_id, ring->id);
773 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
777 for (i = 0; i < ring->ring_size; ++i)
778 if (ring->rx_buffer_info[i]) {
779 rte_mbuf_raw_free(ring->rx_buffer_info[i]);
780 ring->rx_buffer_info[i] = NULL;
784 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
788 for (i = 0; i < ring->ring_size; ++i) {
789 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
792 rte_pktmbuf_free(tx_buf->mbuf);
796 static int ena_link_update(struct rte_eth_dev *dev,
797 __rte_unused int wait_to_complete)
799 struct rte_eth_link *link = &dev->data->dev_link;
800 struct ena_adapter *adapter;
802 adapter = (struct ena_adapter *)(dev->data->dev_private);
804 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
805 link->link_speed = ETH_SPEED_NUM_NONE;
806 link->link_duplex = ETH_LINK_FULL_DUPLEX;
811 static int ena_queue_start_all(struct rte_eth_dev *dev,
812 enum ena_ring_type ring_type)
814 struct ena_adapter *adapter =
815 (struct ena_adapter *)(dev->data->dev_private);
816 struct ena_ring *queues = NULL;
821 if (ring_type == ENA_RING_TYPE_RX) {
822 queues = adapter->rx_ring;
823 nb_queues = dev->data->nb_rx_queues;
825 queues = adapter->tx_ring;
826 nb_queues = dev->data->nb_tx_queues;
828 for (i = 0; i < nb_queues; i++) {
829 if (queues[i].configured) {
830 if (ring_type == ENA_RING_TYPE_RX) {
832 dev->data->rx_queues[i] == &queues[i],
833 "Inconsistent state of rx queues\n");
836 dev->data->tx_queues[i] == &queues[i],
837 "Inconsistent state of tx queues\n");
840 rc = ena_queue_start(&queues[i]);
844 "failed to start queue %d type(%d)",
855 if (queues[i].configured)
856 ena_queue_stop(&queues[i]);
861 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
863 uint32_t max_frame_len = adapter->max_mtu;
865 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
866 DEV_RX_OFFLOAD_JUMBO_FRAME)
868 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
870 return max_frame_len;
873 static int ena_check_valid_conf(struct ena_adapter *adapter)
875 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
877 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
878 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
879 "max mtu: %d, min mtu: %d",
880 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
881 return ENA_COM_UNSUPPORTED;
888 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
890 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
891 struct ena_com_dev *ena_dev = ctx->ena_dev;
892 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
893 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
895 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
896 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
897 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
898 rx_queue_size = RTE_MIN(rx_queue_size,
899 max_queue_ext->max_rx_cq_depth);
900 rx_queue_size = RTE_MIN(rx_queue_size,
901 max_queue_ext->max_rx_sq_depth);
902 tx_queue_size = RTE_MIN(tx_queue_size,
903 max_queue_ext->max_tx_cq_depth);
905 if (ena_dev->tx_mem_queue_type ==
906 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
907 tx_queue_size = RTE_MIN(tx_queue_size,
910 tx_queue_size = RTE_MIN(tx_queue_size,
911 max_queue_ext->max_tx_sq_depth);
914 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
915 max_queue_ext->max_per_packet_rx_descs);
916 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
917 max_queue_ext->max_per_packet_tx_descs);
919 struct ena_admin_queue_feature_desc *max_queues =
920 &ctx->get_feat_ctx->max_queues;
921 rx_queue_size = RTE_MIN(rx_queue_size,
922 max_queues->max_cq_depth);
923 rx_queue_size = RTE_MIN(rx_queue_size,
924 max_queues->max_sq_depth);
925 tx_queue_size = RTE_MIN(tx_queue_size,
926 max_queues->max_cq_depth);
928 if (ena_dev->tx_mem_queue_type ==
929 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
930 tx_queue_size = RTE_MIN(tx_queue_size,
933 tx_queue_size = RTE_MIN(tx_queue_size,
934 max_queues->max_sq_depth);
937 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
938 max_queues->max_packet_tx_descs);
939 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
940 max_queues->max_packet_rx_descs);
943 /* Round down to the nearest power of 2 */
944 rx_queue_size = rte_align32prevpow2(rx_queue_size);
945 tx_queue_size = rte_align32prevpow2(tx_queue_size);
947 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
948 PMD_INIT_LOG(ERR, "Invalid queue size");
952 ctx->rx_queue_size = rx_queue_size;
953 ctx->tx_queue_size = tx_queue_size;
958 static void ena_stats_restart(struct rte_eth_dev *dev)
960 struct ena_adapter *adapter =
961 (struct ena_adapter *)(dev->data->dev_private);
963 rte_atomic64_init(&adapter->drv_stats->ierrors);
964 rte_atomic64_init(&adapter->drv_stats->oerrors);
965 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
968 static int ena_stats_get(struct rte_eth_dev *dev,
969 struct rte_eth_stats *stats)
971 struct ena_admin_basic_stats ena_stats;
972 struct ena_adapter *adapter =
973 (struct ena_adapter *)(dev->data->dev_private);
974 struct ena_com_dev *ena_dev = &adapter->ena_dev;
979 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
982 memset(&ena_stats, 0, sizeof(ena_stats));
983 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
985 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n");
989 /* Set of basic statistics from ENA */
990 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
991 ena_stats.rx_pkts_low);
992 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
993 ena_stats.tx_pkts_low);
994 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
995 ena_stats.rx_bytes_low);
996 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
997 ena_stats.tx_bytes_low);
998 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
999 ena_stats.rx_drops_low);
1001 /* Driver related stats */
1002 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1003 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1004 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1006 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1007 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1008 for (i = 0; i < max_rings_stats; ++i) {
1009 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1011 stats->q_ibytes[i] = rx_stats->bytes;
1012 stats->q_ipackets[i] = rx_stats->cnt;
1013 stats->q_errors[i] = rx_stats->bad_desc_num +
1014 rx_stats->bad_req_id;
1017 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1018 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1019 for (i = 0; i < max_rings_stats; ++i) {
1020 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1022 stats->q_obytes[i] = tx_stats->bytes;
1023 stats->q_opackets[i] = tx_stats->cnt;
1029 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1031 struct ena_adapter *adapter;
1032 struct ena_com_dev *ena_dev;
1035 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1036 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1037 adapter = (struct ena_adapter *)(dev->data->dev_private);
1039 ena_dev = &adapter->ena_dev;
1040 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1042 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1044 "Invalid MTU setting. new_mtu: %d "
1045 "max mtu: %d min mtu: %d\n",
1046 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1050 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1052 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1054 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1059 static int ena_start(struct rte_eth_dev *dev)
1061 struct ena_adapter *adapter =
1062 (struct ena_adapter *)(dev->data->dev_private);
1066 rc = ena_check_valid_conf(adapter);
1070 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1074 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1078 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1079 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1080 rc = ena_rss_init_default(adapter);
1085 ena_stats_restart(dev);
1087 adapter->timestamp_wd = rte_get_timer_cycles();
1088 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1090 ticks = rte_get_timer_hz();
1091 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1092 ena_timer_wd_callback, adapter);
1094 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1099 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1101 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1105 static void ena_stop(struct rte_eth_dev *dev)
1107 struct ena_adapter *adapter =
1108 (struct ena_adapter *)(dev->data->dev_private);
1109 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1112 rte_timer_stop_sync(&adapter->timer_wd);
1113 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1114 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1116 if (adapter->trigger_reset) {
1117 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1119 RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc);
1122 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1125 static int ena_create_io_queue(struct ena_ring *ring)
1127 struct ena_adapter *adapter;
1128 struct ena_com_dev *ena_dev;
1129 struct ena_com_create_io_ctx ctx =
1130 /* policy set to _HOST just to satisfy icc compiler */
1131 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1137 adapter = ring->adapter;
1138 ena_dev = &adapter->ena_dev;
1140 if (ring->type == ENA_RING_TYPE_TX) {
1141 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1142 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1143 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1144 ctx.queue_size = adapter->tx_ring_size;
1145 for (i = 0; i < ring->ring_size; i++)
1146 ring->empty_tx_reqs[i] = i;
1148 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1149 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1150 ctx.queue_size = adapter->rx_ring_size;
1151 for (i = 0; i < ring->ring_size; i++)
1152 ring->empty_rx_reqs[i] = i;
1155 ctx.msix_vector = -1; /* interrupts not used */
1156 ctx.numa_node = ena_cpu_to_node(ring->id);
1158 rc = ena_com_create_io_queue(ena_dev, &ctx);
1161 "failed to create io queue #%d (qid:%d) rc: %d\n",
1162 ring->id, ena_qid, rc);
1166 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1167 &ring->ena_com_io_sq,
1168 &ring->ena_com_io_cq);
1171 "Failed to get io queue handlers. queue num %d rc: %d\n",
1173 ena_com_destroy_io_queue(ena_dev, ena_qid);
1177 if (ring->type == ENA_RING_TYPE_TX)
1178 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1183 static void ena_queue_stop(struct ena_ring *ring)
1185 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1187 if (ring->type == ENA_RING_TYPE_RX) {
1188 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1189 ena_rx_queue_release_bufs(ring);
1191 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1192 ena_tx_queue_release_bufs(ring);
1196 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1197 enum ena_ring_type ring_type)
1199 struct ena_adapter *adapter =
1200 (struct ena_adapter *)(dev->data->dev_private);
1201 struct ena_ring *queues = NULL;
1202 uint16_t nb_queues, i;
1204 if (ring_type == ENA_RING_TYPE_RX) {
1205 queues = adapter->rx_ring;
1206 nb_queues = dev->data->nb_rx_queues;
1208 queues = adapter->tx_ring;
1209 nb_queues = dev->data->nb_tx_queues;
1212 for (i = 0; i < nb_queues; ++i)
1213 if (queues[i].configured)
1214 ena_queue_stop(&queues[i]);
1217 static int ena_queue_start(struct ena_ring *ring)
1221 ena_assert_msg(ring->configured == 1,
1222 "Trying to start unconfigured queue\n");
1224 rc = ena_create_io_queue(ring);
1226 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1230 ring->next_to_clean = 0;
1231 ring->next_to_use = 0;
1233 if (ring->type == ENA_RING_TYPE_TX)
1236 bufs_num = ring->ring_size - 1;
1237 rc = ena_populate_rx_queue(ring, bufs_num);
1238 if (rc != bufs_num) {
1239 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1240 ENA_IO_RXQ_IDX(ring->id));
1241 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1242 return ENA_COM_FAULT;
1248 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1251 __rte_unused unsigned int socket_id,
1252 const struct rte_eth_txconf *tx_conf)
1254 struct ena_ring *txq = NULL;
1255 struct ena_adapter *adapter =
1256 (struct ena_adapter *)(dev->data->dev_private);
1259 txq = &adapter->tx_ring[queue_idx];
1261 if (txq->configured) {
1263 "API violation. Queue %d is already configured\n",
1265 return ENA_COM_FAULT;
1268 if (!rte_is_power_of_2(nb_desc)) {
1270 "Unsupported size of TX queue: %d is not a power of 2.\n",
1275 if (nb_desc > adapter->tx_ring_size) {
1277 "Unsupported size of TX queue (max size: %d)\n",
1278 adapter->tx_ring_size);
1282 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1283 nb_desc = adapter->tx_ring_size;
1285 txq->port_id = dev->data->port_id;
1286 txq->next_to_clean = 0;
1287 txq->next_to_use = 0;
1288 txq->ring_size = nb_desc;
1290 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1291 sizeof(struct ena_tx_buffer) *
1293 RTE_CACHE_LINE_SIZE);
1294 if (!txq->tx_buffer_info) {
1295 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1299 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1300 sizeof(u16) * txq->ring_size,
1301 RTE_CACHE_LINE_SIZE);
1302 if (!txq->empty_tx_reqs) {
1303 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1304 rte_free(txq->tx_buffer_info);
1308 txq->push_buf_intermediate_buf =
1309 rte_zmalloc("txq->push_buf_intermediate_buf",
1310 txq->tx_max_header_size,
1311 RTE_CACHE_LINE_SIZE);
1312 if (!txq->push_buf_intermediate_buf) {
1313 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1314 rte_free(txq->tx_buffer_info);
1315 rte_free(txq->empty_tx_reqs);
1319 for (i = 0; i < txq->ring_size; i++)
1320 txq->empty_tx_reqs[i] = i;
1322 if (tx_conf != NULL) {
1324 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1327 /* Store pointer to this queue in upper layer */
1328 txq->configured = 1;
1329 dev->data->tx_queues[queue_idx] = txq;
1334 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1337 __rte_unused unsigned int socket_id,
1338 __rte_unused const struct rte_eth_rxconf *rx_conf,
1339 struct rte_mempool *mp)
1341 struct ena_adapter *adapter =
1342 (struct ena_adapter *)(dev->data->dev_private);
1343 struct ena_ring *rxq = NULL;
1346 rxq = &adapter->rx_ring[queue_idx];
1347 if (rxq->configured) {
1349 "API violation. Queue %d is already configured\n",
1351 return ENA_COM_FAULT;
1354 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1355 nb_desc = adapter->rx_ring_size;
1357 if (!rte_is_power_of_2(nb_desc)) {
1359 "Unsupported size of RX queue: %d is not a power of 2.\n",
1364 if (nb_desc > adapter->rx_ring_size) {
1366 "Unsupported size of RX queue (max size: %d)\n",
1367 adapter->rx_ring_size);
1371 rxq->port_id = dev->data->port_id;
1372 rxq->next_to_clean = 0;
1373 rxq->next_to_use = 0;
1374 rxq->ring_size = nb_desc;
1377 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1378 sizeof(struct rte_mbuf *) * nb_desc,
1379 RTE_CACHE_LINE_SIZE);
1380 if (!rxq->rx_buffer_info) {
1381 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1385 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1386 sizeof(struct rte_mbuf *) * nb_desc,
1387 RTE_CACHE_LINE_SIZE);
1389 if (!rxq->rx_refill_buffer) {
1390 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1391 rte_free(rxq->rx_buffer_info);
1392 rxq->rx_buffer_info = NULL;
1396 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1397 sizeof(uint16_t) * nb_desc,
1398 RTE_CACHE_LINE_SIZE);
1399 if (!rxq->empty_rx_reqs) {
1400 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1401 rte_free(rxq->rx_buffer_info);
1402 rxq->rx_buffer_info = NULL;
1403 rte_free(rxq->rx_refill_buffer);
1404 rxq->rx_refill_buffer = NULL;
1408 for (i = 0; i < nb_desc; i++)
1409 rxq->empty_rx_reqs[i] = i;
1411 /* Store pointer to this queue in upper layer */
1412 rxq->configured = 1;
1413 dev->data->rx_queues[queue_idx] = rxq;
1418 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1422 uint16_t ring_size = rxq->ring_size;
1423 uint16_t ring_mask = ring_size - 1;
1424 uint16_t next_to_use = rxq->next_to_use;
1425 uint16_t in_use, req_id;
1426 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1428 if (unlikely(!count))
1431 in_use = rxq->next_to_use - rxq->next_to_clean;
1432 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1434 /* get resources for incoming packets */
1435 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1436 if (unlikely(rc < 0)) {
1437 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1438 ++rxq->rx_stats.page_alloc_fail;
1439 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1443 for (i = 0; i < count; i++) {
1444 uint16_t next_to_use_masked = next_to_use & ring_mask;
1445 struct rte_mbuf *mbuf = mbufs[i];
1446 struct ena_com_buf ebuf;
1448 if (likely((i + 4) < count))
1449 rte_prefetch0(mbufs[i + 4]);
1451 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1452 rc = validate_rx_req_id(rxq, req_id);
1453 if (unlikely(rc < 0))
1455 rxq->rx_buffer_info[req_id] = mbuf;
1457 /* prepare physical address for DMA transaction */
1458 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1459 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1460 /* pass resource to device */
1461 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1464 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1465 rxq->rx_buffer_info[req_id] = NULL;
1471 if (unlikely(i < count)) {
1472 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1473 "buffers (from %d)\n", rxq->id, i, count);
1474 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1478 /* When we submitted free recources to device... */
1479 if (likely(i > 0)) {
1480 /* ...let HW know that it can fill buffers with data
1482 * Add memory barrier to make sure the desc were written before
1486 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1488 rxq->next_to_use = next_to_use;
1494 static int ena_device_init(struct ena_com_dev *ena_dev,
1495 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1498 uint32_t aenq_groups;
1500 bool readless_supported;
1502 /* Initialize mmio registers */
1503 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1505 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1509 /* The PCIe configuration space revision id indicate if mmio reg
1512 readless_supported =
1513 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1514 & ENA_MMIO_DISABLE_REG_READ);
1515 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1518 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1520 RTE_LOG(ERR, PMD, "cannot reset device\n");
1521 goto err_mmio_read_less;
1524 /* check FW version */
1525 rc = ena_com_validate_version(ena_dev);
1527 RTE_LOG(ERR, PMD, "device version is too low\n");
1528 goto err_mmio_read_less;
1531 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1533 /* ENA device administration layer init */
1534 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1537 "cannot initialize ena admin queue with device\n");
1538 goto err_mmio_read_less;
1541 /* To enable the msix interrupts the driver needs to know the number
1542 * of queues. So the driver uses polling mode to retrieve this
1545 ena_com_set_admin_polling_mode(ena_dev, true);
1547 ena_config_host_info(ena_dev);
1549 /* Get Device Attributes and features */
1550 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1553 "cannot get attribute for ena device rc= %d\n", rc);
1554 goto err_admin_init;
1557 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1558 BIT(ENA_ADMIN_NOTIFICATION) |
1559 BIT(ENA_ADMIN_KEEP_ALIVE) |
1560 BIT(ENA_ADMIN_FATAL_ERROR) |
1561 BIT(ENA_ADMIN_WARNING);
1563 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1564 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1566 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1567 goto err_admin_init;
1570 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1575 ena_com_admin_destroy(ena_dev);
1578 ena_com_mmio_reg_read_request_destroy(ena_dev);
1583 static void ena_interrupt_handler_rte(void *cb_arg)
1585 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1586 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1588 ena_com_admin_q_comp_intr_handler(ena_dev);
1589 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1590 ena_com_aenq_intr_handler(ena_dev, adapter);
1593 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1595 if (!adapter->wd_state)
1598 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1601 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1602 adapter->keep_alive_timeout)) {
1603 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1604 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1605 adapter->trigger_reset = true;
1609 /* Check if admin queue is enabled */
1610 static void check_for_admin_com_state(struct ena_adapter *adapter)
1612 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1613 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1614 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1615 adapter->trigger_reset = true;
1619 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1622 struct ena_adapter *adapter = (struct ena_adapter *)arg;
1623 struct rte_eth_dev *dev = adapter->rte_dev;
1625 check_for_missing_keep_alive(adapter);
1626 check_for_admin_com_state(adapter);
1628 if (unlikely(adapter->trigger_reset)) {
1629 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1630 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1636 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1638 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1639 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1640 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1641 llq_config->llq_num_decs_before_header =
1642 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1643 llq_config->llq_ring_entry_size_value = 128;
1647 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1648 struct ena_com_dev *ena_dev,
1649 struct ena_admin_feature_llq_desc *llq,
1650 struct ena_llq_configurations *llq_default_configurations)
1653 u32 llq_feature_mask;
1655 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1656 if (!(ena_dev->supported_features & llq_feature_mask)) {
1658 "LLQ is not supported. Fallback to host mode policy.\n");
1659 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1663 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1665 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1666 "Fallback to host mode policy.");
1667 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1671 /* Nothing to config, exit */
1672 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1675 if (!adapter->dev_mem_base) {
1676 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1677 "Fallback to host mode policy.\n.");
1678 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1682 ena_dev->mem_bar = adapter->dev_mem_base;
1687 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1688 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1690 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1692 /* Regular queues capabilities */
1693 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1694 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1695 &get_feat_ctx->max_queue_ext.max_queue_ext;
1696 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1697 max_queue_ext->max_rx_cq_num);
1698 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1699 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1701 struct ena_admin_queue_feature_desc *max_queues =
1702 &get_feat_ctx->max_queues;
1703 io_tx_sq_num = max_queues->max_sq_num;
1704 io_tx_cq_num = max_queues->max_cq_num;
1705 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1708 /* In case of LLQ use the llq number in the get feature cmd */
1709 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1710 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1712 io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
1713 io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
1714 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1715 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1717 if (unlikely(io_queue_num == 0)) {
1718 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1722 return io_queue_num;
1725 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1727 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1728 struct rte_pci_device *pci_dev;
1729 struct rte_intr_handle *intr_handle;
1730 struct ena_adapter *adapter =
1731 (struct ena_adapter *)(eth_dev->data->dev_private);
1732 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1733 struct ena_com_dev_get_features_ctx get_feat_ctx;
1734 struct ena_llq_configurations llq_config;
1735 const char *queue_type_str;
1738 static int adapters_found;
1741 memset(adapter, 0, sizeof(struct ena_adapter));
1742 ena_dev = &adapter->ena_dev;
1744 eth_dev->dev_ops = &ena_dev_ops;
1745 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1746 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1747 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1748 adapter->rte_eth_dev_data = eth_dev->data;
1749 adapter->rte_dev = eth_dev;
1751 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1754 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1755 adapter->pdev = pci_dev;
1757 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1758 pci_dev->addr.domain,
1760 pci_dev->addr.devid,
1761 pci_dev->addr.function);
1763 intr_handle = &pci_dev->intr_handle;
1765 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1766 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1768 if (!adapter->regs) {
1769 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1774 ena_dev->reg_bar = adapter->regs;
1775 ena_dev->dmadev = adapter->pdev;
1777 adapter->id_number = adapters_found;
1779 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1780 adapter->id_number);
1782 /* device specific initialization routine */
1783 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1785 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1788 adapter->wd_state = wd_state;
1790 set_default_llq_configurations(&llq_config);
1791 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1792 &get_feat_ctx.llq, &llq_config);
1794 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1798 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1799 queue_type_str = "Regular";
1801 queue_type_str = "Low latency";
1802 RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1804 calc_queue_ctx.ena_dev = ena_dev;
1805 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1806 adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1809 rc = ena_calc_queue_size(&calc_queue_ctx);
1810 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1812 goto err_device_destroy;
1815 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1816 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1818 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1819 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1821 /* prepare ring structures */
1822 ena_init_rings(adapter);
1824 ena_config_debug_area(adapter);
1826 /* Set max MTU for this device */
1827 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1829 /* set device support for TSO */
1830 adapter->tso4_supported = get_feat_ctx.offload.tx &
1831 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1833 /* Copy MAC address and point DPDK to it */
1834 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1835 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1836 (struct ether_addr *)adapter->mac_addr);
1839 * Pass the information to the rte_eth_dev_close() that it should also
1840 * release the private port resources.
1842 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1844 adapter->drv_stats = rte_zmalloc("adapter stats",
1845 sizeof(*adapter->drv_stats),
1846 RTE_CACHE_LINE_SIZE);
1847 if (!adapter->drv_stats) {
1848 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1850 goto err_delete_debug_area;
1853 rte_intr_callback_register(intr_handle,
1854 ena_interrupt_handler_rte,
1856 rte_intr_enable(intr_handle);
1857 ena_com_set_admin_polling_mode(ena_dev, false);
1858 ena_com_admin_aenq_enable(ena_dev);
1860 if (adapters_found == 0)
1861 rte_timer_subsystem_init();
1862 rte_timer_init(&adapter->timer_wd);
1865 adapter->state = ENA_ADAPTER_STATE_INIT;
1869 err_delete_debug_area:
1870 ena_com_delete_debug_area(ena_dev);
1873 ena_com_delete_host_info(ena_dev);
1874 ena_com_admin_destroy(ena_dev);
1880 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1882 struct ena_adapter *adapter =
1883 (struct ena_adapter *)(eth_dev->data->dev_private);
1884 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1886 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1889 ena_com_set_admin_running_state(ena_dev, false);
1891 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1894 ena_com_delete_debug_area(ena_dev);
1895 ena_com_delete_host_info(ena_dev);
1897 ena_com_abort_admin_commands(ena_dev);
1898 ena_com_wait_for_abort_completion(ena_dev);
1899 ena_com_admin_destroy(ena_dev);
1900 ena_com_mmio_reg_read_request_destroy(ena_dev);
1902 adapter->state = ENA_ADAPTER_STATE_FREE;
1905 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1907 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1910 ena_destroy_device(eth_dev);
1912 eth_dev->dev_ops = NULL;
1913 eth_dev->rx_pkt_burst = NULL;
1914 eth_dev->tx_pkt_burst = NULL;
1915 eth_dev->tx_pkt_prepare = NULL;
1920 static int ena_dev_configure(struct rte_eth_dev *dev)
1922 struct ena_adapter *adapter =
1923 (struct ena_adapter *)(dev->data->dev_private);
1925 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1927 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1928 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1932 static void ena_init_rings(struct ena_adapter *adapter)
1936 for (i = 0; i < adapter->num_queues; i++) {
1937 struct ena_ring *ring = &adapter->tx_ring[i];
1939 ring->configured = 0;
1940 ring->type = ENA_RING_TYPE_TX;
1941 ring->adapter = adapter;
1943 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1944 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1945 ring->sgl_size = adapter->max_tx_sgl_size;
1948 for (i = 0; i < adapter->num_queues; i++) {
1949 struct ena_ring *ring = &adapter->rx_ring[i];
1951 ring->configured = 0;
1952 ring->type = ENA_RING_TYPE_RX;
1953 ring->adapter = adapter;
1955 ring->sgl_size = adapter->max_rx_sgl_size;
1959 static void ena_infos_get(struct rte_eth_dev *dev,
1960 struct rte_eth_dev_info *dev_info)
1962 struct ena_adapter *adapter;
1963 struct ena_com_dev *ena_dev;
1964 struct ena_com_dev_get_features_ctx feat;
1965 uint64_t rx_feat = 0, tx_feat = 0;
1968 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1969 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1970 adapter = (struct ena_adapter *)(dev->data->dev_private);
1972 ena_dev = &adapter->ena_dev;
1973 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1975 dev_info->speed_capa =
1977 ETH_LINK_SPEED_2_5G |
1979 ETH_LINK_SPEED_10G |
1980 ETH_LINK_SPEED_25G |
1981 ETH_LINK_SPEED_40G |
1982 ETH_LINK_SPEED_50G |
1983 ETH_LINK_SPEED_100G;
1985 /* Get supported features from HW */
1986 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1989 "Cannot get attribute for ena device rc= %d\n", rc);
1993 /* Set Tx & Rx features available for device */
1994 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1995 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1997 if (feat.offload.tx &
1998 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1999 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2000 DEV_TX_OFFLOAD_UDP_CKSUM |
2001 DEV_TX_OFFLOAD_TCP_CKSUM;
2003 if (feat.offload.rx_supported &
2004 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2005 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2006 DEV_RX_OFFLOAD_UDP_CKSUM |
2007 DEV_RX_OFFLOAD_TCP_CKSUM;
2009 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2011 /* Inform framework about available features */
2012 dev_info->rx_offload_capa = rx_feat;
2013 dev_info->rx_queue_offload_capa = rx_feat;
2014 dev_info->tx_offload_capa = tx_feat;
2015 dev_info->tx_queue_offload_capa = tx_feat;
2017 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2020 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2021 dev_info->max_rx_pktlen = adapter->max_mtu;
2022 dev_info->max_mac_addrs = 1;
2024 dev_info->max_rx_queues = adapter->num_queues;
2025 dev_info->max_tx_queues = adapter->num_queues;
2026 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2028 adapter->tx_supported_offloads = tx_feat;
2029 adapter->rx_supported_offloads = rx_feat;
2031 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
2032 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2033 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2034 adapter->max_rx_sgl_size);
2035 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2036 adapter->max_rx_sgl_size);
2038 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2039 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2040 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2041 adapter->max_tx_sgl_size);
2042 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2043 adapter->max_tx_sgl_size);
2046 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2049 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2050 unsigned int ring_size = rx_ring->ring_size;
2051 unsigned int ring_mask = ring_size - 1;
2052 uint16_t next_to_clean = rx_ring->next_to_clean;
2053 uint16_t desc_in_use = 0;
2055 unsigned int recv_idx = 0;
2056 struct rte_mbuf *mbuf = NULL;
2057 struct rte_mbuf *mbuf_head = NULL;
2058 struct rte_mbuf *mbuf_prev = NULL;
2059 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2060 unsigned int completed;
2062 struct ena_com_rx_ctx ena_rx_ctx;
2065 /* Check adapter state */
2066 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2068 "Trying to receive pkts while device is NOT running\n");
2072 desc_in_use = rx_ring->next_to_use - next_to_clean;
2073 if (unlikely(nb_pkts > desc_in_use))
2074 nb_pkts = desc_in_use;
2076 for (completed = 0; completed < nb_pkts; completed++) {
2079 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2080 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2081 ena_rx_ctx.descs = 0;
2082 /* receive packet context */
2083 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2084 rx_ring->ena_com_io_sq,
2087 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2088 rx_ring->adapter->reset_reason =
2089 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2090 rx_ring->adapter->trigger_reset = true;
2094 if (unlikely(ena_rx_ctx.descs == 0))
2097 while (segments < ena_rx_ctx.descs) {
2098 req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2099 rc = validate_rx_req_id(rx_ring, req_id);
2102 rte_mbuf_raw_free(mbuf_head);
2106 mbuf = rx_buff_info[req_id];
2107 rx_buff_info[req_id] = NULL;
2108 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2109 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2112 if (unlikely(segments == 0)) {
2113 mbuf->nb_segs = ena_rx_ctx.descs;
2114 mbuf->port = rx_ring->port_id;
2118 /* for multi-segment pkts create mbuf chain */
2119 mbuf_prev->next = mbuf;
2121 mbuf_head->pkt_len += mbuf->data_len;
2124 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2132 /* fill mbuf attributes if any */
2133 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2134 mbuf_head->hash.rss = ena_rx_ctx.hash;
2136 /* pass to DPDK application head mbuf */
2137 rx_pkts[recv_idx] = mbuf_head;
2139 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2142 rx_ring->rx_stats.cnt += recv_idx;
2143 rx_ring->next_to_clean = next_to_clean;
2145 desc_in_use = desc_in_use - completed + 1;
2146 /* Burst refill to save doorbells, memory barriers, const interval */
2147 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2148 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2154 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2160 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2161 struct ipv4_hdr *ip_hdr;
2163 uint16_t frag_field;
2165 for (i = 0; i != nb_pkts; i++) {
2167 ol_flags = m->ol_flags;
2169 if (!(ol_flags & PKT_TX_IPV4))
2172 /* If there was not L2 header length specified, assume it is
2173 * length of the ethernet header.
2175 if (unlikely(m->l2_len == 0))
2176 m->l2_len = sizeof(struct ether_hdr);
2178 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2180 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2182 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2183 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2185 /* If IPv4 header has DF flag enabled and TSO support is
2186 * disabled, partial chcecksum should not be calculated.
2188 if (!tx_ring->adapter->tso4_supported)
2192 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2193 (ol_flags & PKT_TX_L4_MASK) ==
2194 PKT_TX_SCTP_CKSUM) {
2195 rte_errno = -ENOTSUP;
2199 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2200 ret = rte_validate_tx_offload(m);
2207 /* In case we are supposed to TSO and have DF not set (DF=0)
2208 * hardware must be provided with partial checksum, otherwise
2209 * it will take care of necessary calculations.
2212 ret = rte_net_intel_cksum_flags_prepare(m,
2213 ol_flags & ~PKT_TX_TCP_SEG);
2223 static void ena_update_hints(struct ena_adapter *adapter,
2224 struct ena_admin_ena_hw_hints *hints)
2226 if (hints->admin_completion_tx_timeout)
2227 adapter->ena_dev.admin_queue.completion_timeout =
2228 hints->admin_completion_tx_timeout * 1000;
2230 if (hints->mmio_read_timeout)
2231 /* convert to usec */
2232 adapter->ena_dev.mmio_read.reg_read_to =
2233 hints->mmio_read_timeout * 1000;
2235 if (hints->driver_watchdog_timeout) {
2236 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2237 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2239 // Convert msecs to ticks
2240 adapter->keep_alive_timeout =
2241 (hints->driver_watchdog_timeout *
2242 rte_get_timer_hz()) / 1000;
2246 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2247 struct rte_mbuf *mbuf)
2249 struct ena_com_dev *ena_dev;
2250 int num_segments, header_len, rc;
2252 ena_dev = &tx_ring->adapter->ena_dev;
2253 num_segments = mbuf->nb_segs;
2254 header_len = mbuf->data_len;
2256 if (likely(num_segments < tx_ring->sgl_size))
2259 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2260 (num_segments == tx_ring->sgl_size) &&
2261 (header_len < tx_ring->tx_max_header_size))
2264 rc = rte_pktmbuf_linearize(mbuf);
2266 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2271 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2274 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2275 uint16_t next_to_use = tx_ring->next_to_use;
2276 uint16_t next_to_clean = tx_ring->next_to_clean;
2277 struct rte_mbuf *mbuf;
2279 unsigned int ring_size = tx_ring->ring_size;
2280 unsigned int ring_mask = ring_size - 1;
2281 struct ena_com_tx_ctx ena_tx_ctx;
2282 struct ena_tx_buffer *tx_info;
2283 struct ena_com_buf *ebuf;
2284 uint16_t rc, req_id, total_tx_descs = 0;
2285 uint16_t sent_idx = 0, empty_tx_reqs;
2286 uint16_t push_len = 0;
2289 uint32_t total_length;
2291 /* Check adapter state */
2292 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2294 "Trying to xmit pkts while device is NOT running\n");
2298 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2299 if (nb_pkts > empty_tx_reqs)
2300 nb_pkts = empty_tx_reqs;
2302 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2303 mbuf = tx_pkts[sent_idx];
2306 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2310 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2311 tx_info = &tx_ring->tx_buffer_info[req_id];
2312 tx_info->mbuf = mbuf;
2313 tx_info->num_of_bufs = 0;
2314 ebuf = tx_info->bufs;
2316 /* Prepare TX context */
2317 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2318 memset(&ena_tx_ctx.ena_meta, 0x0,
2319 sizeof(struct ena_com_tx_meta));
2320 ena_tx_ctx.ena_bufs = ebuf;
2321 ena_tx_ctx.req_id = req_id;
2324 seg_len = mbuf->data_len;
2326 if (tx_ring->tx_mem_queue_type ==
2327 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2328 push_len = RTE_MIN(mbuf->pkt_len,
2329 tx_ring->tx_max_header_size);
2330 ena_tx_ctx.header_len = push_len;
2332 if (likely(push_len <= seg_len)) {
2333 /* If the push header is in the single segment,
2334 * then just point it to the 1st mbuf data.
2336 ena_tx_ctx.push_header =
2337 rte_pktmbuf_mtod(mbuf, uint8_t *);
2339 /* If the push header lays in the several
2340 * segments, copy it to the intermediate buffer.
2342 rte_pktmbuf_read(mbuf, 0, push_len,
2343 tx_ring->push_buf_intermediate_buf);
2344 ena_tx_ctx.push_header =
2345 tx_ring->push_buf_intermediate_buf;
2346 delta = push_len - seg_len;
2348 } /* there's no else as we take advantage of memset zeroing */
2350 /* Set TX offloads flags, if applicable */
2351 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2353 if (unlikely(mbuf->ol_flags &
2354 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2355 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2357 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2359 /* Process first segment taking into
2360 * consideration pushed header
2362 if (seg_len > push_len) {
2363 ebuf->paddr = mbuf->buf_iova +
2366 ebuf->len = seg_len - push_len;
2368 tx_info->num_of_bufs++;
2370 total_length += mbuf->data_len;
2372 while ((mbuf = mbuf->next) != NULL) {
2373 seg_len = mbuf->data_len;
2375 /* Skip mbufs if whole data is pushed as a header */
2376 if (unlikely(delta > seg_len)) {
2381 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2382 ebuf->len = seg_len - delta;
2383 total_length += ebuf->len;
2385 tx_info->num_of_bufs++;
2390 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2392 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2394 RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
2395 " achieved, writing doorbell to send burst\n",
2398 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2401 /* prepare the packet's descriptors to dma engine */
2402 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2403 &ena_tx_ctx, &nb_hw_desc);
2407 tx_info->tx_descs = nb_hw_desc;
2410 tx_ring->tx_stats.cnt += tx_info->num_of_bufs;
2411 tx_ring->tx_stats.bytes += total_length;
2414 /* If there are ready packets to be xmitted... */
2416 /* ...let HW do its best :-) */
2418 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2419 tx_ring->tx_stats.doorbells++;
2420 tx_ring->next_to_use = next_to_use;
2423 /* Clear complete packets */
2424 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2425 rc = validate_tx_req_id(tx_ring, req_id);
2429 /* Get Tx info & store how many descs were processed */
2430 tx_info = &tx_ring->tx_buffer_info[req_id];
2431 total_tx_descs += tx_info->tx_descs;
2433 /* Free whole mbuf chain */
2434 mbuf = tx_info->mbuf;
2435 rte_pktmbuf_free(mbuf);
2436 tx_info->mbuf = NULL;
2438 /* Put back descriptor to the ring for reuse */
2439 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2442 /* If too many descs to clean, leave it for another run */
2443 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2447 if (total_tx_descs > 0) {
2448 /* acknowledge completion of sent packets */
2449 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2450 tx_ring->next_to_clean = next_to_clean;
2456 /*********************************************************************
2458 *********************************************************************/
2459 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2460 struct rte_pci_device *pci_dev)
2462 return rte_eth_dev_pci_generic_probe(pci_dev,
2463 sizeof(struct ena_adapter), eth_ena_dev_init);
2466 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2468 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2471 static struct rte_pci_driver rte_ena_pmd = {
2472 .id_table = pci_id_ena_map,
2473 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2474 RTE_PCI_DRV_WC_ACTIVATE,
2475 .probe = eth_ena_pci_probe,
2476 .remove = eth_ena_pci_remove,
2479 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2480 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2481 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2483 RTE_INIT(ena_init_log)
2485 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2486 if (ena_logtype_init >= 0)
2487 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2488 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2489 if (ena_logtype_driver >= 0)
2490 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2493 /******************************************************************************
2494 ******************************** AENQ Handlers *******************************
2495 *****************************************************************************/
2496 static void ena_update_on_link_change(void *adapter_data,
2497 struct ena_admin_aenq_entry *aenq_e)
2499 struct rte_eth_dev *eth_dev;
2500 struct ena_adapter *adapter;
2501 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2504 adapter = (struct ena_adapter *)adapter_data;
2505 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2506 eth_dev = adapter->rte_dev;
2508 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2509 adapter->link_status = status;
2511 ena_link_update(eth_dev, 0);
2512 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2515 static void ena_notification(void *data,
2516 struct ena_admin_aenq_entry *aenq_e)
2518 struct ena_adapter *adapter = (struct ena_adapter *)data;
2519 struct ena_admin_ena_hw_hints *hints;
2521 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2522 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2523 aenq_e->aenq_common_desc.group,
2524 ENA_ADMIN_NOTIFICATION);
2526 switch (aenq_e->aenq_common_desc.syndrom) {
2527 case ENA_ADMIN_UPDATE_HINTS:
2528 hints = (struct ena_admin_ena_hw_hints *)
2529 (&aenq_e->inline_data_w4);
2530 ena_update_hints(adapter, hints);
2533 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2534 aenq_e->aenq_common_desc.syndrom);
2538 static void ena_keep_alive(void *adapter_data,
2539 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2541 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2543 adapter->timestamp_wd = rte_get_timer_cycles();
2547 * This handler will called for unknown event group or unimplemented handlers
2549 static void unimplemented_aenq_handler(__rte_unused void *data,
2550 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2552 RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2553 "unimplemented handler\n");
2556 static struct ena_aenq_handlers aenq_handlers = {
2558 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2559 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2560 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2562 .unimplemented_handler = unimplemented_aenq_handler