4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 1
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 #define ENA_MIN_RING_DESC 128
90 enum ethtool_stringset {
96 char name[ETH_GSTRING_LEN];
100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
102 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
105 #define ENA_STAT_ENTRY(stat, stat_type) { \
107 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
110 #define ENA_STAT_RX_ENTRY(stat) \
111 ENA_STAT_ENTRY(stat, rx)
113 #define ENA_STAT_TX_ENTRY(stat) \
114 ENA_STAT_ENTRY(stat, tx)
116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
117 ENA_STAT_ENTRY(stat, dev)
119 #define ENA_MAX_RING_SIZE_RX 8192
120 #define ENA_MAX_RING_SIZE_TX 1024
123 * Each rte_memzone should have unique name.
124 * To satisfy it, count number of allocation and add it to name.
126 uint32_t ena_alloc_cnt;
128 static const struct ena_stats ena_stats_global_strings[] = {
129 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
130 ENA_STAT_GLOBAL_ENTRY(io_suspend),
131 ENA_STAT_GLOBAL_ENTRY(io_resume),
132 ENA_STAT_GLOBAL_ENTRY(wd_expired),
133 ENA_STAT_GLOBAL_ENTRY(interface_up),
134 ENA_STAT_GLOBAL_ENTRY(interface_down),
135 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
138 static const struct ena_stats ena_stats_tx_strings[] = {
139 ENA_STAT_TX_ENTRY(cnt),
140 ENA_STAT_TX_ENTRY(bytes),
141 ENA_STAT_TX_ENTRY(queue_stop),
142 ENA_STAT_TX_ENTRY(queue_wakeup),
143 ENA_STAT_TX_ENTRY(dma_mapping_err),
144 ENA_STAT_TX_ENTRY(linearize),
145 ENA_STAT_TX_ENTRY(linearize_failed),
146 ENA_STAT_TX_ENTRY(tx_poll),
147 ENA_STAT_TX_ENTRY(doorbells),
148 ENA_STAT_TX_ENTRY(prepare_ctx_err),
149 ENA_STAT_TX_ENTRY(missing_tx_comp),
150 ENA_STAT_TX_ENTRY(bad_req_id),
153 static const struct ena_stats ena_stats_rx_strings[] = {
154 ENA_STAT_RX_ENTRY(cnt),
155 ENA_STAT_RX_ENTRY(bytes),
156 ENA_STAT_RX_ENTRY(refil_partial),
157 ENA_STAT_RX_ENTRY(bad_csum),
158 ENA_STAT_RX_ENTRY(page_alloc_fail),
159 ENA_STAT_RX_ENTRY(skb_alloc_fail),
160 ENA_STAT_RX_ENTRY(dma_mapping_err),
161 ENA_STAT_RX_ENTRY(bad_desc_num),
162 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
165 static const struct ena_stats ena_stats_ena_com_strings[] = {
166 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
167 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
168 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
169 ENA_STAT_ENA_COM_ENTRY(out_of_space),
170 ENA_STAT_ENA_COM_ENTRY(no_completion),
173 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
174 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
175 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
176 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
178 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
179 DEV_TX_OFFLOAD_UDP_CKSUM |\
180 DEV_TX_OFFLOAD_IPV4_CKSUM |\
181 DEV_TX_OFFLOAD_TCP_TSO)
182 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
186 /** Vendor ID used by Amazon devices */
187 #define PCI_VENDOR_ID_AMAZON 0x1D0F
188 /** Amazon devices */
189 #define PCI_DEVICE_ID_ENA_VF 0xEC20
190 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
192 #define ENA_TX_OFFLOAD_MASK (\
199 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
200 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
202 int ena_logtype_init;
203 int ena_logtype_driver;
205 static const struct rte_pci_id pci_id_ena_map[] = {
206 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
207 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
211 static struct ena_aenq_handlers aenq_handlers;
213 static int ena_device_init(struct ena_com_dev *ena_dev,
214 struct ena_com_dev_get_features_ctx *get_feat_ctx,
216 static int ena_dev_configure(struct rte_eth_dev *dev);
217 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
219 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
221 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
222 uint16_t nb_desc, unsigned int socket_id,
223 const struct rte_eth_txconf *tx_conf);
224 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
225 uint16_t nb_desc, unsigned int socket_id,
226 const struct rte_eth_rxconf *rx_conf,
227 struct rte_mempool *mp);
228 static uint16_t eth_ena_recv_pkts(void *rx_queue,
229 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
230 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
231 static void ena_init_rings(struct ena_adapter *adapter);
232 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
233 static int ena_start(struct rte_eth_dev *dev);
234 static void ena_stop(struct rte_eth_dev *dev);
235 static void ena_close(struct rte_eth_dev *dev);
236 static int ena_dev_reset(struct rte_eth_dev *dev);
237 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
238 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
239 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
240 static void ena_rx_queue_release(void *queue);
241 static void ena_tx_queue_release(void *queue);
242 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
243 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
244 static int ena_link_update(struct rte_eth_dev *dev,
245 int wait_to_complete);
246 static int ena_create_io_queue(struct ena_ring *ring);
247 static void ena_queue_stop(struct ena_ring *ring);
248 static void ena_queue_stop_all(struct rte_eth_dev *dev,
249 enum ena_ring_type ring_type);
250 static int ena_queue_start(struct ena_ring *ring);
251 static int ena_queue_start_all(struct rte_eth_dev *dev,
252 enum ena_ring_type ring_type);
253 static void ena_stats_restart(struct rte_eth_dev *dev);
254 static void ena_infos_get(struct rte_eth_dev *dev,
255 struct rte_eth_dev_info *dev_info);
256 static int ena_rss_reta_update(struct rte_eth_dev *dev,
257 struct rte_eth_rss_reta_entry64 *reta_conf,
259 static int ena_rss_reta_query(struct rte_eth_dev *dev,
260 struct rte_eth_rss_reta_entry64 *reta_conf,
262 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
263 static void ena_interrupt_handler_rte(void *cb_arg);
264 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
265 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
266 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
268 static const struct eth_dev_ops ena_dev_ops = {
269 .dev_configure = ena_dev_configure,
270 .dev_infos_get = ena_infos_get,
271 .rx_queue_setup = ena_rx_queue_setup,
272 .tx_queue_setup = ena_tx_queue_setup,
273 .dev_start = ena_start,
274 .dev_stop = ena_stop,
275 .link_update = ena_link_update,
276 .stats_get = ena_stats_get,
277 .mtu_set = ena_mtu_set,
278 .rx_queue_release = ena_rx_queue_release,
279 .tx_queue_release = ena_tx_queue_release,
280 .dev_close = ena_close,
281 .dev_reset = ena_dev_reset,
282 .reta_update = ena_rss_reta_update,
283 .reta_query = ena_rss_reta_query,
286 #define NUMA_NO_NODE SOCKET_ID_ANY
288 static inline int ena_cpu_to_node(int cpu)
290 struct rte_config *config = rte_eal_get_configuration();
291 struct rte_fbarray *arr = &config->mem_config->memzones;
292 const struct rte_memzone *mz;
294 if (unlikely(cpu >= RTE_MAX_MEMZONE))
297 mz = rte_fbarray_get(arr, cpu);
299 return mz->socket_id;
302 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
303 struct ena_com_rx_ctx *ena_rx_ctx)
305 uint64_t ol_flags = 0;
306 uint32_t packet_type = 0;
308 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
309 packet_type |= RTE_PTYPE_L4_TCP;
310 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
311 packet_type |= RTE_PTYPE_L4_UDP;
313 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
314 packet_type |= RTE_PTYPE_L3_IPV4;
315 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
316 packet_type |= RTE_PTYPE_L3_IPV6;
318 if (unlikely(ena_rx_ctx->l4_csum_err))
319 ol_flags |= PKT_RX_L4_CKSUM_BAD;
320 if (unlikely(ena_rx_ctx->l3_csum_err))
321 ol_flags |= PKT_RX_IP_CKSUM_BAD;
323 mbuf->ol_flags = ol_flags;
324 mbuf->packet_type = packet_type;
327 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
328 struct ena_com_tx_ctx *ena_tx_ctx,
329 uint64_t queue_offloads)
331 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
333 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
334 (queue_offloads & QUEUE_OFFLOADS)) {
335 /* check if TSO is required */
336 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
337 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
338 ena_tx_ctx->tso_enable = true;
340 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
343 /* check if L3 checksum is needed */
344 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
345 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
346 ena_tx_ctx->l3_csum_enable = true;
348 if (mbuf->ol_flags & PKT_TX_IPV6) {
349 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
351 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
353 /* set don't fragment (DF) flag */
354 if (mbuf->packet_type &
355 (RTE_PTYPE_L4_NONFRAG
356 | RTE_PTYPE_INNER_L4_NONFRAG))
357 ena_tx_ctx->df = true;
360 /* check if L4 checksum is needed */
361 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
362 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
363 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
364 ena_tx_ctx->l4_csum_enable = true;
365 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
366 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
367 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
368 ena_tx_ctx->l4_csum_enable = true;
370 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
371 ena_tx_ctx->l4_csum_enable = false;
374 ena_meta->mss = mbuf->tso_segsz;
375 ena_meta->l3_hdr_len = mbuf->l3_len;
376 ena_meta->l3_hdr_offset = mbuf->l2_len;
378 ena_tx_ctx->meta_valid = true;
380 ena_tx_ctx->meta_valid = false;
384 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
386 if (likely(req_id < rx_ring->ring_size))
389 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
391 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
392 rx_ring->adapter->trigger_reset = true;
397 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
399 struct ena_tx_buffer *tx_info = NULL;
401 if (likely(req_id < tx_ring->ring_size)) {
402 tx_info = &tx_ring->tx_buffer_info[req_id];
403 if (likely(tx_info->mbuf))
408 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
410 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
412 /* Trigger device reset */
413 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
414 tx_ring->adapter->trigger_reset = true;
418 static void ena_config_host_info(struct ena_com_dev *ena_dev)
420 struct ena_admin_host_info *host_info;
423 /* Allocate only the host info */
424 rc = ena_com_allocate_host_info(ena_dev);
426 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
430 host_info = ena_dev->host_attr.host_info;
432 host_info->os_type = ENA_ADMIN_OS_DPDK;
433 host_info->kernel_ver = RTE_VERSION;
434 snprintf((char *)host_info->kernel_ver_str,
435 sizeof(host_info->kernel_ver_str),
436 "%s", rte_version());
437 host_info->os_dist = RTE_VERSION;
438 snprintf((char *)host_info->os_dist_str,
439 sizeof(host_info->os_dist_str),
440 "%s", rte_version());
441 host_info->driver_version =
442 (DRV_MODULE_VER_MAJOR) |
443 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
444 (DRV_MODULE_VER_SUBMINOR <<
445 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
446 host_info->num_cpus = rte_lcore_count();
448 rc = ena_com_set_host_attributes(ena_dev);
450 if (rc == -ENA_COM_UNSUPPORTED)
451 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
453 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
461 ena_com_delete_host_info(ena_dev);
465 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
467 if (sset != ETH_SS_STATS)
470 /* Workaround for clang:
471 * touch internal structures to prevent
474 ENA_TOUCH(ena_stats_global_strings);
475 ENA_TOUCH(ena_stats_tx_strings);
476 ENA_TOUCH(ena_stats_rx_strings);
477 ENA_TOUCH(ena_stats_ena_com_strings);
479 return dev->data->nb_tx_queues *
480 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
481 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
484 static void ena_config_debug_area(struct ena_adapter *adapter)
489 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
491 RTE_LOG(ERR, PMD, "SS count is negative\n");
495 /* allocate 32 bytes for each string and 64bit for the value */
496 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
498 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
500 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
504 rc = ena_com_set_host_attributes(&adapter->ena_dev);
506 if (rc == -ENA_COM_UNSUPPORTED)
507 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
509 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
516 ena_com_delete_debug_area(&adapter->ena_dev);
519 static void ena_close(struct rte_eth_dev *dev)
521 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
522 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
523 struct ena_adapter *adapter =
524 (struct ena_adapter *)(dev->data->dev_private);
526 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
528 adapter->state = ENA_ADAPTER_STATE_CLOSED;
530 ena_rx_queue_release_all(dev);
531 ena_tx_queue_release_all(dev);
533 rte_free(adapter->drv_stats);
534 adapter->drv_stats = NULL;
536 rte_intr_disable(intr_handle);
537 rte_intr_callback_unregister(intr_handle,
538 ena_interrupt_handler_rte,
542 * MAC is not allocated dynamically. Setting NULL should prevent from
543 * release of the resource in the rte_eth_dev_release_port().
545 dev->data->mac_addrs = NULL;
549 ena_dev_reset(struct rte_eth_dev *dev)
553 ena_destroy_device(dev);
554 rc = eth_ena_dev_init(dev);
556 PMD_INIT_LOG(CRIT, "Cannot initialize device");
561 static int ena_rss_reta_update(struct rte_eth_dev *dev,
562 struct rte_eth_rss_reta_entry64 *reta_conf,
565 struct ena_adapter *adapter =
566 (struct ena_adapter *)(dev->data->dev_private);
567 struct ena_com_dev *ena_dev = &adapter->ena_dev;
573 if ((reta_size == 0) || (reta_conf == NULL))
576 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
577 RTE_LOG(WARNING, PMD,
578 "indirection table %d is bigger than supported (%d)\n",
579 reta_size, ENA_RX_RSS_TABLE_SIZE);
583 for (i = 0 ; i < reta_size ; i++) {
584 /* each reta_conf is for 64 entries.
585 * to support 128 we use 2 conf of 64
587 conf_idx = i / RTE_RETA_GROUP_SIZE;
588 idx = i % RTE_RETA_GROUP_SIZE;
589 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
591 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
593 rc = ena_com_indirect_table_fill_entry(ena_dev,
596 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
598 "Cannot fill indirect table\n");
604 rc = ena_com_indirect_table_set(ena_dev);
605 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
606 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
610 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
611 __func__, reta_size, adapter->rte_dev->data->port_id);
616 /* Query redirection table. */
617 static int ena_rss_reta_query(struct rte_eth_dev *dev,
618 struct rte_eth_rss_reta_entry64 *reta_conf,
621 struct ena_adapter *adapter =
622 (struct ena_adapter *)(dev->data->dev_private);
623 struct ena_com_dev *ena_dev = &adapter->ena_dev;
626 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
630 if (reta_size == 0 || reta_conf == NULL ||
631 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
634 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
635 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
636 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
640 for (i = 0 ; i < reta_size ; i++) {
641 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
642 reta_idx = i % RTE_RETA_GROUP_SIZE;
643 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
644 reta_conf[reta_conf_idx].reta[reta_idx] =
645 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
651 static int ena_rss_init_default(struct ena_adapter *adapter)
653 struct ena_com_dev *ena_dev = &adapter->ena_dev;
654 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
658 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
660 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
664 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
665 val = i % nb_rx_queues;
666 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
667 ENA_IO_RXQ_IDX(val));
668 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
669 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
674 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
675 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
676 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
677 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
681 rc = ena_com_set_default_hash_ctrl(ena_dev);
682 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
683 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
687 rc = ena_com_indirect_table_set(ena_dev);
688 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
689 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
692 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
693 adapter->rte_dev->data->port_id);
698 ena_com_rss_destroy(ena_dev);
704 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
706 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
707 int nb_queues = dev->data->nb_rx_queues;
710 for (i = 0; i < nb_queues; i++)
711 ena_rx_queue_release(queues[i]);
714 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
716 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
717 int nb_queues = dev->data->nb_tx_queues;
720 for (i = 0; i < nb_queues; i++)
721 ena_tx_queue_release(queues[i]);
724 static void ena_rx_queue_release(void *queue)
726 struct ena_ring *ring = (struct ena_ring *)queue;
728 /* Free ring resources */
729 if (ring->rx_buffer_info)
730 rte_free(ring->rx_buffer_info);
731 ring->rx_buffer_info = NULL;
733 if (ring->rx_refill_buffer)
734 rte_free(ring->rx_refill_buffer);
735 ring->rx_refill_buffer = NULL;
737 if (ring->empty_rx_reqs)
738 rte_free(ring->empty_rx_reqs);
739 ring->empty_rx_reqs = NULL;
741 ring->configured = 0;
743 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
744 ring->port_id, ring->id);
747 static void ena_tx_queue_release(void *queue)
749 struct ena_ring *ring = (struct ena_ring *)queue;
751 /* Free ring resources */
752 if (ring->push_buf_intermediate_buf)
753 rte_free(ring->push_buf_intermediate_buf);
755 if (ring->tx_buffer_info)
756 rte_free(ring->tx_buffer_info);
758 if (ring->empty_tx_reqs)
759 rte_free(ring->empty_tx_reqs);
761 ring->empty_tx_reqs = NULL;
762 ring->tx_buffer_info = NULL;
763 ring->push_buf_intermediate_buf = NULL;
765 ring->configured = 0;
767 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
768 ring->port_id, ring->id);
771 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
773 unsigned int ring_mask = ring->ring_size - 1;
775 while (ring->next_to_clean != ring->next_to_use) {
777 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
780 rte_mbuf_raw_free(m);
782 ring->next_to_clean++;
786 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
790 for (i = 0; i < ring->ring_size; ++i) {
791 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
794 rte_pktmbuf_free(tx_buf->mbuf);
796 ring->next_to_clean++;
800 static int ena_link_update(struct rte_eth_dev *dev,
801 __rte_unused int wait_to_complete)
803 struct rte_eth_link *link = &dev->data->dev_link;
804 struct ena_adapter *adapter;
806 adapter = (struct ena_adapter *)(dev->data->dev_private);
808 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
809 link->link_speed = ETH_SPEED_NUM_NONE;
810 link->link_duplex = ETH_LINK_FULL_DUPLEX;
815 static int ena_queue_start_all(struct rte_eth_dev *dev,
816 enum ena_ring_type ring_type)
818 struct ena_adapter *adapter =
819 (struct ena_adapter *)(dev->data->dev_private);
820 struct ena_ring *queues = NULL;
825 if (ring_type == ENA_RING_TYPE_RX) {
826 queues = adapter->rx_ring;
827 nb_queues = dev->data->nb_rx_queues;
829 queues = adapter->tx_ring;
830 nb_queues = dev->data->nb_tx_queues;
832 for (i = 0; i < nb_queues; i++) {
833 if (queues[i].configured) {
834 if (ring_type == ENA_RING_TYPE_RX) {
836 dev->data->rx_queues[i] == &queues[i],
837 "Inconsistent state of rx queues\n");
840 dev->data->tx_queues[i] == &queues[i],
841 "Inconsistent state of tx queues\n");
844 rc = ena_queue_start(&queues[i]);
848 "failed to start queue %d type(%d)",
859 if (queues[i].configured)
860 ena_queue_stop(&queues[i]);
865 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
867 uint32_t max_frame_len = adapter->max_mtu;
869 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
870 DEV_RX_OFFLOAD_JUMBO_FRAME)
872 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
874 return max_frame_len;
877 static int ena_check_valid_conf(struct ena_adapter *adapter)
879 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
881 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
882 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
883 "max mtu: %d, min mtu: %d",
884 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
885 return ENA_COM_UNSUPPORTED;
892 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
894 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
895 struct ena_com_dev *ena_dev = ctx->ena_dev;
896 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
897 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
899 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
900 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
901 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
902 rx_queue_size = RTE_MIN(rx_queue_size,
903 max_queue_ext->max_rx_cq_depth);
904 rx_queue_size = RTE_MIN(rx_queue_size,
905 max_queue_ext->max_rx_sq_depth);
906 tx_queue_size = RTE_MIN(tx_queue_size,
907 max_queue_ext->max_tx_cq_depth);
909 if (ena_dev->tx_mem_queue_type ==
910 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
911 tx_queue_size = RTE_MIN(tx_queue_size,
914 tx_queue_size = RTE_MIN(tx_queue_size,
915 max_queue_ext->max_tx_sq_depth);
918 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
919 max_queue_ext->max_per_packet_rx_descs);
920 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
921 max_queue_ext->max_per_packet_tx_descs);
923 struct ena_admin_queue_feature_desc *max_queues =
924 &ctx->get_feat_ctx->max_queues;
925 rx_queue_size = RTE_MIN(rx_queue_size,
926 max_queues->max_cq_depth);
927 rx_queue_size = RTE_MIN(rx_queue_size,
928 max_queues->max_sq_depth);
929 tx_queue_size = RTE_MIN(tx_queue_size,
930 max_queues->max_cq_depth);
932 if (ena_dev->tx_mem_queue_type ==
933 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
934 tx_queue_size = RTE_MIN(tx_queue_size,
937 tx_queue_size = RTE_MIN(tx_queue_size,
938 max_queues->max_sq_depth);
941 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
942 max_queues->max_packet_tx_descs);
943 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
944 max_queues->max_packet_rx_descs);
947 /* Round down to the nearest power of 2 */
948 rx_queue_size = rte_align32prevpow2(rx_queue_size);
949 tx_queue_size = rte_align32prevpow2(tx_queue_size);
951 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
952 PMD_INIT_LOG(ERR, "Invalid queue size");
956 ctx->rx_queue_size = rx_queue_size;
957 ctx->tx_queue_size = tx_queue_size;
962 static void ena_stats_restart(struct rte_eth_dev *dev)
964 struct ena_adapter *adapter =
965 (struct ena_adapter *)(dev->data->dev_private);
967 rte_atomic64_init(&adapter->drv_stats->ierrors);
968 rte_atomic64_init(&adapter->drv_stats->oerrors);
969 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
972 static int ena_stats_get(struct rte_eth_dev *dev,
973 struct rte_eth_stats *stats)
975 struct ena_admin_basic_stats ena_stats;
976 struct ena_adapter *adapter =
977 (struct ena_adapter *)(dev->data->dev_private);
978 struct ena_com_dev *ena_dev = &adapter->ena_dev;
981 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
984 memset(&ena_stats, 0, sizeof(ena_stats));
985 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
987 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n");
991 /* Set of basic statistics from ENA */
992 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
993 ena_stats.rx_pkts_low);
994 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
995 ena_stats.tx_pkts_low);
996 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
997 ena_stats.rx_bytes_low);
998 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
999 ena_stats.tx_bytes_low);
1000 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1001 ena_stats.rx_drops_low);
1003 /* Driver related stats */
1004 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1005 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1006 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1010 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1012 struct ena_adapter *adapter;
1013 struct ena_com_dev *ena_dev;
1016 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1017 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1018 adapter = (struct ena_adapter *)(dev->data->dev_private);
1020 ena_dev = &adapter->ena_dev;
1021 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1023 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1025 "Invalid MTU setting. new_mtu: %d "
1026 "max mtu: %d min mtu: %d\n",
1027 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1031 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1033 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1035 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1040 static int ena_start(struct rte_eth_dev *dev)
1042 struct ena_adapter *adapter =
1043 (struct ena_adapter *)(dev->data->dev_private);
1047 rc = ena_check_valid_conf(adapter);
1051 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1055 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1059 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1060 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1061 rc = ena_rss_init_default(adapter);
1066 ena_stats_restart(dev);
1068 adapter->timestamp_wd = rte_get_timer_cycles();
1069 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1071 ticks = rte_get_timer_hz();
1072 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1073 ena_timer_wd_callback, adapter);
1075 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1080 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1082 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1086 static void ena_stop(struct rte_eth_dev *dev)
1088 struct ena_adapter *adapter =
1089 (struct ena_adapter *)(dev->data->dev_private);
1090 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1093 rte_timer_stop_sync(&adapter->timer_wd);
1094 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1095 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1097 if (adapter->trigger_reset) {
1098 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1100 RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc);
1103 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1106 static int ena_create_io_queue(struct ena_ring *ring)
1108 struct ena_adapter *adapter;
1109 struct ena_com_dev *ena_dev;
1110 struct ena_com_create_io_ctx ctx =
1111 /* policy set to _HOST just to satisfy icc compiler */
1112 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1118 adapter = ring->adapter;
1119 ena_dev = &adapter->ena_dev;
1121 if (ring->type == ENA_RING_TYPE_TX) {
1122 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1123 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1124 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1125 ctx.queue_size = adapter->tx_ring_size;
1126 for (i = 0; i < ring->ring_size; i++)
1127 ring->empty_tx_reqs[i] = i;
1129 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1130 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1131 ctx.queue_size = adapter->rx_ring_size;
1132 for (i = 0; i < ring->ring_size; i++)
1133 ring->empty_rx_reqs[i] = i;
1136 ctx.msix_vector = -1; /* interrupts not used */
1137 ctx.numa_node = ena_cpu_to_node(ring->id);
1139 rc = ena_com_create_io_queue(ena_dev, &ctx);
1142 "failed to create io queue #%d (qid:%d) rc: %d\n",
1143 ring->id, ena_qid, rc);
1147 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1148 &ring->ena_com_io_sq,
1149 &ring->ena_com_io_cq);
1152 "Failed to get io queue handlers. queue num %d rc: %d\n",
1154 ena_com_destroy_io_queue(ena_dev, ena_qid);
1158 if (ring->type == ENA_RING_TYPE_TX)
1159 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1164 static void ena_queue_stop(struct ena_ring *ring)
1166 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1168 if (ring->type == ENA_RING_TYPE_RX) {
1169 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1170 ena_rx_queue_release_bufs(ring);
1172 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1173 ena_tx_queue_release_bufs(ring);
1177 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1178 enum ena_ring_type ring_type)
1180 struct ena_adapter *adapter =
1181 (struct ena_adapter *)(dev->data->dev_private);
1182 struct ena_ring *queues = NULL;
1183 uint16_t nb_queues, i;
1185 if (ring_type == ENA_RING_TYPE_RX) {
1186 queues = adapter->rx_ring;
1187 nb_queues = dev->data->nb_rx_queues;
1189 queues = adapter->tx_ring;
1190 nb_queues = dev->data->nb_tx_queues;
1193 for (i = 0; i < nb_queues; ++i)
1194 if (queues[i].configured)
1195 ena_queue_stop(&queues[i]);
1198 static int ena_queue_start(struct ena_ring *ring)
1202 ena_assert_msg(ring->configured == 1,
1203 "Trying to start unconfigured queue\n");
1205 rc = ena_create_io_queue(ring);
1207 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1211 ring->next_to_clean = 0;
1212 ring->next_to_use = 0;
1214 if (ring->type == ENA_RING_TYPE_TX)
1217 bufs_num = ring->ring_size - 1;
1218 rc = ena_populate_rx_queue(ring, bufs_num);
1219 if (rc != bufs_num) {
1220 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1221 ENA_IO_RXQ_IDX(ring->id));
1222 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1223 return ENA_COM_FAULT;
1229 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1232 __rte_unused unsigned int socket_id,
1233 const struct rte_eth_txconf *tx_conf)
1235 struct ena_ring *txq = NULL;
1236 struct ena_adapter *adapter =
1237 (struct ena_adapter *)(dev->data->dev_private);
1240 txq = &adapter->tx_ring[queue_idx];
1242 if (txq->configured) {
1244 "API violation. Queue %d is already configured\n",
1246 return ENA_COM_FAULT;
1249 if (!rte_is_power_of_2(nb_desc)) {
1251 "Unsupported size of TX queue: %d is not a power of 2.\n",
1256 if (nb_desc > adapter->tx_ring_size) {
1258 "Unsupported size of TX queue (max size: %d)\n",
1259 adapter->tx_ring_size);
1263 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1264 nb_desc = adapter->tx_ring_size;
1266 txq->port_id = dev->data->port_id;
1267 txq->next_to_clean = 0;
1268 txq->next_to_use = 0;
1269 txq->ring_size = nb_desc;
1271 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1272 sizeof(struct ena_tx_buffer) *
1274 RTE_CACHE_LINE_SIZE);
1275 if (!txq->tx_buffer_info) {
1276 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1280 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1281 sizeof(u16) * txq->ring_size,
1282 RTE_CACHE_LINE_SIZE);
1283 if (!txq->empty_tx_reqs) {
1284 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1285 rte_free(txq->tx_buffer_info);
1289 txq->push_buf_intermediate_buf =
1290 rte_zmalloc("txq->push_buf_intermediate_buf",
1291 txq->tx_max_header_size,
1292 RTE_CACHE_LINE_SIZE);
1293 if (!txq->push_buf_intermediate_buf) {
1294 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1295 rte_free(txq->tx_buffer_info);
1296 rte_free(txq->empty_tx_reqs);
1300 for (i = 0; i < txq->ring_size; i++)
1301 txq->empty_tx_reqs[i] = i;
1303 if (tx_conf != NULL) {
1305 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1308 /* Store pointer to this queue in upper layer */
1309 txq->configured = 1;
1310 dev->data->tx_queues[queue_idx] = txq;
1315 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1318 __rte_unused unsigned int socket_id,
1319 __rte_unused const struct rte_eth_rxconf *rx_conf,
1320 struct rte_mempool *mp)
1322 struct ena_adapter *adapter =
1323 (struct ena_adapter *)(dev->data->dev_private);
1324 struct ena_ring *rxq = NULL;
1327 rxq = &adapter->rx_ring[queue_idx];
1328 if (rxq->configured) {
1330 "API violation. Queue %d is already configured\n",
1332 return ENA_COM_FAULT;
1335 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1336 nb_desc = adapter->rx_ring_size;
1338 if (!rte_is_power_of_2(nb_desc)) {
1340 "Unsupported size of RX queue: %d is not a power of 2.\n",
1345 if (nb_desc > adapter->rx_ring_size) {
1347 "Unsupported size of RX queue (max size: %d)\n",
1348 adapter->rx_ring_size);
1352 rxq->port_id = dev->data->port_id;
1353 rxq->next_to_clean = 0;
1354 rxq->next_to_use = 0;
1355 rxq->ring_size = nb_desc;
1358 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1359 sizeof(struct rte_mbuf *) * nb_desc,
1360 RTE_CACHE_LINE_SIZE);
1361 if (!rxq->rx_buffer_info) {
1362 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1366 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1367 sizeof(struct rte_mbuf *) * nb_desc,
1368 RTE_CACHE_LINE_SIZE);
1370 if (!rxq->rx_refill_buffer) {
1371 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1372 rte_free(rxq->rx_buffer_info);
1373 rxq->rx_buffer_info = NULL;
1377 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1378 sizeof(uint16_t) * nb_desc,
1379 RTE_CACHE_LINE_SIZE);
1380 if (!rxq->empty_rx_reqs) {
1381 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1382 rte_free(rxq->rx_buffer_info);
1383 rxq->rx_buffer_info = NULL;
1384 rte_free(rxq->rx_refill_buffer);
1385 rxq->rx_refill_buffer = NULL;
1389 for (i = 0; i < nb_desc; i++)
1390 rxq->empty_tx_reqs[i] = i;
1392 /* Store pointer to this queue in upper layer */
1393 rxq->configured = 1;
1394 dev->data->rx_queues[queue_idx] = rxq;
1399 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1403 uint16_t ring_size = rxq->ring_size;
1404 uint16_t ring_mask = ring_size - 1;
1405 uint16_t next_to_use = rxq->next_to_use;
1406 uint16_t in_use, req_id;
1407 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1409 if (unlikely(!count))
1412 in_use = rxq->next_to_use - rxq->next_to_clean;
1413 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1415 /* get resources for incoming packets */
1416 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1417 if (unlikely(rc < 0)) {
1418 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1419 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1423 for (i = 0; i < count; i++) {
1424 uint16_t next_to_use_masked = next_to_use & ring_mask;
1425 struct rte_mbuf *mbuf = mbufs[i];
1426 struct ena_com_buf ebuf;
1428 if (likely((i + 4) < count))
1429 rte_prefetch0(mbufs[i + 4]);
1431 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1432 rc = validate_rx_req_id(rxq, req_id);
1433 if (unlikely(rc < 0))
1435 rxq->rx_buffer_info[req_id] = mbuf;
1437 /* prepare physical address for DMA transaction */
1438 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1439 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1440 /* pass resource to device */
1441 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1444 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1445 rxq->rx_buffer_info[req_id] = NULL;
1451 if (unlikely(i < count)) {
1452 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1453 "buffers (from %d)\n", rxq->id, i, count);
1454 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1458 /* When we submitted free recources to device... */
1459 if (likely(i > 0)) {
1460 /* ...let HW know that it can fill buffers with data
1462 * Add memory barrier to make sure the desc were written before
1466 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1468 rxq->next_to_use = next_to_use;
1474 static int ena_device_init(struct ena_com_dev *ena_dev,
1475 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1478 uint32_t aenq_groups;
1480 bool readless_supported;
1482 /* Initialize mmio registers */
1483 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1485 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1489 /* The PCIe configuration space revision id indicate if mmio reg
1492 readless_supported =
1493 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1494 & ENA_MMIO_DISABLE_REG_READ);
1495 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1498 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1500 RTE_LOG(ERR, PMD, "cannot reset device\n");
1501 goto err_mmio_read_less;
1504 /* check FW version */
1505 rc = ena_com_validate_version(ena_dev);
1507 RTE_LOG(ERR, PMD, "device version is too low\n");
1508 goto err_mmio_read_less;
1511 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1513 /* ENA device administration layer init */
1514 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1517 "cannot initialize ena admin queue with device\n");
1518 goto err_mmio_read_less;
1521 /* To enable the msix interrupts the driver needs to know the number
1522 * of queues. So the driver uses polling mode to retrieve this
1525 ena_com_set_admin_polling_mode(ena_dev, true);
1527 ena_config_host_info(ena_dev);
1529 /* Get Device Attributes and features */
1530 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1533 "cannot get attribute for ena device rc= %d\n", rc);
1534 goto err_admin_init;
1537 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1538 BIT(ENA_ADMIN_NOTIFICATION) |
1539 BIT(ENA_ADMIN_KEEP_ALIVE) |
1540 BIT(ENA_ADMIN_FATAL_ERROR) |
1541 BIT(ENA_ADMIN_WARNING);
1543 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1544 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1546 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1547 goto err_admin_init;
1550 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1555 ena_com_admin_destroy(ena_dev);
1558 ena_com_mmio_reg_read_request_destroy(ena_dev);
1563 static void ena_interrupt_handler_rte(void *cb_arg)
1565 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1566 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1568 ena_com_admin_q_comp_intr_handler(ena_dev);
1569 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1570 ena_com_aenq_intr_handler(ena_dev, adapter);
1573 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1575 if (!adapter->wd_state)
1578 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1581 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1582 adapter->keep_alive_timeout)) {
1583 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1584 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1585 adapter->trigger_reset = true;
1589 /* Check if admin queue is enabled */
1590 static void check_for_admin_com_state(struct ena_adapter *adapter)
1592 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1593 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1594 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1595 adapter->trigger_reset = true;
1599 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1602 struct ena_adapter *adapter = (struct ena_adapter *)arg;
1603 struct rte_eth_dev *dev = adapter->rte_dev;
1605 check_for_missing_keep_alive(adapter);
1606 check_for_admin_com_state(adapter);
1608 if (unlikely(adapter->trigger_reset)) {
1609 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1610 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1616 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1618 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1619 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1620 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1621 llq_config->llq_num_decs_before_header =
1622 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1623 llq_config->llq_ring_entry_size_value = 128;
1627 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1628 struct ena_com_dev *ena_dev,
1629 struct ena_admin_feature_llq_desc *llq,
1630 struct ena_llq_configurations *llq_default_configurations)
1633 u32 llq_feature_mask;
1635 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1636 if (!(ena_dev->supported_features & llq_feature_mask)) {
1638 "LLQ is not supported. Fallback to host mode policy.\n");
1639 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1643 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1645 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1646 "Fallback to host mode policy.");
1647 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1651 /* Nothing to config, exit */
1652 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1655 if (!adapter->dev_mem_base) {
1656 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1657 "Fallback to host mode policy.\n.");
1658 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1662 ena_dev->mem_bar = adapter->dev_mem_base;
1667 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1668 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1670 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1672 /* Regular queues capabilities */
1673 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1674 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1675 &get_feat_ctx->max_queue_ext.max_queue_ext;
1676 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1677 max_queue_ext->max_rx_cq_num);
1678 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1679 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1681 struct ena_admin_queue_feature_desc *max_queues =
1682 &get_feat_ctx->max_queues;
1683 io_tx_sq_num = max_queues->max_sq_num;
1684 io_tx_cq_num = max_queues->max_cq_num;
1685 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1688 /* In case of LLQ use the llq number in the get feature cmd */
1689 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1690 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1692 io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
1693 io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
1694 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1695 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1697 if (unlikely(io_queue_num == 0)) {
1698 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1702 return io_queue_num;
1705 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1707 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1708 struct rte_pci_device *pci_dev;
1709 struct rte_intr_handle *intr_handle;
1710 struct ena_adapter *adapter =
1711 (struct ena_adapter *)(eth_dev->data->dev_private);
1712 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1713 struct ena_com_dev_get_features_ctx get_feat_ctx;
1714 struct ena_llq_configurations llq_config;
1715 const char *queue_type_str;
1718 static int adapters_found;
1721 memset(adapter, 0, sizeof(struct ena_adapter));
1722 ena_dev = &adapter->ena_dev;
1724 eth_dev->dev_ops = &ena_dev_ops;
1725 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1726 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1727 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1728 adapter->rte_eth_dev_data = eth_dev->data;
1729 adapter->rte_dev = eth_dev;
1731 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1734 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1735 adapter->pdev = pci_dev;
1737 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1738 pci_dev->addr.domain,
1740 pci_dev->addr.devid,
1741 pci_dev->addr.function);
1743 intr_handle = &pci_dev->intr_handle;
1745 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1746 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1748 if (!adapter->regs) {
1749 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1754 ena_dev->reg_bar = adapter->regs;
1755 ena_dev->dmadev = adapter->pdev;
1757 adapter->id_number = adapters_found;
1759 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1760 adapter->id_number);
1762 /* device specific initialization routine */
1763 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1765 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1768 adapter->wd_state = wd_state;
1770 set_default_llq_configurations(&llq_config);
1771 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1772 &get_feat_ctx.llq, &llq_config);
1774 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1778 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1779 queue_type_str = "Regular";
1781 queue_type_str = "Low latency";
1782 RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1784 calc_queue_ctx.ena_dev = ena_dev;
1785 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1786 adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1789 rc = ena_calc_queue_size(&calc_queue_ctx);
1790 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1792 goto err_device_destroy;
1795 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1796 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1798 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1799 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1801 /* prepare ring structures */
1802 ena_init_rings(adapter);
1804 ena_config_debug_area(adapter);
1806 /* Set max MTU for this device */
1807 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1809 /* set device support for TSO */
1810 adapter->tso4_supported = get_feat_ctx.offload.tx &
1811 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1813 /* Copy MAC address and point DPDK to it */
1814 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1815 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1816 (struct ether_addr *)adapter->mac_addr);
1819 * Pass the information to the rte_eth_dev_close() that it should also
1820 * release the private port resources.
1822 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1824 adapter->drv_stats = rte_zmalloc("adapter stats",
1825 sizeof(*adapter->drv_stats),
1826 RTE_CACHE_LINE_SIZE);
1827 if (!adapter->drv_stats) {
1828 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1830 goto err_delete_debug_area;
1833 rte_intr_callback_register(intr_handle,
1834 ena_interrupt_handler_rte,
1836 rte_intr_enable(intr_handle);
1837 ena_com_set_admin_polling_mode(ena_dev, false);
1838 ena_com_admin_aenq_enable(ena_dev);
1840 if (adapters_found == 0)
1841 rte_timer_subsystem_init();
1842 rte_timer_init(&adapter->timer_wd);
1845 adapter->state = ENA_ADAPTER_STATE_INIT;
1849 err_delete_debug_area:
1850 ena_com_delete_debug_area(ena_dev);
1853 ena_com_delete_host_info(ena_dev);
1854 ena_com_admin_destroy(ena_dev);
1860 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1862 struct ena_adapter *adapter =
1863 (struct ena_adapter *)(eth_dev->data->dev_private);
1864 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1866 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1869 ena_com_set_admin_running_state(ena_dev, false);
1871 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1874 ena_com_delete_debug_area(ena_dev);
1875 ena_com_delete_host_info(ena_dev);
1877 ena_com_abort_admin_commands(ena_dev);
1878 ena_com_wait_for_abort_completion(ena_dev);
1879 ena_com_admin_destroy(ena_dev);
1880 ena_com_mmio_reg_read_request_destroy(ena_dev);
1882 adapter->state = ENA_ADAPTER_STATE_FREE;
1885 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1887 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1890 ena_destroy_device(eth_dev);
1892 eth_dev->dev_ops = NULL;
1893 eth_dev->rx_pkt_burst = NULL;
1894 eth_dev->tx_pkt_burst = NULL;
1895 eth_dev->tx_pkt_prepare = NULL;
1900 static int ena_dev_configure(struct rte_eth_dev *dev)
1902 struct ena_adapter *adapter =
1903 (struct ena_adapter *)(dev->data->dev_private);
1905 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1907 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1908 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1912 static void ena_init_rings(struct ena_adapter *adapter)
1916 for (i = 0; i < adapter->num_queues; i++) {
1917 struct ena_ring *ring = &adapter->tx_ring[i];
1919 ring->configured = 0;
1920 ring->type = ENA_RING_TYPE_TX;
1921 ring->adapter = adapter;
1923 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1924 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1925 ring->sgl_size = adapter->max_tx_sgl_size;
1928 for (i = 0; i < adapter->num_queues; i++) {
1929 struct ena_ring *ring = &adapter->rx_ring[i];
1931 ring->configured = 0;
1932 ring->type = ENA_RING_TYPE_RX;
1933 ring->adapter = adapter;
1935 ring->sgl_size = adapter->max_rx_sgl_size;
1939 static void ena_infos_get(struct rte_eth_dev *dev,
1940 struct rte_eth_dev_info *dev_info)
1942 struct ena_adapter *adapter;
1943 struct ena_com_dev *ena_dev;
1944 struct ena_com_dev_get_features_ctx feat;
1945 uint64_t rx_feat = 0, tx_feat = 0;
1948 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1949 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1950 adapter = (struct ena_adapter *)(dev->data->dev_private);
1952 ena_dev = &adapter->ena_dev;
1953 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1955 dev_info->speed_capa =
1957 ETH_LINK_SPEED_2_5G |
1959 ETH_LINK_SPEED_10G |
1960 ETH_LINK_SPEED_25G |
1961 ETH_LINK_SPEED_40G |
1962 ETH_LINK_SPEED_50G |
1963 ETH_LINK_SPEED_100G;
1965 /* Get supported features from HW */
1966 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1969 "Cannot get attribute for ena device rc= %d\n", rc);
1973 /* Set Tx & Rx features available for device */
1974 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1975 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1977 if (feat.offload.tx &
1978 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1979 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1980 DEV_TX_OFFLOAD_UDP_CKSUM |
1981 DEV_TX_OFFLOAD_TCP_CKSUM;
1983 if (feat.offload.rx_supported &
1984 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1985 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1986 DEV_RX_OFFLOAD_UDP_CKSUM |
1987 DEV_RX_OFFLOAD_TCP_CKSUM;
1989 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1991 /* Inform framework about available features */
1992 dev_info->rx_offload_capa = rx_feat;
1993 dev_info->rx_queue_offload_capa = rx_feat;
1994 dev_info->tx_offload_capa = tx_feat;
1995 dev_info->tx_queue_offload_capa = tx_feat;
1997 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1998 dev_info->max_rx_pktlen = adapter->max_mtu;
1999 dev_info->max_mac_addrs = 1;
2001 dev_info->max_rx_queues = adapter->num_queues;
2002 dev_info->max_tx_queues = adapter->num_queues;
2003 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2005 adapter->tx_supported_offloads = tx_feat;
2006 adapter->rx_supported_offloads = rx_feat;
2008 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
2009 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2010 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2011 adapter->max_rx_sgl_size);
2012 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2013 adapter->max_rx_sgl_size);
2015 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2016 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2017 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2018 adapter->max_tx_sgl_size);
2019 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2020 adapter->max_tx_sgl_size);
2023 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2026 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2027 unsigned int ring_size = rx_ring->ring_size;
2028 unsigned int ring_mask = ring_size - 1;
2029 uint16_t next_to_clean = rx_ring->next_to_clean;
2030 uint16_t desc_in_use = 0;
2032 unsigned int recv_idx = 0;
2033 struct rte_mbuf *mbuf = NULL;
2034 struct rte_mbuf *mbuf_head = NULL;
2035 struct rte_mbuf *mbuf_prev = NULL;
2036 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2037 unsigned int completed;
2039 struct ena_com_rx_ctx ena_rx_ctx;
2042 /* Check adapter state */
2043 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2045 "Trying to receive pkts while device is NOT running\n");
2049 desc_in_use = rx_ring->next_to_use - next_to_clean;
2050 if (unlikely(nb_pkts > desc_in_use))
2051 nb_pkts = desc_in_use;
2053 for (completed = 0; completed < nb_pkts; completed++) {
2056 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2057 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2058 ena_rx_ctx.descs = 0;
2059 /* receive packet context */
2060 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2061 rx_ring->ena_com_io_sq,
2064 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2065 rx_ring->adapter->reset_reason =
2066 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2067 rx_ring->adapter->trigger_reset = true;
2071 if (unlikely(ena_rx_ctx.descs == 0))
2074 while (segments < ena_rx_ctx.descs) {
2075 req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2076 rc = validate_rx_req_id(rx_ring, req_id);
2080 mbuf = rx_buff_info[req_id];
2081 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2082 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2085 if (unlikely(segments == 0)) {
2086 mbuf->nb_segs = ena_rx_ctx.descs;
2087 mbuf->port = rx_ring->port_id;
2091 /* for multi-segment pkts create mbuf chain */
2092 mbuf_prev->next = mbuf;
2094 mbuf_head->pkt_len += mbuf->data_len;
2097 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2105 /* fill mbuf attributes if any */
2106 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2107 mbuf_head->hash.rss = ena_rx_ctx.hash;
2109 /* pass to DPDK application head mbuf */
2110 rx_pkts[recv_idx] = mbuf_head;
2114 rx_ring->next_to_clean = next_to_clean;
2116 desc_in_use = desc_in_use - completed + 1;
2117 /* Burst refill to save doorbells, memory barriers, const interval */
2118 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2119 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2125 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2131 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2132 struct ipv4_hdr *ip_hdr;
2134 uint16_t frag_field;
2136 for (i = 0; i != nb_pkts; i++) {
2138 ol_flags = m->ol_flags;
2140 if (!(ol_flags & PKT_TX_IPV4))
2143 /* If there was not L2 header length specified, assume it is
2144 * length of the ethernet header.
2146 if (unlikely(m->l2_len == 0))
2147 m->l2_len = sizeof(struct ether_hdr);
2149 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2151 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2153 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2154 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2156 /* If IPv4 header has DF flag enabled and TSO support is
2157 * disabled, partial chcecksum should not be calculated.
2159 if (!tx_ring->adapter->tso4_supported)
2163 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2164 (ol_flags & PKT_TX_L4_MASK) ==
2165 PKT_TX_SCTP_CKSUM) {
2166 rte_errno = -ENOTSUP;
2170 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2171 ret = rte_validate_tx_offload(m);
2178 /* In case we are supposed to TSO and have DF not set (DF=0)
2179 * hardware must be provided with partial checksum, otherwise
2180 * it will take care of necessary calculations.
2183 ret = rte_net_intel_cksum_flags_prepare(m,
2184 ol_flags & ~PKT_TX_TCP_SEG);
2194 static void ena_update_hints(struct ena_adapter *adapter,
2195 struct ena_admin_ena_hw_hints *hints)
2197 if (hints->admin_completion_tx_timeout)
2198 adapter->ena_dev.admin_queue.completion_timeout =
2199 hints->admin_completion_tx_timeout * 1000;
2201 if (hints->mmio_read_timeout)
2202 /* convert to usec */
2203 adapter->ena_dev.mmio_read.reg_read_to =
2204 hints->mmio_read_timeout * 1000;
2206 if (hints->driver_watchdog_timeout) {
2207 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2208 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2210 // Convert msecs to ticks
2211 adapter->keep_alive_timeout =
2212 (hints->driver_watchdog_timeout *
2213 rte_get_timer_hz()) / 1000;
2217 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2218 struct rte_mbuf *mbuf)
2220 struct ena_com_dev *ena_dev;
2221 int num_segments, header_len, rc;
2223 ena_dev = &tx_ring->adapter->ena_dev;
2224 num_segments = mbuf->nb_segs;
2225 header_len = mbuf->data_len;
2227 if (likely(num_segments < tx_ring->sgl_size))
2230 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2231 (num_segments == tx_ring->sgl_size) &&
2232 (header_len < tx_ring->tx_max_header_size))
2235 rc = rte_pktmbuf_linearize(mbuf);
2237 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2242 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2245 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2246 uint16_t next_to_use = tx_ring->next_to_use;
2247 uint16_t next_to_clean = tx_ring->next_to_clean;
2248 struct rte_mbuf *mbuf;
2250 unsigned int ring_size = tx_ring->ring_size;
2251 unsigned int ring_mask = ring_size - 1;
2252 struct ena_com_tx_ctx ena_tx_ctx;
2253 struct ena_tx_buffer *tx_info;
2254 struct ena_com_buf *ebuf;
2255 uint16_t rc, req_id, total_tx_descs = 0;
2256 uint16_t sent_idx = 0, empty_tx_reqs;
2257 uint16_t push_len = 0;
2261 /* Check adapter state */
2262 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2264 "Trying to xmit pkts while device is NOT running\n");
2268 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2269 if (nb_pkts > empty_tx_reqs)
2270 nb_pkts = empty_tx_reqs;
2272 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2273 mbuf = tx_pkts[sent_idx];
2275 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2279 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2280 tx_info = &tx_ring->tx_buffer_info[req_id];
2281 tx_info->mbuf = mbuf;
2282 tx_info->num_of_bufs = 0;
2283 ebuf = tx_info->bufs;
2285 /* Prepare TX context */
2286 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2287 memset(&ena_tx_ctx.ena_meta, 0x0,
2288 sizeof(struct ena_com_tx_meta));
2289 ena_tx_ctx.ena_bufs = ebuf;
2290 ena_tx_ctx.req_id = req_id;
2293 seg_len = mbuf->data_len;
2295 if (tx_ring->tx_mem_queue_type ==
2296 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2297 push_len = RTE_MIN(mbuf->pkt_len,
2298 tx_ring->tx_max_header_size);
2299 ena_tx_ctx.header_len = push_len;
2301 if (likely(push_len <= seg_len)) {
2302 /* If the push header is in the single segment,
2303 * then just point it to the 1st mbuf data.
2305 ena_tx_ctx.push_header =
2306 rte_pktmbuf_mtod(mbuf, uint8_t *);
2308 /* If the push header lays in the several
2309 * segments, copy it to the intermediate buffer.
2311 rte_pktmbuf_read(mbuf, 0, push_len,
2312 tx_ring->push_buf_intermediate_buf);
2313 ena_tx_ctx.push_header =
2314 tx_ring->push_buf_intermediate_buf;
2315 delta = push_len - seg_len;
2317 } /* there's no else as we take advantage of memset zeroing */
2319 /* Set TX offloads flags, if applicable */
2320 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2322 if (unlikely(mbuf->ol_flags &
2323 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2324 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2326 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2328 /* Process first segment taking into
2329 * consideration pushed header
2331 if (seg_len > push_len) {
2332 ebuf->paddr = mbuf->buf_iova +
2335 ebuf->len = seg_len - push_len;
2337 tx_info->num_of_bufs++;
2340 while ((mbuf = mbuf->next) != NULL) {
2341 seg_len = mbuf->data_len;
2343 /* Skip mbufs if whole data is pushed as a header */
2344 if (unlikely(delta > seg_len)) {
2349 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2350 ebuf->len = seg_len - delta;
2352 tx_info->num_of_bufs++;
2357 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2359 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2361 RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
2362 " achieved, writing doorbell to send burst\n",
2365 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2368 /* prepare the packet's descriptors to dma engine */
2369 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2370 &ena_tx_ctx, &nb_hw_desc);
2374 tx_info->tx_descs = nb_hw_desc;
2379 /* If there are ready packets to be xmitted... */
2381 /* ...let HW do its best :-) */
2383 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2385 tx_ring->next_to_use = next_to_use;
2388 /* Clear complete packets */
2389 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2390 rc = validate_tx_req_id(tx_ring, req_id);
2394 /* Get Tx info & store how many descs were processed */
2395 tx_info = &tx_ring->tx_buffer_info[req_id];
2396 total_tx_descs += tx_info->tx_descs;
2398 /* Free whole mbuf chain */
2399 mbuf = tx_info->mbuf;
2400 rte_pktmbuf_free(mbuf);
2401 tx_info->mbuf = NULL;
2403 /* Put back descriptor to the ring for reuse */
2404 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2407 /* If too many descs to clean, leave it for another run */
2408 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2412 if (total_tx_descs > 0) {
2413 /* acknowledge completion of sent packets */
2414 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2415 tx_ring->next_to_clean = next_to_clean;
2421 /*********************************************************************
2423 *********************************************************************/
2424 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2425 struct rte_pci_device *pci_dev)
2427 return rte_eth_dev_pci_generic_probe(pci_dev,
2428 sizeof(struct ena_adapter), eth_ena_dev_init);
2431 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2433 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2436 static struct rte_pci_driver rte_ena_pmd = {
2437 .id_table = pci_id_ena_map,
2438 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2439 RTE_PCI_DRV_WC_ACTIVATE,
2440 .probe = eth_ena_pci_probe,
2441 .remove = eth_ena_pci_remove,
2444 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2445 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2446 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2448 RTE_INIT(ena_init_log)
2450 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2451 if (ena_logtype_init >= 0)
2452 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2453 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2454 if (ena_logtype_driver >= 0)
2455 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2458 /******************************************************************************
2459 ******************************** AENQ Handlers *******************************
2460 *****************************************************************************/
2461 static void ena_update_on_link_change(void *adapter_data,
2462 struct ena_admin_aenq_entry *aenq_e)
2464 struct rte_eth_dev *eth_dev;
2465 struct ena_adapter *adapter;
2466 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2469 adapter = (struct ena_adapter *)adapter_data;
2470 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2471 eth_dev = adapter->rte_dev;
2473 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2474 adapter->link_status = status;
2476 ena_link_update(eth_dev, 0);
2477 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2480 static void ena_notification(void *data,
2481 struct ena_admin_aenq_entry *aenq_e)
2483 struct ena_adapter *adapter = (struct ena_adapter *)data;
2484 struct ena_admin_ena_hw_hints *hints;
2486 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2487 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2488 aenq_e->aenq_common_desc.group,
2489 ENA_ADMIN_NOTIFICATION);
2491 switch (aenq_e->aenq_common_desc.syndrom) {
2492 case ENA_ADMIN_UPDATE_HINTS:
2493 hints = (struct ena_admin_ena_hw_hints *)
2494 (&aenq_e->inline_data_w4);
2495 ena_update_hints(adapter, hints);
2498 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2499 aenq_e->aenq_common_desc.syndrom);
2503 static void ena_keep_alive(void *adapter_data,
2504 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2506 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2508 adapter->timestamp_wd = rte_get_timer_cycles();
2512 * This handler will called for unknown event group or unimplemented handlers
2514 static void unimplemented_aenq_handler(__rte_unused void *data,
2515 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2517 RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2518 "unimplemented handler\n");
2521 static struct ena_aenq_handlers aenq_handlers = {
2523 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2524 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2525 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2527 .unimplemented_handler = unimplemented_aenq_handler