4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 0
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 enum ethtool_stringset {
94 char name[ETH_GSTRING_LEN];
98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
100 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
103 #define ENA_STAT_ENTRY(stat, stat_type) { \
105 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
108 #define ENA_STAT_RX_ENTRY(stat) \
109 ENA_STAT_ENTRY(stat, rx)
111 #define ENA_STAT_TX_ENTRY(stat) \
112 ENA_STAT_ENTRY(stat, tx)
114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
115 ENA_STAT_ENTRY(stat, dev)
118 * Each rte_memzone should have unique name.
119 * To satisfy it, count number of allocation and add it to name.
121 uint32_t ena_alloc_cnt;
123 static const struct ena_stats ena_stats_global_strings[] = {
124 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
125 ENA_STAT_GLOBAL_ENTRY(io_suspend),
126 ENA_STAT_GLOBAL_ENTRY(io_resume),
127 ENA_STAT_GLOBAL_ENTRY(wd_expired),
128 ENA_STAT_GLOBAL_ENTRY(interface_up),
129 ENA_STAT_GLOBAL_ENTRY(interface_down),
130 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
133 static const struct ena_stats ena_stats_tx_strings[] = {
134 ENA_STAT_TX_ENTRY(cnt),
135 ENA_STAT_TX_ENTRY(bytes),
136 ENA_STAT_TX_ENTRY(queue_stop),
137 ENA_STAT_TX_ENTRY(queue_wakeup),
138 ENA_STAT_TX_ENTRY(dma_mapping_err),
139 ENA_STAT_TX_ENTRY(linearize),
140 ENA_STAT_TX_ENTRY(linearize_failed),
141 ENA_STAT_TX_ENTRY(tx_poll),
142 ENA_STAT_TX_ENTRY(doorbells),
143 ENA_STAT_TX_ENTRY(prepare_ctx_err),
144 ENA_STAT_TX_ENTRY(missing_tx_comp),
145 ENA_STAT_TX_ENTRY(bad_req_id),
148 static const struct ena_stats ena_stats_rx_strings[] = {
149 ENA_STAT_RX_ENTRY(cnt),
150 ENA_STAT_RX_ENTRY(bytes),
151 ENA_STAT_RX_ENTRY(refil_partial),
152 ENA_STAT_RX_ENTRY(bad_csum),
153 ENA_STAT_RX_ENTRY(page_alloc_fail),
154 ENA_STAT_RX_ENTRY(skb_alloc_fail),
155 ENA_STAT_RX_ENTRY(dma_mapping_err),
156 ENA_STAT_RX_ENTRY(bad_desc_num),
157 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
160 static const struct ena_stats ena_stats_ena_com_strings[] = {
161 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
162 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
163 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
164 ENA_STAT_ENA_COM_ENTRY(out_of_space),
165 ENA_STAT_ENA_COM_ENTRY(no_completion),
168 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
169 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
170 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
174 DEV_TX_OFFLOAD_UDP_CKSUM |\
175 DEV_TX_OFFLOAD_IPV4_CKSUM |\
176 DEV_TX_OFFLOAD_TCP_TSO)
177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
181 /** Vendor ID used by Amazon devices */
182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
183 /** Amazon devices */
184 #define PCI_DEVICE_ID_ENA_VF 0xEC20
185 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
187 #define ENA_TX_OFFLOAD_MASK (\
192 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
193 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
195 int ena_logtype_init;
196 int ena_logtype_driver;
198 static const struct rte_pci_id pci_id_ena_map[] = {
199 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
200 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
204 static struct ena_aenq_handlers aenq_handlers;
206 static int ena_device_init(struct ena_com_dev *ena_dev,
207 struct ena_com_dev_get_features_ctx *get_feat_ctx);
208 static int ena_dev_configure(struct rte_eth_dev *dev);
209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
214 uint16_t nb_desc, unsigned int socket_id,
215 const struct rte_eth_txconf *tx_conf);
216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
217 uint16_t nb_desc, unsigned int socket_id,
218 const struct rte_eth_rxconf *rx_conf,
219 struct rte_mempool *mp);
220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
221 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
223 static void ena_init_rings(struct ena_adapter *adapter);
224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
225 static int ena_start(struct rte_eth_dev *dev);
226 static void ena_stop(struct rte_eth_dev *dev);
227 static void ena_close(struct rte_eth_dev *dev);
228 static int ena_dev_reset(struct rte_eth_dev *dev);
229 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
230 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
231 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
232 static void ena_rx_queue_release(void *queue);
233 static void ena_tx_queue_release(void *queue);
234 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
235 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
236 static int ena_link_update(struct rte_eth_dev *dev,
237 int wait_to_complete);
238 static int ena_queue_restart(struct ena_ring *ring);
239 static int ena_queue_restart_all(struct rte_eth_dev *dev,
240 enum ena_ring_type ring_type);
241 static void ena_stats_restart(struct rte_eth_dev *dev);
242 static void ena_infos_get(struct rte_eth_dev *dev,
243 struct rte_eth_dev_info *dev_info);
244 static int ena_rss_reta_update(struct rte_eth_dev *dev,
245 struct rte_eth_rss_reta_entry64 *reta_conf,
247 static int ena_rss_reta_query(struct rte_eth_dev *dev,
248 struct rte_eth_rss_reta_entry64 *reta_conf,
250 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
251 static void ena_interrupt_handler_rte(void *cb_arg);
252 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
254 static const struct eth_dev_ops ena_dev_ops = {
255 .dev_configure = ena_dev_configure,
256 .dev_infos_get = ena_infos_get,
257 .rx_queue_setup = ena_rx_queue_setup,
258 .tx_queue_setup = ena_tx_queue_setup,
259 .dev_start = ena_start,
260 .dev_stop = ena_stop,
261 .link_update = ena_link_update,
262 .stats_get = ena_stats_get,
263 .mtu_set = ena_mtu_set,
264 .rx_queue_release = ena_rx_queue_release,
265 .tx_queue_release = ena_tx_queue_release,
266 .dev_close = ena_close,
267 .dev_reset = ena_dev_reset,
268 .reta_update = ena_rss_reta_update,
269 .reta_query = ena_rss_reta_query,
272 #define NUMA_NO_NODE SOCKET_ID_ANY
274 static inline int ena_cpu_to_node(int cpu)
276 struct rte_config *config = rte_eal_get_configuration();
277 struct rte_fbarray *arr = &config->mem_config->memzones;
278 const struct rte_memzone *mz;
280 if (unlikely(cpu >= RTE_MAX_MEMZONE))
283 mz = rte_fbarray_get(arr, cpu);
285 return mz->socket_id;
288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
289 struct ena_com_rx_ctx *ena_rx_ctx)
291 uint64_t ol_flags = 0;
292 uint32_t packet_type = 0;
294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
295 packet_type |= RTE_PTYPE_L4_TCP;
296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
297 packet_type |= RTE_PTYPE_L4_UDP;
299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
300 packet_type |= RTE_PTYPE_L3_IPV4;
301 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
302 packet_type |= RTE_PTYPE_L3_IPV6;
304 if (unlikely(ena_rx_ctx->l4_csum_err))
305 ol_flags |= PKT_RX_L4_CKSUM_BAD;
306 if (unlikely(ena_rx_ctx->l3_csum_err))
307 ol_flags |= PKT_RX_IP_CKSUM_BAD;
309 mbuf->ol_flags = ol_flags;
310 mbuf->packet_type = packet_type;
313 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
314 struct ena_com_tx_ctx *ena_tx_ctx,
315 uint64_t queue_offloads)
317 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
319 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
320 (queue_offloads & QUEUE_OFFLOADS)) {
321 /* check if TSO is required */
322 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
323 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
324 ena_tx_ctx->tso_enable = true;
326 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
329 /* check if L3 checksum is needed */
330 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
331 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
332 ena_tx_ctx->l3_csum_enable = true;
334 if (mbuf->ol_flags & PKT_TX_IPV6) {
335 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
337 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
339 /* set don't fragment (DF) flag */
340 if (mbuf->packet_type &
341 (RTE_PTYPE_L4_NONFRAG
342 | RTE_PTYPE_INNER_L4_NONFRAG))
343 ena_tx_ctx->df = true;
346 /* check if L4 checksum is needed */
347 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
348 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
349 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
350 ena_tx_ctx->l4_csum_enable = true;
351 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
352 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
353 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
354 ena_tx_ctx->l4_csum_enable = true;
356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
357 ena_tx_ctx->l4_csum_enable = false;
360 ena_meta->mss = mbuf->tso_segsz;
361 ena_meta->l3_hdr_len = mbuf->l3_len;
362 ena_meta->l3_hdr_offset = mbuf->l2_len;
364 ena_tx_ctx->meta_valid = true;
366 ena_tx_ctx->meta_valid = false;
370 static void ena_config_host_info(struct ena_com_dev *ena_dev)
372 struct ena_admin_host_info *host_info;
375 /* Allocate only the host info */
376 rc = ena_com_allocate_host_info(ena_dev);
378 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
382 host_info = ena_dev->host_attr.host_info;
384 host_info->os_type = ENA_ADMIN_OS_DPDK;
385 host_info->kernel_ver = RTE_VERSION;
386 snprintf((char *)host_info->kernel_ver_str,
387 sizeof(host_info->kernel_ver_str),
388 "%s", rte_version());
389 host_info->os_dist = RTE_VERSION;
390 snprintf((char *)host_info->os_dist_str,
391 sizeof(host_info->os_dist_str),
392 "%s", rte_version());
393 host_info->driver_version =
394 (DRV_MODULE_VER_MAJOR) |
395 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
396 (DRV_MODULE_VER_SUBMINOR <<
397 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
399 rc = ena_com_set_host_attributes(ena_dev);
401 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
402 if (rc != -ENA_COM_UNSUPPORTED)
409 ena_com_delete_host_info(ena_dev);
413 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
415 if (sset != ETH_SS_STATS)
418 /* Workaround for clang:
419 * touch internal structures to prevent
422 ENA_TOUCH(ena_stats_global_strings);
423 ENA_TOUCH(ena_stats_tx_strings);
424 ENA_TOUCH(ena_stats_rx_strings);
425 ENA_TOUCH(ena_stats_ena_com_strings);
427 return dev->data->nb_tx_queues *
428 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
429 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
432 static void ena_config_debug_area(struct ena_adapter *adapter)
437 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
439 RTE_LOG(ERR, PMD, "SS count is negative\n");
443 /* allocate 32 bytes for each string and 64bit for the value */
444 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
446 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
448 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
452 rc = ena_com_set_host_attributes(&adapter->ena_dev);
454 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
455 if (rc != -ENA_COM_UNSUPPORTED)
461 ena_com_delete_debug_area(&adapter->ena_dev);
464 static void ena_close(struct rte_eth_dev *dev)
466 struct ena_adapter *adapter =
467 (struct ena_adapter *)(dev->data->dev_private);
470 adapter->state = ENA_ADAPTER_STATE_CLOSED;
472 ena_rx_queue_release_all(dev);
473 ena_tx_queue_release_all(dev);
477 ena_dev_reset(struct rte_eth_dev *dev)
479 struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
480 struct rte_eth_dev *eth_dev;
481 struct rte_pci_device *pci_dev;
482 struct rte_intr_handle *intr_handle;
483 struct ena_com_dev *ena_dev;
484 struct ena_com_dev_get_features_ctx get_feat_ctx;
485 struct ena_adapter *adapter;
489 adapter = (struct ena_adapter *)(dev->data->dev_private);
490 ena_dev = &adapter->ena_dev;
491 eth_dev = adapter->rte_dev;
492 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
493 intr_handle = &pci_dev->intr_handle;
494 nb_queues = eth_dev->data->nb_rx_queues;
496 ena_com_set_admin_running_state(ena_dev, false);
498 ena_com_dev_reset(ena_dev, adapter->reset_reason);
500 for (i = 0; i < nb_queues; i++)
501 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
503 ena_rx_queue_release_all(eth_dev);
504 ena_tx_queue_release_all(eth_dev);
506 rte_intr_disable(intr_handle);
508 ena_com_abort_admin_commands(ena_dev);
509 ena_com_wait_for_abort_completion(ena_dev);
510 ena_com_admin_destroy(ena_dev);
511 ena_com_mmio_reg_read_request_destroy(ena_dev);
513 rc = ena_device_init(ena_dev, &get_feat_ctx);
515 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
519 rte_intr_enable(intr_handle);
520 ena_com_set_admin_polling_mode(ena_dev, false);
521 ena_com_admin_aenq_enable(ena_dev);
523 for (i = 0; i < nb_queues; ++i)
524 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
527 for (i = 0; i < nb_queues; ++i)
528 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
530 adapter->trigger_reset = false;
535 static int ena_rss_reta_update(struct rte_eth_dev *dev,
536 struct rte_eth_rss_reta_entry64 *reta_conf,
539 struct ena_adapter *adapter =
540 (struct ena_adapter *)(dev->data->dev_private);
541 struct ena_com_dev *ena_dev = &adapter->ena_dev;
547 if ((reta_size == 0) || (reta_conf == NULL))
550 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
551 RTE_LOG(WARNING, PMD,
552 "indirection table %d is bigger than supported (%d)\n",
553 reta_size, ENA_RX_RSS_TABLE_SIZE);
558 for (i = 0 ; i < reta_size ; i++) {
559 /* each reta_conf is for 64 entries.
560 * to support 128 we use 2 conf of 64
562 conf_idx = i / RTE_RETA_GROUP_SIZE;
563 idx = i % RTE_RETA_GROUP_SIZE;
564 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
566 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
567 ret = ena_com_indirect_table_fill_entry(ena_dev,
570 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
572 "Cannot fill indirect table\n");
579 ret = ena_com_indirect_table_set(ena_dev);
580 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
581 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
586 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
587 __func__, reta_size, adapter->rte_dev->data->port_id);
592 /* Query redirection table. */
593 static int ena_rss_reta_query(struct rte_eth_dev *dev,
594 struct rte_eth_rss_reta_entry64 *reta_conf,
597 struct ena_adapter *adapter =
598 (struct ena_adapter *)(dev->data->dev_private);
599 struct ena_com_dev *ena_dev = &adapter->ena_dev;
602 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
606 if (reta_size == 0 || reta_conf == NULL ||
607 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
610 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
611 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
612 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
617 for (i = 0 ; i < reta_size ; i++) {
618 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
619 reta_idx = i % RTE_RETA_GROUP_SIZE;
620 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
621 reta_conf[reta_conf_idx].reta[reta_idx] =
622 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
628 static int ena_rss_init_default(struct ena_adapter *adapter)
630 struct ena_com_dev *ena_dev = &adapter->ena_dev;
631 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
635 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
637 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
641 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
642 val = i % nb_rx_queues;
643 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
644 ENA_IO_RXQ_IDX(val));
645 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
646 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
651 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
652 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
653 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
654 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
658 rc = ena_com_set_default_hash_ctrl(ena_dev);
659 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
660 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
664 rc = ena_com_indirect_table_set(ena_dev);
665 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
666 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
669 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
670 adapter->rte_dev->data->port_id);
675 ena_com_rss_destroy(ena_dev);
681 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
683 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
684 int nb_queues = dev->data->nb_rx_queues;
687 for (i = 0; i < nb_queues; i++)
688 ena_rx_queue_release(queues[i]);
691 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
693 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
694 int nb_queues = dev->data->nb_tx_queues;
697 for (i = 0; i < nb_queues; i++)
698 ena_tx_queue_release(queues[i]);
701 static void ena_rx_queue_release(void *queue)
703 struct ena_ring *ring = (struct ena_ring *)queue;
704 struct ena_adapter *adapter = ring->adapter;
707 ena_assert_msg(ring->configured,
708 "API violation - releasing not configured queue");
709 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
712 /* Destroy HW queue */
713 ena_qid = ENA_IO_RXQ_IDX(ring->id);
714 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
717 ena_rx_queue_release_bufs(ring);
719 /* Free ring resources */
720 if (ring->rx_buffer_info)
721 rte_free(ring->rx_buffer_info);
722 ring->rx_buffer_info = NULL;
724 ring->configured = 0;
726 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
727 ring->port_id, ring->id);
730 static void ena_tx_queue_release(void *queue)
732 struct ena_ring *ring = (struct ena_ring *)queue;
733 struct ena_adapter *adapter = ring->adapter;
736 ena_assert_msg(ring->configured,
737 "API violation. Releasing not configured queue");
738 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
741 /* Destroy HW queue */
742 ena_qid = ENA_IO_TXQ_IDX(ring->id);
743 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
746 ena_tx_queue_release_bufs(ring);
748 /* Free ring resources */
749 if (ring->tx_buffer_info)
750 rte_free(ring->tx_buffer_info);
752 if (ring->empty_tx_reqs)
753 rte_free(ring->empty_tx_reqs);
755 ring->empty_tx_reqs = NULL;
756 ring->tx_buffer_info = NULL;
758 ring->configured = 0;
760 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
761 ring->port_id, ring->id);
764 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
766 unsigned int ring_mask = ring->ring_size - 1;
768 while (ring->next_to_clean != ring->next_to_use) {
770 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
773 rte_mbuf_raw_free(m);
775 ring->next_to_clean++;
779 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
783 for (i = 0; i < ring->ring_size; ++i) {
784 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
787 rte_pktmbuf_free(tx_buf->mbuf);
789 ring->next_to_clean++;
793 static int ena_link_update(struct rte_eth_dev *dev,
794 __rte_unused int wait_to_complete)
796 struct rte_eth_link *link = &dev->data->dev_link;
797 struct ena_adapter *adapter;
799 adapter = (struct ena_adapter *)(dev->data->dev_private);
801 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
802 link->link_speed = ETH_SPEED_NUM_10G;
803 link->link_duplex = ETH_LINK_FULL_DUPLEX;
808 static int ena_queue_restart_all(struct rte_eth_dev *dev,
809 enum ena_ring_type ring_type)
811 struct ena_adapter *adapter =
812 (struct ena_adapter *)(dev->data->dev_private);
813 struct ena_ring *queues = NULL;
818 if (ring_type == ENA_RING_TYPE_RX) {
819 queues = adapter->rx_ring;
820 nb_queues = dev->data->nb_rx_queues;
822 queues = adapter->tx_ring;
823 nb_queues = dev->data->nb_tx_queues;
825 for (i = 0; i < nb_queues; i++) {
826 if (queues[i].configured) {
827 if (ring_type == ENA_RING_TYPE_RX) {
829 dev->data->rx_queues[i] == &queues[i],
830 "Inconsistent state of rx queues\n");
833 dev->data->tx_queues[i] == &queues[i],
834 "Inconsistent state of tx queues\n");
837 rc = ena_queue_restart(&queues[i]);
841 "failed to restart queue %d type(%d)",
851 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
853 uint32_t max_frame_len = adapter->max_mtu;
855 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
856 DEV_RX_OFFLOAD_JUMBO_FRAME)
858 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
860 return max_frame_len;
863 static int ena_check_valid_conf(struct ena_adapter *adapter)
865 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
867 if (max_frame_len > adapter->max_mtu) {
868 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
876 ena_calc_queue_size(struct ena_com_dev *ena_dev,
877 struct ena_com_dev_get_features_ctx *get_feat_ctx)
879 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
881 queue_size = RTE_MIN(queue_size,
882 get_feat_ctx->max_queues.max_cq_depth);
883 queue_size = RTE_MIN(queue_size,
884 get_feat_ctx->max_queues.max_sq_depth);
886 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
887 queue_size = RTE_MIN(queue_size,
888 get_feat_ctx->max_queues.max_llq_depth);
890 /* Round down to power of 2 */
891 if (!rte_is_power_of_2(queue_size))
892 queue_size = rte_align32pow2(queue_size >> 1);
894 if (queue_size == 0) {
895 PMD_INIT_LOG(ERR, "Invalid queue size");
902 static void ena_stats_restart(struct rte_eth_dev *dev)
904 struct ena_adapter *adapter =
905 (struct ena_adapter *)(dev->data->dev_private);
907 rte_atomic64_init(&adapter->drv_stats->ierrors);
908 rte_atomic64_init(&adapter->drv_stats->oerrors);
909 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
912 static int ena_stats_get(struct rte_eth_dev *dev,
913 struct rte_eth_stats *stats)
915 struct ena_admin_basic_stats ena_stats;
916 struct ena_adapter *adapter =
917 (struct ena_adapter *)(dev->data->dev_private);
918 struct ena_com_dev *ena_dev = &adapter->ena_dev;
921 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
924 memset(&ena_stats, 0, sizeof(ena_stats));
925 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
927 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
931 /* Set of basic statistics from ENA */
932 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
933 ena_stats.rx_pkts_low);
934 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
935 ena_stats.tx_pkts_low);
936 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
937 ena_stats.rx_bytes_low);
938 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
939 ena_stats.tx_bytes_low);
940 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
941 ena_stats.rx_drops_low);
943 /* Driver related stats */
944 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
945 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
946 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
950 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
952 struct ena_adapter *adapter;
953 struct ena_com_dev *ena_dev;
956 ena_assert_msg(dev->data != NULL, "Uninitialized device");
957 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
958 adapter = (struct ena_adapter *)(dev->data->dev_private);
960 ena_dev = &adapter->ena_dev;
961 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
963 if (mtu > ena_get_mtu_conf(adapter)) {
965 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
966 mtu, ena_get_mtu_conf(adapter));
971 rc = ena_com_set_dev_mtu(ena_dev, mtu);
973 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
975 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
981 static int ena_start(struct rte_eth_dev *dev)
983 struct ena_adapter *adapter =
984 (struct ena_adapter *)(dev->data->dev_private);
988 rc = ena_check_valid_conf(adapter);
992 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
996 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1000 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1001 ETH_MQ_RX_RSS_FLAG) {
1002 rc = ena_rss_init_default(adapter);
1007 ena_stats_restart(dev);
1009 adapter->timestamp_wd = rte_get_timer_cycles();
1010 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1012 ticks = rte_get_timer_hz();
1013 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1014 ena_timer_wd_callback, adapter);
1016 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1021 static void ena_stop(struct rte_eth_dev *dev)
1023 struct ena_adapter *adapter =
1024 (struct ena_adapter *)(dev->data->dev_private);
1026 rte_timer_stop_sync(&adapter->timer_wd);
1028 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1031 static int ena_queue_restart(struct ena_ring *ring)
1035 ena_assert_msg(ring->configured == 1,
1036 "Trying to restart unconfigured queue\n");
1038 ring->next_to_clean = 0;
1039 ring->next_to_use = 0;
1041 if (ring->type == ENA_RING_TYPE_TX)
1044 bufs_num = ring->ring_size - 1;
1045 rc = ena_populate_rx_queue(ring, bufs_num);
1046 if (rc != bufs_num) {
1047 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1054 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1057 __rte_unused unsigned int socket_id,
1058 const struct rte_eth_txconf *tx_conf)
1060 struct ena_com_create_io_ctx ctx =
1061 /* policy set to _HOST just to satisfy icc compiler */
1062 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1063 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1064 struct ena_ring *txq = NULL;
1065 struct ena_adapter *adapter =
1066 (struct ena_adapter *)(dev->data->dev_private);
1070 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1072 txq = &adapter->tx_ring[queue_idx];
1074 if (txq->configured) {
1076 "API violation. Queue %d is already configured\n",
1081 if (!rte_is_power_of_2(nb_desc)) {
1083 "Unsupported size of RX queue: %d is not a power of 2.",
1088 if (nb_desc > adapter->tx_ring_size) {
1090 "Unsupported size of TX queue (max size: %d)\n",
1091 adapter->tx_ring_size);
1095 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1097 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1099 ctx.msix_vector = -1; /* admin interrupts not used */
1100 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1101 ctx.queue_size = adapter->tx_ring_size;
1102 ctx.numa_node = ena_cpu_to_node(queue_idx);
1104 rc = ena_com_create_io_queue(ena_dev, &ctx);
1107 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1108 queue_idx, ena_qid, rc);
1110 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1111 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1113 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1114 &txq->ena_com_io_sq,
1115 &txq->ena_com_io_cq);
1118 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1120 ena_com_destroy_io_queue(ena_dev, ena_qid);
1124 txq->port_id = dev->data->port_id;
1125 txq->next_to_clean = 0;
1126 txq->next_to_use = 0;
1127 txq->ring_size = nb_desc;
1129 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1130 sizeof(struct ena_tx_buffer) *
1132 RTE_CACHE_LINE_SIZE);
1133 if (!txq->tx_buffer_info) {
1134 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1138 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1139 sizeof(u16) * txq->ring_size,
1140 RTE_CACHE_LINE_SIZE);
1141 if (!txq->empty_tx_reqs) {
1142 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1143 rte_free(txq->tx_buffer_info);
1146 for (i = 0; i < txq->ring_size; i++)
1147 txq->empty_tx_reqs[i] = i;
1149 if (tx_conf != NULL) {
1151 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1154 /* Store pointer to this queue in upper layer */
1155 txq->configured = 1;
1156 dev->data->tx_queues[queue_idx] = txq;
1161 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1164 __rte_unused unsigned int socket_id,
1165 __rte_unused const struct rte_eth_rxconf *rx_conf,
1166 struct rte_mempool *mp)
1168 struct ena_com_create_io_ctx ctx =
1169 /* policy set to _HOST just to satisfy icc compiler */
1170 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1171 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1172 struct ena_adapter *adapter =
1173 (struct ena_adapter *)(dev->data->dev_private);
1174 struct ena_ring *rxq = NULL;
1175 uint16_t ena_qid = 0;
1177 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1179 rxq = &adapter->rx_ring[queue_idx];
1180 if (rxq->configured) {
1182 "API violation. Queue %d is already configured\n",
1187 if (!rte_is_power_of_2(nb_desc)) {
1189 "Unsupported size of TX queue: %d is not a power of 2.",
1194 if (nb_desc > adapter->rx_ring_size) {
1196 "Unsupported size of RX queue (max size: %d)\n",
1197 adapter->rx_ring_size);
1201 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1204 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1205 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1206 ctx.msix_vector = -1; /* admin interrupts not used */
1207 ctx.queue_size = adapter->rx_ring_size;
1208 ctx.numa_node = ena_cpu_to_node(queue_idx);
1210 rc = ena_com_create_io_queue(ena_dev, &ctx);
1212 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1215 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1216 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1218 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1219 &rxq->ena_com_io_sq,
1220 &rxq->ena_com_io_cq);
1223 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1225 ena_com_destroy_io_queue(ena_dev, ena_qid);
1228 rxq->port_id = dev->data->port_id;
1229 rxq->next_to_clean = 0;
1230 rxq->next_to_use = 0;
1231 rxq->ring_size = nb_desc;
1234 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1235 sizeof(struct rte_mbuf *) * nb_desc,
1236 RTE_CACHE_LINE_SIZE);
1237 if (!rxq->rx_buffer_info) {
1238 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1242 /* Store pointer to this queue in upper layer */
1243 rxq->configured = 1;
1244 dev->data->rx_queues[queue_idx] = rxq;
1249 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1253 uint16_t ring_size = rxq->ring_size;
1254 uint16_t ring_mask = ring_size - 1;
1255 uint16_t next_to_use = rxq->next_to_use;
1257 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1259 if (unlikely(!count))
1262 in_use = rxq->next_to_use - rxq->next_to_clean;
1263 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1265 count = RTE_MIN(count,
1266 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1268 /* get resources for incoming packets */
1269 rc = rte_mempool_get_bulk(rxq->mb_pool,
1270 (void **)(&mbufs[next_to_use & ring_mask]),
1272 if (unlikely(rc < 0)) {
1273 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1274 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1278 for (i = 0; i < count; i++) {
1279 uint16_t next_to_use_masked = next_to_use & ring_mask;
1280 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1281 struct ena_com_buf ebuf;
1283 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1284 /* prepare physical address for DMA transaction */
1285 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1286 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1287 /* pass resource to device */
1288 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1289 &ebuf, next_to_use_masked);
1291 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1293 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1299 /* When we submitted free recources to device... */
1301 /* ...let HW know that it can fill buffers with data */
1303 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1305 rxq->next_to_use = next_to_use;
1311 static int ena_device_init(struct ena_com_dev *ena_dev,
1312 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1314 uint32_t aenq_groups;
1316 bool readless_supported;
1318 /* Initialize mmio registers */
1319 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1321 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1325 /* The PCIe configuration space revision id indicate if mmio reg
1328 readless_supported =
1329 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1330 & ENA_MMIO_DISABLE_REG_READ);
1331 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1334 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1336 RTE_LOG(ERR, PMD, "cannot reset device\n");
1337 goto err_mmio_read_less;
1340 /* check FW version */
1341 rc = ena_com_validate_version(ena_dev);
1343 RTE_LOG(ERR, PMD, "device version is too low\n");
1344 goto err_mmio_read_less;
1347 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1349 /* ENA device administration layer init */
1350 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1353 "cannot initialize ena admin queue with device\n");
1354 goto err_mmio_read_less;
1357 /* To enable the msix interrupts the driver needs to know the number
1358 * of queues. So the driver uses polling mode to retrieve this
1361 ena_com_set_admin_polling_mode(ena_dev, true);
1363 ena_config_host_info(ena_dev);
1365 /* Get Device Attributes and features */
1366 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1369 "cannot get attribute for ena device rc= %d\n", rc);
1370 goto err_admin_init;
1373 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1374 BIT(ENA_ADMIN_NOTIFICATION) |
1375 BIT(ENA_ADMIN_KEEP_ALIVE);
1377 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1378 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1380 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1381 goto err_admin_init;
1387 ena_com_admin_destroy(ena_dev);
1390 ena_com_mmio_reg_read_request_destroy(ena_dev);
1395 static void ena_interrupt_handler_rte(void *cb_arg)
1397 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1398 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1400 ena_com_admin_q_comp_intr_handler(ena_dev);
1401 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1402 ena_com_aenq_intr_handler(ena_dev, adapter);
1405 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1407 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1410 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1411 adapter->keep_alive_timeout)) {
1412 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1413 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1414 adapter->trigger_reset = true;
1418 /* Check if admin queue is enabled */
1419 static void check_for_admin_com_state(struct ena_adapter *adapter)
1421 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1422 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1423 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1424 adapter->trigger_reset = true;
1428 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1431 struct ena_adapter *adapter = (struct ena_adapter *)arg;
1432 struct rte_eth_dev *dev = adapter->rte_dev;
1434 check_for_missing_keep_alive(adapter);
1435 check_for_admin_com_state(adapter);
1437 if (unlikely(adapter->trigger_reset)) {
1438 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1439 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1444 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1446 struct rte_pci_device *pci_dev;
1447 struct rte_intr_handle *intr_handle;
1448 struct ena_adapter *adapter =
1449 (struct ena_adapter *)(eth_dev->data->dev_private);
1450 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1451 struct ena_com_dev_get_features_ctx get_feat_ctx;
1454 static int adapters_found;
1456 memset(adapter, 0, sizeof(struct ena_adapter));
1457 ena_dev = &adapter->ena_dev;
1459 eth_dev->dev_ops = &ena_dev_ops;
1460 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1461 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1462 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1463 adapter->rte_eth_dev_data = eth_dev->data;
1464 adapter->rte_dev = eth_dev;
1466 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1469 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1470 adapter->pdev = pci_dev;
1472 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1473 pci_dev->addr.domain,
1475 pci_dev->addr.devid,
1476 pci_dev->addr.function);
1478 intr_handle = &pci_dev->intr_handle;
1480 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1481 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1483 if (!adapter->regs) {
1484 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1489 ena_dev->reg_bar = adapter->regs;
1490 ena_dev->dmadev = adapter->pdev;
1492 adapter->id_number = adapters_found;
1494 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1495 adapter->id_number);
1497 /* device specific initialization routine */
1498 rc = ena_device_init(ena_dev, &get_feat_ctx);
1500 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1504 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1505 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1507 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1508 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1511 adapter->tx_ring_size = queue_size;
1512 adapter->rx_ring_size = queue_size;
1514 /* prepare ring structures */
1515 ena_init_rings(adapter);
1517 ena_config_debug_area(adapter);
1519 /* Set max MTU for this device */
1520 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1522 /* set device support for TSO */
1523 adapter->tso4_supported = get_feat_ctx.offload.tx &
1524 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1526 /* Copy MAC address and point DPDK to it */
1527 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1528 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1529 (struct ether_addr *)adapter->mac_addr);
1531 adapter->drv_stats = rte_zmalloc("adapter stats",
1532 sizeof(*adapter->drv_stats),
1533 RTE_CACHE_LINE_SIZE);
1534 if (!adapter->drv_stats) {
1535 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1539 rte_intr_callback_register(intr_handle,
1540 ena_interrupt_handler_rte,
1542 rte_intr_enable(intr_handle);
1543 ena_com_set_admin_polling_mode(ena_dev, false);
1544 ena_com_admin_aenq_enable(ena_dev);
1546 if (adapters_found == 0)
1547 rte_timer_subsystem_init();
1548 rte_timer_init(&adapter->timer_wd);
1551 adapter->state = ENA_ADAPTER_STATE_INIT;
1556 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1558 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1559 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560 struct ena_adapter *adapter =
1561 (struct ena_adapter *)(eth_dev->data->dev_private);
1563 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1566 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1569 eth_dev->dev_ops = NULL;
1570 eth_dev->rx_pkt_burst = NULL;
1571 eth_dev->tx_pkt_burst = NULL;
1572 eth_dev->tx_pkt_prepare = NULL;
1574 rte_free(adapter->drv_stats);
1575 adapter->drv_stats = NULL;
1577 rte_intr_disable(intr_handle);
1578 rte_intr_callback_unregister(intr_handle,
1579 ena_interrupt_handler_rte,
1582 adapter->state = ENA_ADAPTER_STATE_FREE;
1587 static int ena_dev_configure(struct rte_eth_dev *dev)
1589 struct ena_adapter *adapter =
1590 (struct ena_adapter *)(dev->data->dev_private);
1592 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1594 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1595 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1599 static void ena_init_rings(struct ena_adapter *adapter)
1603 for (i = 0; i < adapter->num_queues; i++) {
1604 struct ena_ring *ring = &adapter->tx_ring[i];
1606 ring->configured = 0;
1607 ring->type = ENA_RING_TYPE_TX;
1608 ring->adapter = adapter;
1610 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1611 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1614 for (i = 0; i < adapter->num_queues; i++) {
1615 struct ena_ring *ring = &adapter->rx_ring[i];
1617 ring->configured = 0;
1618 ring->type = ENA_RING_TYPE_RX;
1619 ring->adapter = adapter;
1624 static void ena_infos_get(struct rte_eth_dev *dev,
1625 struct rte_eth_dev_info *dev_info)
1627 struct ena_adapter *adapter;
1628 struct ena_com_dev *ena_dev;
1629 struct ena_com_dev_get_features_ctx feat;
1630 uint64_t rx_feat = 0, tx_feat = 0;
1633 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1634 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1635 adapter = (struct ena_adapter *)(dev->data->dev_private);
1637 ena_dev = &adapter->ena_dev;
1638 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1640 dev_info->speed_capa =
1642 ETH_LINK_SPEED_2_5G |
1644 ETH_LINK_SPEED_10G |
1645 ETH_LINK_SPEED_25G |
1646 ETH_LINK_SPEED_40G |
1647 ETH_LINK_SPEED_50G |
1648 ETH_LINK_SPEED_100G;
1650 /* Get supported features from HW */
1651 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1654 "Cannot get attribute for ena device rc= %d\n", rc);
1658 /* Set Tx & Rx features available for device */
1659 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1660 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1662 if (feat.offload.tx &
1663 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1664 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1665 DEV_TX_OFFLOAD_UDP_CKSUM |
1666 DEV_TX_OFFLOAD_TCP_CKSUM;
1668 if (feat.offload.rx_supported &
1669 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1670 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1671 DEV_RX_OFFLOAD_UDP_CKSUM |
1672 DEV_RX_OFFLOAD_TCP_CKSUM;
1674 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1676 /* Inform framework about available features */
1677 dev_info->rx_offload_capa = rx_feat;
1678 dev_info->rx_queue_offload_capa = rx_feat;
1679 dev_info->tx_offload_capa = tx_feat;
1680 dev_info->tx_queue_offload_capa = tx_feat;
1682 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1683 dev_info->max_rx_pktlen = adapter->max_mtu;
1684 dev_info->max_mac_addrs = 1;
1686 dev_info->max_rx_queues = adapter->num_queues;
1687 dev_info->max_tx_queues = adapter->num_queues;
1688 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1690 adapter->tx_supported_offloads = tx_feat;
1691 adapter->rx_supported_offloads = rx_feat;
1694 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1697 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1698 unsigned int ring_size = rx_ring->ring_size;
1699 unsigned int ring_mask = ring_size - 1;
1700 uint16_t next_to_clean = rx_ring->next_to_clean;
1701 uint16_t desc_in_use = 0;
1702 unsigned int recv_idx = 0;
1703 struct rte_mbuf *mbuf = NULL;
1704 struct rte_mbuf *mbuf_head = NULL;
1705 struct rte_mbuf *mbuf_prev = NULL;
1706 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1707 unsigned int completed;
1709 struct ena_com_rx_ctx ena_rx_ctx;
1712 /* Check adapter state */
1713 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1715 "Trying to receive pkts while device is NOT running\n");
1719 desc_in_use = rx_ring->next_to_use - next_to_clean;
1720 if (unlikely(nb_pkts > desc_in_use))
1721 nb_pkts = desc_in_use;
1723 for (completed = 0; completed < nb_pkts; completed++) {
1726 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1727 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1728 ena_rx_ctx.descs = 0;
1729 /* receive packet context */
1730 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1731 rx_ring->ena_com_io_sq,
1734 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1738 if (unlikely(ena_rx_ctx.descs == 0))
1741 while (segments < ena_rx_ctx.descs) {
1742 mbuf = rx_buff_info[next_to_clean & ring_mask];
1743 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1744 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1747 if (segments == 0) {
1748 mbuf->nb_segs = ena_rx_ctx.descs;
1749 mbuf->port = rx_ring->port_id;
1753 /* for multi-segment pkts create mbuf chain */
1754 mbuf_prev->next = mbuf;
1756 mbuf_head->pkt_len += mbuf->data_len;
1763 /* fill mbuf attributes if any */
1764 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1765 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1767 /* pass to DPDK application head mbuf */
1768 rx_pkts[recv_idx] = mbuf_head;
1772 rx_ring->next_to_clean = next_to_clean;
1774 desc_in_use = desc_in_use - completed + 1;
1775 /* Burst refill to save doorbells, memory barriers, const interval */
1776 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1777 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1783 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1789 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1790 struct ipv4_hdr *ip_hdr;
1792 uint16_t frag_field;
1794 for (i = 0; i != nb_pkts; i++) {
1796 ol_flags = m->ol_flags;
1798 if (!(ol_flags & PKT_TX_IPV4))
1801 /* If there was not L2 header length specified, assume it is
1802 * length of the ethernet header.
1804 if (unlikely(m->l2_len == 0))
1805 m->l2_len = sizeof(struct ether_hdr);
1807 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1809 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1811 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1812 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1814 /* If IPv4 header has DF flag enabled and TSO support is
1815 * disabled, partial chcecksum should not be calculated.
1817 if (!tx_ring->adapter->tso4_supported)
1821 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1822 (ol_flags & PKT_TX_L4_MASK) ==
1823 PKT_TX_SCTP_CKSUM) {
1824 rte_errno = -ENOTSUP;
1828 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1829 ret = rte_validate_tx_offload(m);
1836 /* In case we are supposed to TSO and have DF not set (DF=0)
1837 * hardware must be provided with partial checksum, otherwise
1838 * it will take care of necessary calculations.
1841 ret = rte_net_intel_cksum_flags_prepare(m,
1842 ol_flags & ~PKT_TX_TCP_SEG);
1852 static void ena_update_hints(struct ena_adapter *adapter,
1853 struct ena_admin_ena_hw_hints *hints)
1855 if (hints->admin_completion_tx_timeout)
1856 adapter->ena_dev.admin_queue.completion_timeout =
1857 hints->admin_completion_tx_timeout * 1000;
1859 if (hints->mmio_read_timeout)
1860 /* convert to usec */
1861 adapter->ena_dev.mmio_read.reg_read_to =
1862 hints->mmio_read_timeout * 1000;
1864 if (hints->driver_watchdog_timeout) {
1865 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1866 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1868 // Convert msecs to ticks
1869 adapter->keep_alive_timeout =
1870 (hints->driver_watchdog_timeout *
1871 rte_get_timer_hz()) / 1000;
1875 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1878 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1879 uint16_t next_to_use = tx_ring->next_to_use;
1880 uint16_t next_to_clean = tx_ring->next_to_clean;
1881 struct rte_mbuf *mbuf;
1882 unsigned int ring_size = tx_ring->ring_size;
1883 unsigned int ring_mask = ring_size - 1;
1884 struct ena_com_tx_ctx ena_tx_ctx;
1885 struct ena_tx_buffer *tx_info;
1886 struct ena_com_buf *ebuf;
1887 uint16_t rc, req_id, total_tx_descs = 0;
1888 uint16_t sent_idx = 0, empty_tx_reqs;
1891 /* Check adapter state */
1892 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1894 "Trying to xmit pkts while device is NOT running\n");
1898 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1899 if (nb_pkts > empty_tx_reqs)
1900 nb_pkts = empty_tx_reqs;
1902 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1903 mbuf = tx_pkts[sent_idx];
1905 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1906 tx_info = &tx_ring->tx_buffer_info[req_id];
1907 tx_info->mbuf = mbuf;
1908 tx_info->num_of_bufs = 0;
1909 ebuf = tx_info->bufs;
1911 /* Prepare TX context */
1912 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1913 memset(&ena_tx_ctx.ena_meta, 0x0,
1914 sizeof(struct ena_com_tx_meta));
1915 ena_tx_ctx.ena_bufs = ebuf;
1916 ena_tx_ctx.req_id = req_id;
1917 if (tx_ring->tx_mem_queue_type ==
1918 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1919 /* prepare the push buffer with
1920 * virtual address of the data
1922 ena_tx_ctx.header_len =
1923 RTE_MIN(mbuf->data_len,
1924 tx_ring->tx_max_header_size);
1925 ena_tx_ctx.push_header =
1926 (void *)((char *)mbuf->buf_addr +
1928 } /* there's no else as we take advantage of memset zeroing */
1930 /* Set TX offloads flags, if applicable */
1931 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1933 if (unlikely(mbuf->ol_flags &
1934 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1935 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1937 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1939 /* Process first segment taking into
1940 * consideration pushed header
1942 if (mbuf->data_len > ena_tx_ctx.header_len) {
1943 ebuf->paddr = mbuf->buf_iova +
1945 ena_tx_ctx.header_len;
1946 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1948 tx_info->num_of_bufs++;
1951 while ((mbuf = mbuf->next) != NULL) {
1952 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1953 ebuf->len = mbuf->data_len;
1955 tx_info->num_of_bufs++;
1958 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1960 /* Write data to device */
1961 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1962 &ena_tx_ctx, &nb_hw_desc);
1966 tx_info->tx_descs = nb_hw_desc;
1971 /* If there are ready packets to be xmitted... */
1973 /* ...let HW do its best :-) */
1975 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1977 tx_ring->next_to_use = next_to_use;
1980 /* Clear complete packets */
1981 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1982 /* Get Tx info & store how many descs were processed */
1983 tx_info = &tx_ring->tx_buffer_info[req_id];
1984 total_tx_descs += tx_info->tx_descs;
1986 /* Free whole mbuf chain */
1987 mbuf = tx_info->mbuf;
1988 rte_pktmbuf_free(mbuf);
1989 tx_info->mbuf = NULL;
1991 /* Put back descriptor to the ring for reuse */
1992 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1995 /* If too many descs to clean, leave it for another run */
1996 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2000 if (total_tx_descs > 0) {
2001 /* acknowledge completion of sent packets */
2002 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2003 tx_ring->next_to_clean = next_to_clean;
2009 /*********************************************************************
2011 *********************************************************************/
2012 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2013 struct rte_pci_device *pci_dev)
2015 return rte_eth_dev_pci_generic_probe(pci_dev,
2016 sizeof(struct ena_adapter), eth_ena_dev_init);
2019 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2021 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2024 static struct rte_pci_driver rte_ena_pmd = {
2025 .id_table = pci_id_ena_map,
2026 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2027 .probe = eth_ena_pci_probe,
2028 .remove = eth_ena_pci_remove,
2031 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2032 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2033 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2035 RTE_INIT(ena_init_log);
2039 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2040 if (ena_logtype_init >= 0)
2041 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2042 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2043 if (ena_logtype_driver >= 0)
2044 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2047 /******************************************************************************
2048 ******************************** AENQ Handlers *******************************
2049 *****************************************************************************/
2050 static void ena_update_on_link_change(void *adapter_data,
2051 struct ena_admin_aenq_entry *aenq_e)
2053 struct rte_eth_dev *eth_dev;
2054 struct ena_adapter *adapter;
2055 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2058 adapter = (struct ena_adapter *)adapter_data;
2059 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2060 eth_dev = adapter->rte_dev;
2062 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2063 adapter->link_status = status;
2065 ena_link_update(eth_dev, 0);
2066 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2069 static void ena_notification(void *data,
2070 struct ena_admin_aenq_entry *aenq_e)
2072 struct ena_adapter *adapter = (struct ena_adapter *)data;
2073 struct ena_admin_ena_hw_hints *hints;
2075 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2076 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2077 aenq_e->aenq_common_desc.group,
2078 ENA_ADMIN_NOTIFICATION);
2080 switch (aenq_e->aenq_common_desc.syndrom) {
2081 case ENA_ADMIN_UPDATE_HINTS:
2082 hints = (struct ena_admin_ena_hw_hints *)
2083 (&aenq_e->inline_data_w4);
2084 ena_update_hints(adapter, hints);
2087 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2088 aenq_e->aenq_common_desc.syndrom);
2092 static void ena_keep_alive(void *adapter_data,
2093 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2095 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2097 adapter->timestamp_wd = rte_get_timer_cycles();
2101 * This handler will called for unknown event group or unimplemented handlers
2103 static void unimplemented_aenq_handler(__rte_unused void *data,
2104 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2106 // Unimplemented handler
2109 static struct ena_aenq_handlers aenq_handlers = {
2111 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2112 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2113 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2115 .unimplemented_handler = unimplemented_aenq_handler