1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <rte_version.h>
10 #include <rte_kvargs.h>
12 #include "ena_ethdev.h"
14 #include "ena_platform.h"
16 #include "ena_eth_com.h"
18 #include <ena_common_defs.h>
19 #include <ena_regs_defs.h>
20 #include <ena_admin_defs.h>
21 #include <ena_eth_io_defs.h>
23 #define DRV_MODULE_VER_MAJOR 2
24 #define DRV_MODULE_VER_MINOR 5
25 #define DRV_MODULE_VER_SUBMINOR 0
27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
29 #define GET_L4_HDR_LEN(mbuf) \
30 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
31 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
33 #define ETH_GSTRING_LEN 32
35 #define ARRAY_SIZE(x) RTE_DIM(x)
37 #define ENA_MIN_RING_DESC 128
39 #define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
42 char name[ETH_GSTRING_LEN];
46 #define ENA_STAT_ENTRY(stat, stat_type) { \
48 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
51 #define ENA_STAT_RX_ENTRY(stat) \
52 ENA_STAT_ENTRY(stat, rx)
54 #define ENA_STAT_TX_ENTRY(stat) \
55 ENA_STAT_ENTRY(stat, tx)
57 #define ENA_STAT_ENI_ENTRY(stat) \
58 ENA_STAT_ENTRY(stat, eni)
60 #define ENA_STAT_GLOBAL_ENTRY(stat) \
61 ENA_STAT_ENTRY(stat, dev)
63 /* Device arguments */
64 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
67 * Each rte_memzone should have unique name.
68 * To satisfy it, count number of allocation and add it to name.
70 rte_atomic64_t ena_alloc_cnt;
72 static const struct ena_stats ena_stats_global_strings[] = {
73 ENA_STAT_GLOBAL_ENTRY(wd_expired),
74 ENA_STAT_GLOBAL_ENTRY(dev_start),
75 ENA_STAT_GLOBAL_ENTRY(dev_stop),
76 ENA_STAT_GLOBAL_ENTRY(tx_drops),
79 static const struct ena_stats ena_stats_eni_strings[] = {
80 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
81 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
82 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
83 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
84 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
87 static const struct ena_stats ena_stats_tx_strings[] = {
88 ENA_STAT_TX_ENTRY(cnt),
89 ENA_STAT_TX_ENTRY(bytes),
90 ENA_STAT_TX_ENTRY(prepare_ctx_err),
91 ENA_STAT_TX_ENTRY(tx_poll),
92 ENA_STAT_TX_ENTRY(doorbells),
93 ENA_STAT_TX_ENTRY(bad_req_id),
94 ENA_STAT_TX_ENTRY(available_desc),
95 ENA_STAT_TX_ENTRY(missed_tx),
98 static const struct ena_stats ena_stats_rx_strings[] = {
99 ENA_STAT_RX_ENTRY(cnt),
100 ENA_STAT_RX_ENTRY(bytes),
101 ENA_STAT_RX_ENTRY(refill_partial),
102 ENA_STAT_RX_ENTRY(l3_csum_bad),
103 ENA_STAT_RX_ENTRY(l4_csum_bad),
104 ENA_STAT_RX_ENTRY(l4_csum_good),
105 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
106 ENA_STAT_RX_ENTRY(bad_desc_num),
107 ENA_STAT_RX_ENTRY(bad_req_id),
110 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
111 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings)
112 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
113 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
115 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
116 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
117 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
118 RTE_ETH_TX_OFFLOAD_TCP_TSO)
119 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
120 RTE_MBUF_F_TX_IP_CKSUM |\
121 RTE_MBUF_F_TX_TCP_SEG)
123 /** Vendor ID used by Amazon devices */
124 #define PCI_VENDOR_ID_AMAZON 0x1D0F
125 /** Amazon devices */
126 #define PCI_DEVICE_ID_ENA_VF 0xEC20
127 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21
129 #define ENA_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_L4_MASK | \
130 RTE_MBUF_F_TX_IPV6 | \
131 RTE_MBUF_F_TX_IPV4 | \
132 RTE_MBUF_F_TX_IP_CKSUM | \
133 RTE_MBUF_F_TX_TCP_SEG)
135 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
136 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
138 /** HW specific offloads capabilities. */
139 /* IPv4 checksum offload. */
140 #define ENA_L3_IPV4_CSUM 0x0001
141 /* TCP/UDP checksum offload for IPv4 packets. */
142 #define ENA_L4_IPV4_CSUM 0x0002
143 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
144 #define ENA_L4_IPV4_CSUM_PARTIAL 0x0004
145 /* TCP/UDP checksum offload for IPv6 packets. */
146 #define ENA_L4_IPV6_CSUM 0x0008
147 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
148 #define ENA_L4_IPV6_CSUM_PARTIAL 0x0010
149 /* TSO support for IPv4 packets. */
150 #define ENA_IPV4_TSO 0x0020
152 /* Device supports setting RSS hash. */
153 #define ENA_RX_RSS_HASH 0x0040
155 static const struct rte_pci_id pci_id_ena_map[] = {
156 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
161 static struct ena_aenq_handlers aenq_handlers;
163 static int ena_device_init(struct ena_adapter *adapter,
164 struct rte_pci_device *pdev,
165 struct ena_com_dev_get_features_ctx *get_feat_ctx);
166 static int ena_dev_configure(struct rte_eth_dev *dev);
167 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
168 struct ena_tx_buffer *tx_info,
169 struct rte_mbuf *mbuf,
171 uint16_t *header_len);
172 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
173 static void ena_tx_cleanup(struct ena_ring *tx_ring);
174 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
176 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
178 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
179 uint16_t nb_desc, unsigned int socket_id,
180 const struct rte_eth_txconf *tx_conf);
181 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
182 uint16_t nb_desc, unsigned int socket_id,
183 const struct rte_eth_rxconf *rx_conf,
184 struct rte_mempool *mp);
185 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
186 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
187 struct ena_com_rx_buf_info *ena_bufs,
189 uint16_t *next_to_clean,
191 static uint16_t eth_ena_recv_pkts(void *rx_queue,
192 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
193 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
194 struct rte_mbuf *mbuf, uint16_t id);
195 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
196 static void ena_init_rings(struct ena_adapter *adapter,
197 bool disable_meta_caching);
198 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
199 static int ena_start(struct rte_eth_dev *dev);
200 static int ena_stop(struct rte_eth_dev *dev);
201 static int ena_close(struct rte_eth_dev *dev);
202 static int ena_dev_reset(struct rte_eth_dev *dev);
203 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
204 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
205 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
206 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
207 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
208 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
209 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
210 static int ena_link_update(struct rte_eth_dev *dev,
211 int wait_to_complete);
212 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
213 static void ena_queue_stop(struct ena_ring *ring);
214 static void ena_queue_stop_all(struct rte_eth_dev *dev,
215 enum ena_ring_type ring_type);
216 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
217 static int ena_queue_start_all(struct rte_eth_dev *dev,
218 enum ena_ring_type ring_type);
219 static void ena_stats_restart(struct rte_eth_dev *dev);
220 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
221 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
222 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
223 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
224 static int ena_infos_get(struct rte_eth_dev *dev,
225 struct rte_eth_dev_info *dev_info);
226 static void ena_interrupt_handler_rte(void *cb_arg);
227 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
228 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
229 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
230 static int ena_xstats_get_names(struct rte_eth_dev *dev,
231 struct rte_eth_xstat_name *xstats_names,
233 static int ena_xstats_get(struct rte_eth_dev *dev,
234 struct rte_eth_xstat *stats,
236 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
240 static int ena_process_bool_devarg(const char *key,
243 static int ena_parse_devargs(struct ena_adapter *adapter,
244 struct rte_devargs *devargs);
245 static int ena_copy_eni_stats(struct ena_adapter *adapter,
246 struct ena_stats_eni *stats);
247 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
248 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static int ena_configure_aenq(struct ena_adapter *adapter);
253 static int ena_mp_primary_handle(const struct rte_mp_msg *mp_msg,
256 static const struct eth_dev_ops ena_dev_ops = {
257 .dev_configure = ena_dev_configure,
258 .dev_infos_get = ena_infos_get,
259 .rx_queue_setup = ena_rx_queue_setup,
260 .tx_queue_setup = ena_tx_queue_setup,
261 .dev_start = ena_start,
262 .dev_stop = ena_stop,
263 .link_update = ena_link_update,
264 .stats_get = ena_stats_get,
265 .xstats_get_names = ena_xstats_get_names,
266 .xstats_get = ena_xstats_get,
267 .xstats_get_by_id = ena_xstats_get_by_id,
268 .mtu_set = ena_mtu_set,
269 .rx_queue_release = ena_rx_queue_release,
270 .tx_queue_release = ena_tx_queue_release,
271 .dev_close = ena_close,
272 .dev_reset = ena_dev_reset,
273 .reta_update = ena_rss_reta_update,
274 .reta_query = ena_rss_reta_query,
275 .rx_queue_intr_enable = ena_rx_queue_intr_enable,
276 .rx_queue_intr_disable = ena_rx_queue_intr_disable,
277 .rss_hash_update = ena_rss_hash_update,
278 .rss_hash_conf_get = ena_rss_hash_conf_get,
281 /*********************************************************************
282 * Multi-Process communication bits
283 *********************************************************************/
284 /* rte_mp IPC message name */
285 #define ENA_MP_NAME "net_ena_mp"
286 /* Request timeout in seconds */
287 #define ENA_MP_REQ_TMO 5
289 /** Proxy request type */
291 ENA_MP_DEV_STATS_GET,
292 ENA_MP_ENI_STATS_GET,
298 /** Proxy message body. Shared between requests and responses. */
301 enum ena_mp_req type;
303 /* Processing result. Set in replies. 0 if message succeeded, negative
304 * error code otherwise.
308 int mtu; /* For ENA_MP_MTU_SET */
313 * Initialize IPC message.
316 * Pointer to the message to initialize.
320 * Port ID of target device.
324 mp_msg_init(struct rte_mp_msg *msg, enum ena_mp_req type, int port_id)
326 struct ena_mp_body *body = (struct ena_mp_body *)&msg->param;
328 memset(msg, 0, sizeof(*msg));
329 strlcpy(msg->name, ENA_MP_NAME, sizeof(msg->name));
330 msg->len_param = sizeof(*body);
332 body->port_id = port_id;
335 /*********************************************************************
336 * Multi-Process communication PMD API
337 *********************************************************************/
339 * Define proxy request descriptor
341 * Used to define all structures and functions required for proxying a given
342 * function to the primary process including the code to perform to prepare the
343 * request and process the response.
346 * Name of the function to proxy
348 * Message type to use
350 * Body of a function to prepare the request in form of a statement
351 * expression. It is passed all the original function arguments along with two
353 * - struct ena_adapter *adapter - PMD data of the device calling the proxy.
354 * - struct ena_mp_body *req - body of a request to prepare.
356 * Body of a function to process the response in form of a statement
357 * expression. It is passed all the original function arguments along with two
359 * - struct ena_adapter *adapter - PMD data of the device calling the proxy.
360 * - struct ena_mp_body *rsp - body of a response to process.
362 * Proxied function's arguments
364 * @note Inside prep and proc any parameters which aren't used should be marked
365 * as such (with ENA_TOUCH or __rte_unused).
367 #define ENA_PROXY_DESC(f, t, prep, proc, ...) \
368 static const enum ena_mp_req mp_type_ ## f = t; \
369 static const char *mp_name_ ## f = #t; \
370 static void mp_prep_ ## f(struct ena_adapter *adapter, \
371 struct ena_mp_body *req, \
376 static void mp_proc_ ## f(struct ena_adapter *adapter, \
377 struct ena_mp_body *rsp, \
384 * Proxy wrapper for calling primary functions in a secondary process.
386 * Depending on whether called in primary or secondary process, calls the
387 * @p func directly or proxies the call to the primary process via rte_mp IPC.
388 * This macro requires a proxy request descriptor to be defined for @p func
389 * using ENA_PROXY_DESC() macro.
392 * Device PMD data. Used for sending the message and sharing message results
393 * between primary and secondary.
397 * Arguments of @p func.
400 * - 0: Processing succeeded and response handler was called.
401 * - -EPERM: IPC is unavailable on this platform. This means only primary
402 * process may call the proxied function.
403 * - -EIO: IPC returned error on request send. Inspect rte_errno detailed
405 * - Negative error code from the proxied function.
407 * @note This mechanism is geared towards control-path tasks. Avoid calling it
408 * in fast-path unless unbound delays are allowed. This is due to the IPC
409 * mechanism itself (socket based).
410 * @note Due to IPC parameter size limitations the proxy logic shares call
411 * results through the struct ena_adapter shared memory. This makes the
412 * proxy mechanism strictly single-threaded. Therefore be sure to make all
413 * calls to the same proxied function under the same lock.
415 #define ENA_PROXY(a, f, ...) \
417 struct ena_adapter *_a = (a); \
418 struct timespec ts = { .tv_sec = ENA_MP_REQ_TMO }; \
419 struct ena_mp_body *req, *rsp; \
420 struct rte_mp_reply mp_rep; \
421 struct rte_mp_msg mp_req; \
424 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { \
425 ret = f(__VA_ARGS__); \
427 /* Prepare and send request */ \
428 req = (struct ena_mp_body *)&mp_req.param; \
429 mp_msg_init(&mp_req, mp_type_ ## f, _a->edev_data->port_id); \
430 mp_prep_ ## f(_a, req, ## __VA_ARGS__); \
432 ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts); \
433 if (likely(!ret)) { \
434 RTE_ASSERT(mp_rep.nb_received == 1); \
435 rsp = (struct ena_mp_body *)&mp_rep.msgs[0].param; \
438 mp_proc_##f(_a, rsp, ## __VA_ARGS__); \
441 "%s returned error: %d\n", \
442 mp_name_ ## f, rsp->result);\
445 } else if (rte_errno == ENOTSUP) { \
447 "No IPC, can't proxy to primary\n");\
450 PMD_DRV_LOG(ERR, "Request %s failed: %s\n", \
452 rte_strerror(rte_errno)); \
459 /*********************************************************************
460 * Multi-Process communication request descriptors
461 *********************************************************************/
463 ENA_PROXY_DESC(ena_com_get_dev_basic_stats, ENA_MP_DEV_STATS_GET,
473 if (stats != &adapter->basic_stats)
474 rte_memcpy(stats, &adapter->basic_stats, sizeof(*stats));
476 struct ena_com_dev *ena_dev, struct ena_admin_basic_stats *stats);
478 ENA_PROXY_DESC(ena_com_get_eni_stats, ENA_MP_ENI_STATS_GET,
488 if (stats != (struct ena_admin_eni_stats *)&adapter->eni_stats)
489 rte_memcpy(stats, &adapter->eni_stats, sizeof(*stats));
491 struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats);
493 ENA_PROXY_DESC(ena_com_set_dev_mtu, ENA_MP_MTU_SET,
505 struct ena_com_dev *ena_dev, int mtu);
507 ENA_PROXY_DESC(ena_com_indirect_table_set, ENA_MP_IND_TBL_SET,
518 struct ena_com_dev *ena_dev);
520 ENA_PROXY_DESC(ena_com_indirect_table_get, ENA_MP_IND_TBL_GET,
530 if (ind_tbl != adapter->indirect_table)
531 rte_memcpy(ind_tbl, adapter->indirect_table,
532 sizeof(adapter->indirect_table));
534 struct ena_com_dev *ena_dev, u32 *ind_tbl);
536 static inline void ena_rx_mbuf_prepare(struct ena_ring *rx_ring,
537 struct rte_mbuf *mbuf,
538 struct ena_com_rx_ctx *ena_rx_ctx,
541 struct ena_stats_rx *rx_stats = &rx_ring->rx_stats;
542 uint64_t ol_flags = 0;
543 uint32_t packet_type = 0;
545 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
546 packet_type |= RTE_PTYPE_L4_TCP;
547 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
548 packet_type |= RTE_PTYPE_L4_UDP;
550 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
551 packet_type |= RTE_PTYPE_L3_IPV4;
552 if (unlikely(ena_rx_ctx->l3_csum_err)) {
553 ++rx_stats->l3_csum_bad;
554 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
556 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
558 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
559 packet_type |= RTE_PTYPE_L3_IPV6;
562 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) {
563 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
565 if (unlikely(ena_rx_ctx->l4_csum_err)) {
566 ++rx_stats->l4_csum_bad;
567 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
569 ++rx_stats->l4_csum_good;
570 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
575 likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
576 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
577 mbuf->hash.rss = ena_rx_ctx->hash;
580 mbuf->ol_flags = ol_flags;
581 mbuf->packet_type = packet_type;
584 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
585 struct ena_com_tx_ctx *ena_tx_ctx,
586 uint64_t queue_offloads,
587 bool disable_meta_caching)
589 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
591 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
592 (queue_offloads & QUEUE_OFFLOADS)) {
593 /* check if TSO is required */
594 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
595 (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
596 ena_tx_ctx->tso_enable = true;
598 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
601 /* check if L3 checksum is needed */
602 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
603 (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
604 ena_tx_ctx->l3_csum_enable = true;
606 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
607 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
609 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
611 /* set don't fragment (DF) flag */
612 if (mbuf->packet_type &
613 (RTE_PTYPE_L4_NONFRAG
614 | RTE_PTYPE_INNER_L4_NONFRAG))
615 ena_tx_ctx->df = true;
618 /* check if L4 checksum is needed */
619 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
620 (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
621 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
622 ena_tx_ctx->l4_csum_enable = true;
623 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
624 RTE_MBUF_F_TX_UDP_CKSUM) &&
625 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
626 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
627 ena_tx_ctx->l4_csum_enable = true;
629 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
630 ena_tx_ctx->l4_csum_enable = false;
633 ena_meta->mss = mbuf->tso_segsz;
634 ena_meta->l3_hdr_len = mbuf->l3_len;
635 ena_meta->l3_hdr_offset = mbuf->l2_len;
637 ena_tx_ctx->meta_valid = true;
638 } else if (disable_meta_caching) {
639 memset(ena_meta, 0, sizeof(*ena_meta));
640 ena_tx_ctx->meta_valid = true;
642 ena_tx_ctx->meta_valid = false;
646 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
648 struct ena_tx_buffer *tx_info = NULL;
650 if (likely(req_id < tx_ring->ring_size)) {
651 tx_info = &tx_ring->tx_buffer_info[req_id];
652 if (likely(tx_info->mbuf))
657 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
659 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
661 /* Trigger device reset */
662 ++tx_ring->tx_stats.bad_req_id;
663 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
664 tx_ring->adapter->trigger_reset = true;
668 static void ena_config_host_info(struct ena_com_dev *ena_dev)
670 struct ena_admin_host_info *host_info;
673 /* Allocate only the host info */
674 rc = ena_com_allocate_host_info(ena_dev);
676 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
680 host_info = ena_dev->host_attr.host_info;
682 host_info->os_type = ENA_ADMIN_OS_DPDK;
683 host_info->kernel_ver = RTE_VERSION;
684 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
685 sizeof(host_info->kernel_ver_str));
686 host_info->os_dist = RTE_VERSION;
687 strlcpy((char *)host_info->os_dist_str, rte_version(),
688 sizeof(host_info->os_dist_str));
689 host_info->driver_version =
690 (DRV_MODULE_VER_MAJOR) |
691 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
692 (DRV_MODULE_VER_SUBMINOR <<
693 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
694 host_info->num_cpus = rte_lcore_count();
696 host_info->driver_supported_features =
697 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
698 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
700 rc = ena_com_set_host_attributes(ena_dev);
702 if (rc == -ENA_COM_UNSUPPORTED)
703 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
705 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
713 ena_com_delete_host_info(ena_dev);
716 /* This function calculates the number of xstats based on the current config */
717 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
719 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
720 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
721 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
724 static void ena_config_debug_area(struct ena_adapter *adapter)
729 ss_count = ena_xstats_calc_num(adapter->edev_data);
731 /* allocate 32 bytes for each string and 64bit for the value */
732 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
734 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
736 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
740 rc = ena_com_set_host_attributes(&adapter->ena_dev);
742 if (rc == -ENA_COM_UNSUPPORTED)
743 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
745 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
752 ena_com_delete_debug_area(&adapter->ena_dev);
755 static int ena_close(struct rte_eth_dev *dev)
757 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
758 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
759 struct ena_adapter *adapter = dev->data->dev_private;
762 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
765 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
767 adapter->state = ENA_ADAPTER_STATE_CLOSED;
769 ena_rx_queue_release_all(dev);
770 ena_tx_queue_release_all(dev);
772 rte_free(adapter->drv_stats);
773 adapter->drv_stats = NULL;
775 rte_intr_disable(intr_handle);
776 rte_intr_callback_unregister(intr_handle,
777 ena_interrupt_handler_rte,
781 * MAC is not allocated dynamically. Setting NULL should prevent from
782 * release of the resource in the rte_eth_dev_release_port().
784 dev->data->mac_addrs = NULL;
790 ena_dev_reset(struct rte_eth_dev *dev)
794 /* Cannot release memory in secondary process */
795 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
796 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
800 ena_destroy_device(dev);
801 rc = eth_ena_dev_init(dev);
803 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
808 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
810 int nb_queues = dev->data->nb_rx_queues;
813 for (i = 0; i < nb_queues; i++)
814 ena_rx_queue_release(dev, i);
817 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
819 int nb_queues = dev->data->nb_tx_queues;
822 for (i = 0; i < nb_queues; i++)
823 ena_tx_queue_release(dev, i);
826 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
828 struct ena_ring *ring = dev->data->rx_queues[qid];
830 /* Free ring resources */
831 rte_free(ring->rx_buffer_info);
832 ring->rx_buffer_info = NULL;
834 rte_free(ring->rx_refill_buffer);
835 ring->rx_refill_buffer = NULL;
837 rte_free(ring->empty_rx_reqs);
838 ring->empty_rx_reqs = NULL;
840 ring->configured = 0;
842 PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
843 ring->port_id, ring->id);
846 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
848 struct ena_ring *ring = dev->data->tx_queues[qid];
850 /* Free ring resources */
851 rte_free(ring->push_buf_intermediate_buf);
853 rte_free(ring->tx_buffer_info);
855 rte_free(ring->empty_tx_reqs);
857 ring->empty_tx_reqs = NULL;
858 ring->tx_buffer_info = NULL;
859 ring->push_buf_intermediate_buf = NULL;
861 ring->configured = 0;
863 PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
864 ring->port_id, ring->id);
867 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
871 for (i = 0; i < ring->ring_size; ++i) {
872 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
874 rte_mbuf_raw_free(rx_info->mbuf);
875 rx_info->mbuf = NULL;
880 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
884 for (i = 0; i < ring->ring_size; ++i) {
885 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
888 rte_pktmbuf_free(tx_buf->mbuf);
894 static int ena_link_update(struct rte_eth_dev *dev,
895 __rte_unused int wait_to_complete)
897 struct rte_eth_link *link = &dev->data->dev_link;
898 struct ena_adapter *adapter = dev->data->dev_private;
900 link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
901 link->link_speed = RTE_ETH_SPEED_NUM_NONE;
902 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
907 static int ena_queue_start_all(struct rte_eth_dev *dev,
908 enum ena_ring_type ring_type)
910 struct ena_adapter *adapter = dev->data->dev_private;
911 struct ena_ring *queues = NULL;
916 if (ring_type == ENA_RING_TYPE_RX) {
917 queues = adapter->rx_ring;
918 nb_queues = dev->data->nb_rx_queues;
920 queues = adapter->tx_ring;
921 nb_queues = dev->data->nb_tx_queues;
923 for (i = 0; i < nb_queues; i++) {
924 if (queues[i].configured) {
925 if (ring_type == ENA_RING_TYPE_RX) {
927 dev->data->rx_queues[i] == &queues[i],
928 "Inconsistent state of Rx queues\n");
931 dev->data->tx_queues[i] == &queues[i],
932 "Inconsistent state of Tx queues\n");
935 rc = ena_queue_start(dev, &queues[i]);
939 "Failed to start queue[%d] of type(%d)\n",
950 if (queues[i].configured)
951 ena_queue_stop(&queues[i]);
956 static int ena_check_valid_conf(struct ena_adapter *adapter)
958 uint32_t mtu = adapter->edev_data->mtu;
960 if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
962 "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
963 mtu, adapter->max_mtu, ENA_MIN_MTU);
964 return ENA_COM_UNSUPPORTED;
971 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
972 bool use_large_llq_hdr)
974 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
975 struct ena_com_dev *ena_dev = ctx->ena_dev;
976 uint32_t max_tx_queue_size;
977 uint32_t max_rx_queue_size;
979 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
980 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
981 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
982 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
983 max_queue_ext->max_rx_sq_depth);
984 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
986 if (ena_dev->tx_mem_queue_type ==
987 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
988 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
991 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
992 max_queue_ext->max_tx_sq_depth);
995 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
996 max_queue_ext->max_per_packet_rx_descs);
997 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
998 max_queue_ext->max_per_packet_tx_descs);
1000 struct ena_admin_queue_feature_desc *max_queues =
1001 &ctx->get_feat_ctx->max_queues;
1002 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
1003 max_queues->max_sq_depth);
1004 max_tx_queue_size = max_queues->max_cq_depth;
1006 if (ena_dev->tx_mem_queue_type ==
1007 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1008 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1009 llq->max_llq_depth);
1011 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1012 max_queues->max_sq_depth);
1015 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1016 max_queues->max_packet_rx_descs);
1017 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1018 max_queues->max_packet_tx_descs);
1021 /* Round down to the nearest power of 2 */
1022 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
1023 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
1025 if (use_large_llq_hdr) {
1026 if ((llq->entry_size_ctrl_supported &
1027 ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
1028 (ena_dev->tx_mem_queue_type ==
1029 ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
1030 max_tx_queue_size /= 2;
1032 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
1036 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
1040 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
1041 PMD_INIT_LOG(ERR, "Invalid queue size\n");
1045 ctx->max_tx_queue_size = max_tx_queue_size;
1046 ctx->max_rx_queue_size = max_rx_queue_size;
1051 static void ena_stats_restart(struct rte_eth_dev *dev)
1053 struct ena_adapter *adapter = dev->data->dev_private;
1055 rte_atomic64_init(&adapter->drv_stats->ierrors);
1056 rte_atomic64_init(&adapter->drv_stats->oerrors);
1057 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
1058 adapter->drv_stats->rx_drops = 0;
1061 static int ena_stats_get(struct rte_eth_dev *dev,
1062 struct rte_eth_stats *stats)
1064 struct ena_admin_basic_stats ena_stats;
1065 struct ena_adapter *adapter = dev->data->dev_private;
1066 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1069 int max_rings_stats;
1071 memset(&ena_stats, 0, sizeof(ena_stats));
1073 rte_spinlock_lock(&adapter->admin_lock);
1074 rc = ENA_PROXY(adapter, ena_com_get_dev_basic_stats, ena_dev,
1076 rte_spinlock_unlock(&adapter->admin_lock);
1078 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
1082 /* Set of basic statistics from ENA */
1083 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1084 ena_stats.rx_pkts_low);
1085 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1086 ena_stats.tx_pkts_low);
1087 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1088 ena_stats.rx_bytes_low);
1089 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1090 ena_stats.tx_bytes_low);
1092 /* Driver related stats */
1093 stats->imissed = adapter->drv_stats->rx_drops;
1094 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1095 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1096 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1098 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1099 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1100 for (i = 0; i < max_rings_stats; ++i) {
1101 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1103 stats->q_ibytes[i] = rx_stats->bytes;
1104 stats->q_ipackets[i] = rx_stats->cnt;
1105 stats->q_errors[i] = rx_stats->bad_desc_num +
1106 rx_stats->bad_req_id;
1109 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1110 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1111 for (i = 0; i < max_rings_stats; ++i) {
1112 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1114 stats->q_obytes[i] = tx_stats->bytes;
1115 stats->q_opackets[i] = tx_stats->cnt;
1121 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1123 struct ena_adapter *adapter;
1124 struct ena_com_dev *ena_dev;
1127 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1128 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1129 adapter = dev->data->dev_private;
1131 ena_dev = &adapter->ena_dev;
1132 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1134 if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
1136 "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
1137 mtu, adapter->max_mtu, ENA_MIN_MTU);
1141 rc = ENA_PROXY(adapter, ena_com_set_dev_mtu, ena_dev, mtu);
1143 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1145 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
1150 static int ena_start(struct rte_eth_dev *dev)
1152 struct ena_adapter *adapter = dev->data->dev_private;
1156 /* Cannot allocate memory in secondary process */
1157 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1158 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
1162 rc = ena_check_valid_conf(adapter);
1166 rc = ena_setup_rx_intr(dev);
1170 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1174 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1178 if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
1179 rc = ena_rss_configure(adapter);
1184 ena_stats_restart(dev);
1186 adapter->timestamp_wd = rte_get_timer_cycles();
1187 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1189 ticks = rte_get_timer_hz();
1190 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1191 ena_timer_wd_callback, dev);
1193 ++adapter->dev_stats.dev_start;
1194 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1199 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1201 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1205 static int ena_stop(struct rte_eth_dev *dev)
1207 struct ena_adapter *adapter = dev->data->dev_private;
1208 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1209 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1210 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1213 /* Cannot free memory in secondary process */
1214 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1215 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
1219 rte_timer_stop_sync(&adapter->timer_wd);
1220 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1221 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1223 if (adapter->trigger_reset) {
1224 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1226 PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
1229 rte_intr_disable(intr_handle);
1231 rte_intr_efd_disable(intr_handle);
1233 /* Cleanup vector list */
1234 rte_intr_vec_list_free(intr_handle);
1236 rte_intr_enable(intr_handle);
1238 ++adapter->dev_stats.dev_stop;
1239 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1240 dev->data->dev_started = 0;
1245 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
1247 struct ena_adapter *adapter = ring->adapter;
1248 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1249 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1250 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1251 struct ena_com_create_io_ctx ctx =
1252 /* policy set to _HOST just to satisfy icc compiler */
1253 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1259 ctx.msix_vector = -1;
1260 if (ring->type == ENA_RING_TYPE_TX) {
1261 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1262 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1263 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1264 for (i = 0; i < ring->ring_size; i++)
1265 ring->empty_tx_reqs[i] = i;
1267 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1268 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1269 if (rte_intr_dp_is_en(intr_handle))
1271 rte_intr_vec_list_index_get(intr_handle,
1274 for (i = 0; i < ring->ring_size; i++)
1275 ring->empty_rx_reqs[i] = i;
1277 ctx.queue_size = ring->ring_size;
1279 ctx.numa_node = ring->numa_socket_id;
1281 rc = ena_com_create_io_queue(ena_dev, &ctx);
1284 "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1285 ring->id, ena_qid, rc);
1289 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1290 &ring->ena_com_io_sq,
1291 &ring->ena_com_io_cq);
1294 "Failed to get IO queue[%d] handlers, rc: %d\n",
1296 ena_com_destroy_io_queue(ena_dev, ena_qid);
1300 if (ring->type == ENA_RING_TYPE_TX)
1301 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1303 /* Start with Rx interrupts being masked. */
1304 if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1305 ena_rx_queue_intr_disable(dev, ring->id);
1310 static void ena_queue_stop(struct ena_ring *ring)
1312 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1314 if (ring->type == ENA_RING_TYPE_RX) {
1315 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1316 ena_rx_queue_release_bufs(ring);
1318 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1319 ena_tx_queue_release_bufs(ring);
1323 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1324 enum ena_ring_type ring_type)
1326 struct ena_adapter *adapter = dev->data->dev_private;
1327 struct ena_ring *queues = NULL;
1328 uint16_t nb_queues, i;
1330 if (ring_type == ENA_RING_TYPE_RX) {
1331 queues = adapter->rx_ring;
1332 nb_queues = dev->data->nb_rx_queues;
1334 queues = adapter->tx_ring;
1335 nb_queues = dev->data->nb_tx_queues;
1338 for (i = 0; i < nb_queues; ++i)
1339 if (queues[i].configured)
1340 ena_queue_stop(&queues[i]);
1343 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1347 ena_assert_msg(ring->configured == 1,
1348 "Trying to start unconfigured queue\n");
1350 rc = ena_create_io_queue(dev, ring);
1352 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1356 ring->next_to_clean = 0;
1357 ring->next_to_use = 0;
1359 if (ring->type == ENA_RING_TYPE_TX) {
1360 ring->tx_stats.available_desc =
1361 ena_com_free_q_entries(ring->ena_com_io_sq);
1365 bufs_num = ring->ring_size - 1;
1366 rc = ena_populate_rx_queue(ring, bufs_num);
1367 if (rc != bufs_num) {
1368 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1369 ENA_IO_RXQ_IDX(ring->id));
1370 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1371 return ENA_COM_FAULT;
1373 /* Flush per-core RX buffers pools cache as they can be used on other
1376 rte_mempool_cache_flush(NULL, ring->mb_pool);
1381 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1384 unsigned int socket_id,
1385 const struct rte_eth_txconf *tx_conf)
1387 struct ena_ring *txq = NULL;
1388 struct ena_adapter *adapter = dev->data->dev_private;
1390 uint16_t dyn_thresh;
1392 txq = &adapter->tx_ring[queue_idx];
1394 if (txq->configured) {
1396 "API violation. Queue[%d] is already configured\n",
1398 return ENA_COM_FAULT;
1401 if (!rte_is_power_of_2(nb_desc)) {
1403 "Unsupported size of Tx queue: %d is not a power of 2.\n",
1408 if (nb_desc > adapter->max_tx_ring_size) {
1410 "Unsupported size of Tx queue (max size: %d)\n",
1411 adapter->max_tx_ring_size);
1415 txq->port_id = dev->data->port_id;
1416 txq->next_to_clean = 0;
1417 txq->next_to_use = 0;
1418 txq->ring_size = nb_desc;
1419 txq->size_mask = nb_desc - 1;
1420 txq->numa_socket_id = socket_id;
1421 txq->pkts_without_db = false;
1422 txq->last_cleanup_ticks = 0;
1424 txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1425 sizeof(struct ena_tx_buffer) * txq->ring_size,
1426 RTE_CACHE_LINE_SIZE,
1428 if (!txq->tx_buffer_info) {
1430 "Failed to allocate memory for Tx buffer info\n");
1434 txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1435 sizeof(uint16_t) * txq->ring_size,
1436 RTE_CACHE_LINE_SIZE,
1438 if (!txq->empty_tx_reqs) {
1440 "Failed to allocate memory for empty Tx requests\n");
1441 rte_free(txq->tx_buffer_info);
1445 txq->push_buf_intermediate_buf =
1446 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1447 txq->tx_max_header_size,
1448 RTE_CACHE_LINE_SIZE,
1450 if (!txq->push_buf_intermediate_buf) {
1451 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1452 rte_free(txq->tx_buffer_info);
1453 rte_free(txq->empty_tx_reqs);
1457 for (i = 0; i < txq->ring_size; i++)
1458 txq->empty_tx_reqs[i] = i;
1460 txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1462 /* Check if caller provided the Tx cleanup threshold value. */
1463 if (tx_conf->tx_free_thresh != 0) {
1464 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1466 dyn_thresh = txq->ring_size -
1467 txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1468 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1469 txq->ring_size - ENA_REFILL_THRESH_PACKET);
1472 txq->missing_tx_completion_threshold =
1473 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1475 /* Store pointer to this queue in upper layer */
1476 txq->configured = 1;
1477 dev->data->tx_queues[queue_idx] = txq;
1482 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1485 unsigned int socket_id,
1486 const struct rte_eth_rxconf *rx_conf,
1487 struct rte_mempool *mp)
1489 struct ena_adapter *adapter = dev->data->dev_private;
1490 struct ena_ring *rxq = NULL;
1493 uint16_t dyn_thresh;
1495 rxq = &adapter->rx_ring[queue_idx];
1496 if (rxq->configured) {
1498 "API violation. Queue[%d] is already configured\n",
1500 return ENA_COM_FAULT;
1503 if (!rte_is_power_of_2(nb_desc)) {
1505 "Unsupported size of Rx queue: %d is not a power of 2.\n",
1510 if (nb_desc > adapter->max_rx_ring_size) {
1512 "Unsupported size of Rx queue (max size: %d)\n",
1513 adapter->max_rx_ring_size);
1517 /* ENA isn't supporting buffers smaller than 1400 bytes */
1518 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1519 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1521 "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1522 buffer_size, ENA_RX_BUF_MIN_SIZE);
1526 rxq->port_id = dev->data->port_id;
1527 rxq->next_to_clean = 0;
1528 rxq->next_to_use = 0;
1529 rxq->ring_size = nb_desc;
1530 rxq->size_mask = nb_desc - 1;
1531 rxq->numa_socket_id = socket_id;
1534 rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1535 sizeof(struct ena_rx_buffer) * nb_desc,
1536 RTE_CACHE_LINE_SIZE,
1538 if (!rxq->rx_buffer_info) {
1540 "Failed to allocate memory for Rx buffer info\n");
1544 rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1545 sizeof(struct rte_mbuf *) * nb_desc,
1546 RTE_CACHE_LINE_SIZE,
1548 if (!rxq->rx_refill_buffer) {
1550 "Failed to allocate memory for Rx refill buffer\n");
1551 rte_free(rxq->rx_buffer_info);
1552 rxq->rx_buffer_info = NULL;
1556 rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1557 sizeof(uint16_t) * nb_desc,
1558 RTE_CACHE_LINE_SIZE,
1560 if (!rxq->empty_rx_reqs) {
1562 "Failed to allocate memory for empty Rx requests\n");
1563 rte_free(rxq->rx_buffer_info);
1564 rxq->rx_buffer_info = NULL;
1565 rte_free(rxq->rx_refill_buffer);
1566 rxq->rx_refill_buffer = NULL;
1570 for (i = 0; i < nb_desc; i++)
1571 rxq->empty_rx_reqs[i] = i;
1573 rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1575 if (rx_conf->rx_free_thresh != 0) {
1576 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1578 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1579 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1580 (uint16_t)(ENA_REFILL_THRESH_PACKET));
1583 /* Store pointer to this queue in upper layer */
1584 rxq->configured = 1;
1585 dev->data->rx_queues[queue_idx] = rxq;
1590 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1591 struct rte_mbuf *mbuf, uint16_t id)
1593 struct ena_com_buf ebuf;
1596 /* prepare physical address for DMA transaction */
1597 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1598 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1600 /* pass resource to device */
1601 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1602 if (unlikely(rc != 0))
1603 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1608 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1612 uint16_t next_to_use = rxq->next_to_use;
1614 #ifdef RTE_ETHDEV_DEBUG_RX
1617 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1619 if (unlikely(!count))
1622 #ifdef RTE_ETHDEV_DEBUG_RX
1623 in_use = rxq->ring_size - 1 -
1624 ena_com_free_q_entries(rxq->ena_com_io_sq);
1625 if (unlikely((in_use + count) >= rxq->ring_size))
1626 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1629 /* get resources for incoming packets */
1630 rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1631 if (unlikely(rc < 0)) {
1632 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1633 ++rxq->rx_stats.mbuf_alloc_fail;
1634 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1638 for (i = 0; i < count; i++) {
1639 struct rte_mbuf *mbuf = mbufs[i];
1640 struct ena_rx_buffer *rx_info;
1642 if (likely((i + 4) < count))
1643 rte_prefetch0(mbufs[i + 4]);
1645 req_id = rxq->empty_rx_reqs[next_to_use];
1646 rx_info = &rxq->rx_buffer_info[req_id];
1648 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1649 if (unlikely(rc != 0))
1652 rx_info->mbuf = mbuf;
1653 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1656 if (unlikely(i < count)) {
1658 "Refilled Rx queue[%d] with only %d/%d buffers\n",
1660 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1661 ++rxq->rx_stats.refill_partial;
1664 /* When we submitted free resources to device... */
1665 if (likely(i > 0)) {
1666 /* ...let HW know that it can fill buffers with data. */
1667 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1669 rxq->next_to_use = next_to_use;
1675 static int ena_device_init(struct ena_adapter *adapter,
1676 struct rte_pci_device *pdev,
1677 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1679 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1680 uint32_t aenq_groups;
1682 bool readless_supported;
1684 /* Initialize mmio registers */
1685 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1687 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1691 /* The PCIe configuration space revision id indicate if mmio reg
1694 readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1695 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1698 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1700 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1701 goto err_mmio_read_less;
1704 /* check FW version */
1705 rc = ena_com_validate_version(ena_dev);
1707 PMD_DRV_LOG(ERR, "Device version is too low\n");
1708 goto err_mmio_read_less;
1711 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1713 /* ENA device administration layer init */
1714 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1717 "Cannot initialize ENA admin queue\n");
1718 goto err_mmio_read_less;
1721 /* To enable the msix interrupts the driver needs to know the number
1722 * of queues. So the driver uses polling mode to retrieve this
1725 ena_com_set_admin_polling_mode(ena_dev, true);
1727 ena_config_host_info(ena_dev);
1729 /* Get Device Attributes and features */
1730 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1733 "Cannot get attribute for ENA device, rc: %d\n", rc);
1734 goto err_admin_init;
1737 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1738 BIT(ENA_ADMIN_NOTIFICATION) |
1739 BIT(ENA_ADMIN_KEEP_ALIVE) |
1740 BIT(ENA_ADMIN_FATAL_ERROR) |
1741 BIT(ENA_ADMIN_WARNING);
1743 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1745 adapter->all_aenq_groups = aenq_groups;
1750 ena_com_admin_destroy(ena_dev);
1753 ena_com_mmio_reg_read_request_destroy(ena_dev);
1758 static void ena_interrupt_handler_rte(void *cb_arg)
1760 struct rte_eth_dev *dev = cb_arg;
1761 struct ena_adapter *adapter = dev->data->dev_private;
1762 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1764 ena_com_admin_q_comp_intr_handler(ena_dev);
1765 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1766 ena_com_aenq_intr_handler(ena_dev, dev);
1769 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1771 if (!(adapter->active_aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)))
1774 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1777 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1778 adapter->keep_alive_timeout)) {
1779 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1780 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1781 adapter->trigger_reset = true;
1782 ++adapter->dev_stats.wd_expired;
1786 /* Check if admin queue is enabled */
1787 static void check_for_admin_com_state(struct ena_adapter *adapter)
1789 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1790 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1791 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1792 adapter->trigger_reset = true;
1796 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1797 struct ena_ring *tx_ring)
1799 struct ena_tx_buffer *tx_buf;
1801 uint64_t completion_delay;
1802 uint32_t missed_tx = 0;
1806 for (i = 0; i < tx_ring->ring_size; ++i) {
1807 tx_buf = &tx_ring->tx_buffer_info[i];
1808 timestamp = tx_buf->timestamp;
1813 completion_delay = rte_get_timer_cycles() - timestamp;
1814 if (completion_delay > adapter->missing_tx_completion_to) {
1815 if (unlikely(!tx_buf->print_once)) {
1817 "Found a Tx that wasn't completed on time, qid %d, index %d. "
1818 "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1819 tx_ring->id, i, completion_delay /
1820 rte_get_timer_hz() * 1000);
1821 tx_buf->print_once = true;
1827 if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1829 "The number of lost Tx completions is above the threshold (%d > %d). "
1830 "Trigger the device reset.\n",
1832 tx_ring->missing_tx_completion_threshold);
1833 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1834 adapter->trigger_reset = true;
1838 tx_ring->tx_stats.missed_tx += missed_tx;
1843 static void check_for_tx_completions(struct ena_adapter *adapter)
1845 struct ena_ring *tx_ring;
1846 uint64_t tx_cleanup_delay;
1849 uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1851 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1854 nb_tx_queues = adapter->edev_data->nb_tx_queues;
1855 budget = adapter->missing_tx_completion_budget;
1857 qid = adapter->last_tx_comp_qid;
1858 while (budget-- > 0) {
1859 tx_ring = &adapter->tx_ring[qid];
1861 /* Tx cleanup is called only by the burst function and can be
1862 * called dynamically by the application. Also cleanup is
1863 * limited by the threshold. To avoid false detection of the
1864 * missing HW Tx completion, get the delay since last cleanup
1865 * function was called.
1867 tx_cleanup_delay = rte_get_timer_cycles() -
1868 tx_ring->last_cleanup_ticks;
1869 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1870 check_for_tx_completion_in_queue(adapter, tx_ring);
1871 qid = (qid + 1) % nb_tx_queues;
1874 adapter->last_tx_comp_qid = qid;
1877 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1880 struct rte_eth_dev *dev = arg;
1881 struct ena_adapter *adapter = dev->data->dev_private;
1883 if (unlikely(adapter->trigger_reset))
1886 check_for_missing_keep_alive(adapter);
1887 check_for_admin_com_state(adapter);
1888 check_for_tx_completions(adapter);
1890 if (unlikely(adapter->trigger_reset)) {
1891 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1892 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1898 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1899 struct ena_admin_feature_llq_desc *llq,
1900 bool use_large_llq_hdr)
1902 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1903 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1904 llq_config->llq_num_decs_before_header =
1905 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1907 if (use_large_llq_hdr &&
1908 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1909 llq_config->llq_ring_entry_size =
1910 ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1911 llq_config->llq_ring_entry_size_value = 256;
1913 llq_config->llq_ring_entry_size =
1914 ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1915 llq_config->llq_ring_entry_size_value = 128;
1920 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1921 struct ena_com_dev *ena_dev,
1922 struct ena_admin_feature_llq_desc *llq,
1923 struct ena_llq_configurations *llq_default_configurations)
1926 u32 llq_feature_mask;
1928 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1929 if (!(ena_dev->supported_features & llq_feature_mask)) {
1931 "LLQ is not supported. Fallback to host mode policy.\n");
1932 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1936 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1938 PMD_INIT_LOG(WARNING,
1939 "Failed to config dev mode. Fallback to host mode policy.\n");
1940 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1944 /* Nothing to config, exit */
1945 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1948 if (!adapter->dev_mem_base) {
1950 "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1951 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1955 ena_dev->mem_bar = adapter->dev_mem_base;
1960 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1961 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1963 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1965 /* Regular queues capabilities */
1966 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1967 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1968 &get_feat_ctx->max_queue_ext.max_queue_ext;
1969 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1970 max_queue_ext->max_rx_cq_num);
1971 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1972 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1974 struct ena_admin_queue_feature_desc *max_queues =
1975 &get_feat_ctx->max_queues;
1976 io_tx_sq_num = max_queues->max_sq_num;
1977 io_tx_cq_num = max_queues->max_cq_num;
1978 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1981 /* In case of LLQ use the llq number in the get feature cmd */
1982 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1983 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1985 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1986 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1987 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1989 if (unlikely(max_num_io_queues == 0)) {
1990 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1994 return max_num_io_queues;
1998 ena_set_offloads(struct ena_offloads *offloads,
1999 struct ena_admin_feature_offload_desc *offload_desc)
2001 if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2002 offloads->tx_offloads |= ENA_IPV4_TSO;
2004 /* Tx IPv4 checksum offloads */
2005 if (offload_desc->tx &
2006 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
2007 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
2008 if (offload_desc->tx &
2009 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
2010 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
2011 if (offload_desc->tx &
2012 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2013 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
2015 /* Tx IPv6 checksum offloads */
2016 if (offload_desc->tx &
2017 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
2018 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
2019 if (offload_desc->tx &
2020 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2021 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
2023 /* Rx IPv4 checksum offloads */
2024 if (offload_desc->rx_supported &
2025 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
2026 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
2027 if (offload_desc->rx_supported &
2028 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2029 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
2031 /* Rx IPv6 checksum offloads */
2032 if (offload_desc->rx_supported &
2033 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2034 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
2036 if (offload_desc->rx_supported &
2037 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
2038 offloads->rx_offloads |= ENA_RX_RSS_HASH;
2041 static int ena_init_once(void)
2043 static bool init_done;
2048 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2049 /* Init timer subsystem for the ENA timer service. */
2050 rte_timer_subsystem_init();
2051 /* Register handler for requests from secondary processes. */
2052 rte_mp_action_register(ENA_MP_NAME, ena_mp_primary_handle);
2059 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
2061 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
2062 struct rte_pci_device *pci_dev;
2063 struct rte_intr_handle *intr_handle;
2064 struct ena_adapter *adapter = eth_dev->data->dev_private;
2065 struct ena_com_dev *ena_dev = &adapter->ena_dev;
2066 struct ena_com_dev_get_features_ctx get_feat_ctx;
2067 struct ena_llq_configurations llq_config;
2068 const char *queue_type_str;
2069 uint32_t max_num_io_queues;
2071 static int adapters_found;
2072 bool disable_meta_caching;
2074 eth_dev->dev_ops = &ena_dev_ops;
2075 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
2076 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
2077 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
2079 rc = ena_init_once();
2083 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2086 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2088 memset(adapter, 0, sizeof(struct ena_adapter));
2089 ena_dev = &adapter->ena_dev;
2091 adapter->edev_data = eth_dev->data;
2093 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2095 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
2096 pci_dev->addr.domain,
2098 pci_dev->addr.devid,
2099 pci_dev->addr.function);
2101 intr_handle = pci_dev->intr_handle;
2103 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
2104 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
2106 if (!adapter->regs) {
2107 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
2112 ena_dev->reg_bar = adapter->regs;
2113 /* Pass device data as a pointer which can be passed to the IO functions
2114 * by the ena_com (for example - the memory allocation).
2116 ena_dev->dmadev = eth_dev->data;
2118 adapter->id_number = adapters_found;
2120 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
2121 adapter->id_number);
2123 rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
2125 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
2129 /* device specific initialization routine */
2130 rc = ena_device_init(adapter, pci_dev, &get_feat_ctx);
2132 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
2136 /* Check if device supports LSC */
2137 if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE)))
2138 adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
2140 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
2141 adapter->use_large_llq_hdr);
2142 rc = ena_set_queues_placement_policy(adapter, ena_dev,
2143 &get_feat_ctx.llq, &llq_config);
2145 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
2149 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
2150 queue_type_str = "Regular";
2152 queue_type_str = "Low latency";
2153 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
2155 calc_queue_ctx.ena_dev = ena_dev;
2156 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
2158 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
2159 rc = ena_calc_io_queue_size(&calc_queue_ctx,
2160 adapter->use_large_llq_hdr);
2161 if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
2163 goto err_device_destroy;
2166 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
2167 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
2168 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
2169 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
2170 adapter->max_num_io_queues = max_num_io_queues;
2172 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2173 disable_meta_caching =
2174 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
2175 BIT(ENA_ADMIN_DISABLE_META_CACHING));
2177 disable_meta_caching = false;
2180 /* prepare ring structures */
2181 ena_init_rings(adapter, disable_meta_caching);
2183 ena_config_debug_area(adapter);
2185 /* Set max MTU for this device */
2186 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
2188 ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
2190 /* Copy MAC address and point DPDK to it */
2191 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
2192 rte_ether_addr_copy((struct rte_ether_addr *)
2193 get_feat_ctx.dev_attr.mac_addr,
2194 (struct rte_ether_addr *)adapter->mac_addr);
2196 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2197 if (unlikely(rc != 0)) {
2198 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
2199 goto err_delete_debug_area;
2202 adapter->drv_stats = rte_zmalloc("adapter stats",
2203 sizeof(*adapter->drv_stats),
2204 RTE_CACHE_LINE_SIZE);
2205 if (!adapter->drv_stats) {
2207 "Failed to allocate memory for adapter statistics\n");
2209 goto err_rss_destroy;
2212 rte_spinlock_init(&adapter->admin_lock);
2214 rte_intr_callback_register(intr_handle,
2215 ena_interrupt_handler_rte,
2217 rte_intr_enable(intr_handle);
2218 ena_com_set_admin_polling_mode(ena_dev, false);
2219 ena_com_admin_aenq_enable(ena_dev);
2221 rte_timer_init(&adapter->timer_wd);
2224 adapter->state = ENA_ADAPTER_STATE_INIT;
2229 ena_com_rss_destroy(ena_dev);
2230 err_delete_debug_area:
2231 ena_com_delete_debug_area(ena_dev);
2234 ena_com_delete_host_info(ena_dev);
2235 ena_com_admin_destroy(ena_dev);
2241 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
2243 struct ena_adapter *adapter = eth_dev->data->dev_private;
2244 struct ena_com_dev *ena_dev = &adapter->ena_dev;
2246 if (adapter->state == ENA_ADAPTER_STATE_FREE)
2249 ena_com_set_admin_running_state(ena_dev, false);
2251 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
2254 ena_com_rss_destroy(ena_dev);
2256 ena_com_delete_debug_area(ena_dev);
2257 ena_com_delete_host_info(ena_dev);
2259 ena_com_abort_admin_commands(ena_dev);
2260 ena_com_wait_for_abort_completion(ena_dev);
2261 ena_com_admin_destroy(ena_dev);
2262 ena_com_mmio_reg_read_request_destroy(ena_dev);
2264 adapter->state = ENA_ADAPTER_STATE_FREE;
2267 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
2269 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2272 ena_destroy_device(eth_dev);
2277 static int ena_dev_configure(struct rte_eth_dev *dev)
2279 struct ena_adapter *adapter = dev->data->dev_private;
2282 adapter->state = ENA_ADAPTER_STATE_CONFIG;
2284 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2285 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2286 dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2288 /* Scattered Rx cannot be turned off in the HW, so this capability must
2291 dev->data->scattered_rx = 1;
2293 adapter->last_tx_comp_qid = 0;
2295 adapter->missing_tx_completion_budget =
2296 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2298 adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2299 /* To avoid detection of the spurious Tx completion timeout due to
2300 * application not calling the Tx cleanup function, set timeout for the
2301 * Tx queue which should be half of the missing completion timeout for a
2302 * safety. If there will be a lot of missing Tx completions in the
2303 * queue, they will be detected sooner or later.
2305 adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2307 rc = ena_configure_aenq(adapter);
2312 static void ena_init_rings(struct ena_adapter *adapter,
2313 bool disable_meta_caching)
2317 for (i = 0; i < adapter->max_num_io_queues; i++) {
2318 struct ena_ring *ring = &adapter->tx_ring[i];
2320 ring->configured = 0;
2321 ring->type = ENA_RING_TYPE_TX;
2322 ring->adapter = adapter;
2324 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2325 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2326 ring->sgl_size = adapter->max_tx_sgl_size;
2327 ring->disable_meta_caching = disable_meta_caching;
2330 for (i = 0; i < adapter->max_num_io_queues; i++) {
2331 struct ena_ring *ring = &adapter->rx_ring[i];
2333 ring->configured = 0;
2334 ring->type = ENA_RING_TYPE_RX;
2335 ring->adapter = adapter;
2337 ring->sgl_size = adapter->max_rx_sgl_size;
2341 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2343 uint64_t port_offloads = 0;
2345 if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2346 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2348 if (adapter->offloads.rx_offloads &
2349 (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2351 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2353 if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2354 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2356 port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2358 return port_offloads;
2361 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2363 uint64_t port_offloads = 0;
2365 if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2366 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2368 if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2369 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2370 if (adapter->offloads.tx_offloads &
2371 (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2372 ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2374 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2376 port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2378 return port_offloads;
2381 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2383 RTE_SET_USED(adapter);
2388 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2390 RTE_SET_USED(adapter);
2395 static int ena_infos_get(struct rte_eth_dev *dev,
2396 struct rte_eth_dev_info *dev_info)
2398 struct ena_adapter *adapter;
2399 struct ena_com_dev *ena_dev;
2401 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2402 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2403 adapter = dev->data->dev_private;
2405 ena_dev = &adapter->ena_dev;
2406 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2408 dev_info->speed_capa =
2409 RTE_ETH_LINK_SPEED_1G |
2410 RTE_ETH_LINK_SPEED_2_5G |
2411 RTE_ETH_LINK_SPEED_5G |
2412 RTE_ETH_LINK_SPEED_10G |
2413 RTE_ETH_LINK_SPEED_25G |
2414 RTE_ETH_LINK_SPEED_40G |
2415 RTE_ETH_LINK_SPEED_50G |
2416 RTE_ETH_LINK_SPEED_100G;
2418 /* Inform framework about available features */
2419 dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2420 dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2421 dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2422 dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2424 dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2425 dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2427 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2428 dev_info->max_rx_pktlen = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2430 dev_info->min_mtu = ENA_MIN_MTU;
2431 dev_info->max_mtu = adapter->max_mtu;
2432 dev_info->max_mac_addrs = 1;
2434 dev_info->max_rx_queues = adapter->max_num_io_queues;
2435 dev_info->max_tx_queues = adapter->max_num_io_queues;
2436 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2438 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2439 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2440 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2441 adapter->max_rx_sgl_size);
2442 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2443 adapter->max_rx_sgl_size);
2445 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2446 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2447 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2448 adapter->max_tx_sgl_size);
2449 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2450 adapter->max_tx_sgl_size);
2452 dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2453 dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2458 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2460 mbuf->data_len = len;
2461 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2466 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2467 struct ena_com_rx_buf_info *ena_bufs,
2469 uint16_t *next_to_clean,
2472 struct rte_mbuf *mbuf;
2473 struct rte_mbuf *mbuf_head;
2474 struct ena_rx_buffer *rx_info;
2476 uint16_t ntc, len, req_id, buf = 0;
2478 if (unlikely(descs == 0))
2481 ntc = *next_to_clean;
2483 len = ena_bufs[buf].len;
2484 req_id = ena_bufs[buf].req_id;
2486 rx_info = &rx_ring->rx_buffer_info[req_id];
2488 mbuf = rx_info->mbuf;
2489 RTE_ASSERT(mbuf != NULL);
2491 ena_init_rx_mbuf(mbuf, len);
2493 /* Fill the mbuf head with the data specific for 1st segment. */
2495 mbuf_head->nb_segs = descs;
2496 mbuf_head->port = rx_ring->port_id;
2497 mbuf_head->pkt_len = len;
2498 mbuf_head->data_off += offset;
2500 rx_info->mbuf = NULL;
2501 rx_ring->empty_rx_reqs[ntc] = req_id;
2502 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2506 len = ena_bufs[buf].len;
2507 req_id = ena_bufs[buf].req_id;
2509 rx_info = &rx_ring->rx_buffer_info[req_id];
2510 RTE_ASSERT(rx_info->mbuf != NULL);
2512 if (unlikely(len == 0)) {
2514 * Some devices can pass descriptor with the length 0.
2515 * To avoid confusion, the PMD is simply putting the
2516 * descriptor back, as it was never used. We'll avoid
2517 * mbuf allocation that way.
2519 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2520 rx_info->mbuf, req_id);
2521 if (unlikely(rc != 0)) {
2522 /* Free the mbuf in case of an error. */
2523 rte_mbuf_raw_free(rx_info->mbuf);
2526 * If there was no error, just exit the loop as
2527 * 0 length descriptor is always the last one.
2532 /* Create an mbuf chain. */
2533 mbuf->next = rx_info->mbuf;
2536 ena_init_rx_mbuf(mbuf, len);
2537 mbuf_head->pkt_len += len;
2541 * Mark the descriptor as depleted and perform necessary
2543 * This code will execute in two cases:
2544 * 1. Descriptor len was greater than 0 - normal situation.
2545 * 2. Descriptor len was 0 and we failed to add the descriptor
2546 * to the device. In that situation, we should try to add
2547 * the mbuf again in the populate routine and mark the
2548 * descriptor as used up by the device.
2550 rx_info->mbuf = NULL;
2551 rx_ring->empty_rx_reqs[ntc] = req_id;
2552 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2555 *next_to_clean = ntc;
2560 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2563 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2564 unsigned int free_queue_entries;
2565 uint16_t next_to_clean = rx_ring->next_to_clean;
2566 uint16_t descs_in_use;
2567 struct rte_mbuf *mbuf;
2569 struct ena_com_rx_ctx ena_rx_ctx;
2573 #ifdef RTE_ETHDEV_DEBUG_RX
2574 /* Check adapter state */
2575 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2577 "Trying to receive pkts while device is NOT running\n");
2582 fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2584 descs_in_use = rx_ring->ring_size -
2585 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2586 nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2588 for (completed = 0; completed < nb_pkts; completed++) {
2589 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2590 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2591 ena_rx_ctx.descs = 0;
2592 ena_rx_ctx.pkt_offset = 0;
2593 /* receive packet context */
2594 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2595 rx_ring->ena_com_io_sq,
2599 "Failed to get the packet from the device, rc: %d\n",
2601 if (rc == ENA_COM_NO_SPACE) {
2602 ++rx_ring->rx_stats.bad_desc_num;
2603 rx_ring->adapter->reset_reason =
2604 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2606 ++rx_ring->rx_stats.bad_req_id;
2607 rx_ring->adapter->reset_reason =
2608 ENA_REGS_RESET_INV_RX_REQ_ID;
2610 rx_ring->adapter->trigger_reset = true;
2614 mbuf = ena_rx_mbuf(rx_ring,
2615 ena_rx_ctx.ena_bufs,
2618 ena_rx_ctx.pkt_offset);
2619 if (unlikely(mbuf == NULL)) {
2620 for (i = 0; i < ena_rx_ctx.descs; ++i) {
2621 rx_ring->empty_rx_reqs[next_to_clean] =
2622 rx_ring->ena_bufs[i].req_id;
2623 next_to_clean = ENA_IDX_NEXT_MASKED(
2624 next_to_clean, rx_ring->size_mask);
2629 /* fill mbuf attributes if any */
2630 ena_rx_mbuf_prepare(rx_ring, mbuf, &ena_rx_ctx, fill_hash);
2632 if (unlikely(mbuf->ol_flags &
2633 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD)))
2634 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2636 rx_pkts[completed] = mbuf;
2637 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2640 rx_ring->rx_stats.cnt += completed;
2641 rx_ring->next_to_clean = next_to_clean;
2643 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2645 /* Burst refill to save doorbells, memory barriers, const interval */
2646 if (free_queue_entries >= rx_ring->rx_free_thresh) {
2647 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2648 ena_populate_rx_queue(rx_ring, free_queue_entries);
2655 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2661 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2662 struct ena_adapter *adapter = tx_ring->adapter;
2663 struct rte_ipv4_hdr *ip_hdr;
2665 uint64_t l4_csum_flag;
2666 uint64_t dev_offload_capa;
2667 uint16_t frag_field;
2668 bool need_pseudo_csum;
2670 dev_offload_capa = adapter->offloads.tx_offloads;
2671 for (i = 0; i != nb_pkts; i++) {
2673 ol_flags = m->ol_flags;
2675 /* Check if any offload flag was set */
2679 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2680 /* SCTP checksum offload is not supported by the ENA. */
2681 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2682 l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2684 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2686 rte_errno = ENOTSUP;
2690 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2691 !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2692 m->nb_segs == tx_ring->sgl_size &&
2693 m->data_len < tx_ring->tx_max_header_size))) {
2695 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2701 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2702 /* Check if requested offload is also enabled for the queue */
2703 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2704 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2705 (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2706 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2707 (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2708 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2710 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2711 i, m->nb_segs, tx_ring->id);
2716 /* The caller is obligated to set l2 and l3 len if any cksum
2717 * offload is enabled.
2719 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2720 (m->l2_len == 0 || m->l3_len == 0))) {
2722 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2727 ret = rte_validate_tx_offload(m);
2734 /* Verify HW support for requested offloads and determine if
2735 * pseudo header checksum is needed.
2737 need_pseudo_csum = false;
2738 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2739 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2740 !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2741 rte_errno = ENOTSUP;
2745 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2746 !(dev_offload_capa & ENA_IPV4_TSO)) {
2747 rte_errno = ENOTSUP;
2751 /* Check HW capabilities and if pseudo csum is needed
2754 if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2755 !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2756 if (dev_offload_capa &
2757 ENA_L4_IPV4_CSUM_PARTIAL) {
2758 need_pseudo_csum = true;
2760 rte_errno = ENOTSUP;
2765 /* Parse the DF flag */
2766 ip_hdr = rte_pktmbuf_mtod_offset(m,
2767 struct rte_ipv4_hdr *, m->l2_len);
2768 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2769 if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2770 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2771 } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2772 /* In case we are supposed to TSO and have DF
2773 * not set (DF=0) hardware must be provided with
2776 need_pseudo_csum = true;
2778 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2779 /* There is no support for IPv6 TSO as for now. */
2780 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2781 rte_errno = ENOTSUP;
2785 /* Check HW capabilities and if pseudo csum is needed */
2786 if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2787 !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2788 if (dev_offload_capa &
2789 ENA_L4_IPV6_CSUM_PARTIAL) {
2790 need_pseudo_csum = true;
2792 rte_errno = ENOTSUP;
2798 if (need_pseudo_csum) {
2799 ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2810 static void ena_update_hints(struct ena_adapter *adapter,
2811 struct ena_admin_ena_hw_hints *hints)
2813 if (hints->admin_completion_tx_timeout)
2814 adapter->ena_dev.admin_queue.completion_timeout =
2815 hints->admin_completion_tx_timeout * 1000;
2817 if (hints->mmio_read_timeout)
2818 /* convert to usec */
2819 adapter->ena_dev.mmio_read.reg_read_to =
2820 hints->mmio_read_timeout * 1000;
2822 if (hints->missing_tx_completion_timeout) {
2823 if (hints->missing_tx_completion_timeout ==
2824 ENA_HW_HINTS_NO_TIMEOUT) {
2825 adapter->missing_tx_completion_to =
2826 ENA_HW_HINTS_NO_TIMEOUT;
2828 /* Convert from msecs to ticks */
2829 adapter->missing_tx_completion_to = rte_get_timer_hz() *
2830 hints->missing_tx_completion_timeout / 1000;
2831 adapter->tx_cleanup_stall_delay =
2832 adapter->missing_tx_completion_to / 2;
2836 if (hints->driver_watchdog_timeout) {
2837 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2838 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2840 // Convert msecs to ticks
2841 adapter->keep_alive_timeout =
2842 (hints->driver_watchdog_timeout *
2843 rte_get_timer_hz()) / 1000;
2847 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2848 struct ena_tx_buffer *tx_info,
2849 struct rte_mbuf *mbuf,
2851 uint16_t *header_len)
2853 struct ena_com_buf *ena_buf;
2854 uint16_t delta, seg_len, push_len;
2857 seg_len = mbuf->data_len;
2859 tx_info->mbuf = mbuf;
2860 ena_buf = tx_info->bufs;
2862 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2864 * Tx header might be (and will be in most cases) smaller than
2865 * tx_max_header_size. But it's not an issue to send more data
2866 * to the device, than actually needed if the mbuf size is
2867 * greater than tx_max_header_size.
2869 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2870 *header_len = push_len;
2872 if (likely(push_len <= seg_len)) {
2873 /* If the push header is in the single segment, then
2874 * just point it to the 1st mbuf data.
2876 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2878 /* If the push header lays in the several segments, copy
2879 * it to the intermediate buffer.
2881 rte_pktmbuf_read(mbuf, 0, push_len,
2882 tx_ring->push_buf_intermediate_buf);
2883 *push_header = tx_ring->push_buf_intermediate_buf;
2884 delta = push_len - seg_len;
2887 *push_header = NULL;
2892 /* Process first segment taking into consideration pushed header */
2893 if (seg_len > push_len) {
2894 ena_buf->paddr = mbuf->buf_iova +
2897 ena_buf->len = seg_len - push_len;
2899 tx_info->num_of_bufs++;
2902 while ((mbuf = mbuf->next) != NULL) {
2903 seg_len = mbuf->data_len;
2905 /* Skip mbufs if whole data is pushed as a header */
2906 if (unlikely(delta > seg_len)) {
2911 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2912 ena_buf->len = seg_len - delta;
2914 tx_info->num_of_bufs++;
2920 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2922 struct ena_tx_buffer *tx_info;
2923 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2924 uint16_t next_to_use;
2925 uint16_t header_len;
2931 /* Checking for space for 2 additional metadata descriptors due to
2932 * possible header split and metadata descriptor
2934 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2935 mbuf->nb_segs + 2)) {
2936 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2937 return ENA_COM_NO_MEM;
2940 next_to_use = tx_ring->next_to_use;
2942 req_id = tx_ring->empty_tx_reqs[next_to_use];
2943 tx_info = &tx_ring->tx_buffer_info[req_id];
2944 tx_info->num_of_bufs = 0;
2945 RTE_ASSERT(tx_info->mbuf == NULL);
2947 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2949 ena_tx_ctx.ena_bufs = tx_info->bufs;
2950 ena_tx_ctx.push_header = push_header;
2951 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2952 ena_tx_ctx.req_id = req_id;
2953 ena_tx_ctx.header_len = header_len;
2955 /* Set Tx offloads flags, if applicable */
2956 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2957 tx_ring->disable_meta_caching);
2959 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2962 "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2964 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2965 tx_ring->tx_stats.doorbells++;
2966 tx_ring->pkts_without_db = false;
2969 /* prepare the packet's descriptors to dma engine */
2970 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2973 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2974 ++tx_ring->tx_stats.prepare_ctx_err;
2975 tx_ring->adapter->reset_reason =
2976 ENA_REGS_RESET_DRIVER_INVALID_STATE;
2977 tx_ring->adapter->trigger_reset = true;
2981 tx_info->tx_descs = nb_hw_desc;
2982 tx_info->timestamp = rte_get_timer_cycles();
2984 tx_ring->tx_stats.cnt++;
2985 tx_ring->tx_stats.bytes += mbuf->pkt_len;
2987 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2988 tx_ring->size_mask);
2993 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2995 unsigned int total_tx_descs = 0;
2996 uint16_t cleanup_budget;
2997 uint16_t next_to_clean = tx_ring->next_to_clean;
2999 /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
3000 cleanup_budget = tx_ring->size_mask;
3002 while (likely(total_tx_descs < cleanup_budget)) {
3003 struct rte_mbuf *mbuf;
3004 struct ena_tx_buffer *tx_info;
3007 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
3010 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
3013 /* Get Tx info & store how many descs were processed */
3014 tx_info = &tx_ring->tx_buffer_info[req_id];
3015 tx_info->timestamp = 0;
3017 mbuf = tx_info->mbuf;
3018 rte_pktmbuf_free(mbuf);
3020 tx_info->mbuf = NULL;
3021 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
3023 total_tx_descs += tx_info->tx_descs;
3025 /* Put back descriptor to the ring for reuse */
3026 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
3027 tx_ring->size_mask);
3030 if (likely(total_tx_descs > 0)) {
3031 /* acknowledge completion of sent packets */
3032 tx_ring->next_to_clean = next_to_clean;
3033 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
3034 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
3037 /* Notify completion handler that the cleanup was just called */
3038 tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
3041 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
3044 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
3046 uint16_t sent_idx = 0;
3048 #ifdef RTE_ETHDEV_DEBUG_TX
3049 /* Check adapter state */
3050 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
3052 "Trying to xmit pkts while device is NOT running\n");
3057 available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3058 if (available_desc < tx_ring->tx_free_thresh)
3059 ena_tx_cleanup(tx_ring);
3061 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
3062 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
3064 tx_ring->pkts_without_db = true;
3065 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
3066 tx_ring->size_mask)]);
3069 /* If there are ready packets to be xmitted... */
3070 if (likely(tx_ring->pkts_without_db)) {
3071 /* ...let HW do its best :-) */
3072 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
3073 tx_ring->tx_stats.doorbells++;
3074 tx_ring->pkts_without_db = false;
3077 tx_ring->tx_stats.available_desc =
3078 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3079 tx_ring->tx_stats.tx_poll++;
3084 int ena_copy_eni_stats(struct ena_adapter *adapter, struct ena_stats_eni *stats)
3088 rte_spinlock_lock(&adapter->admin_lock);
3089 /* Retrieve and store the latest statistics from the AQ. This ensures
3090 * that previous value is returned in case of a com error.
3092 rc = ENA_PROXY(adapter, ena_com_get_eni_stats, &adapter->ena_dev,
3093 (struct ena_admin_eni_stats *)stats);
3094 rte_spinlock_unlock(&adapter->admin_lock);
3096 if (rc == ENA_COM_UNSUPPORTED) {
3098 "Retrieving ENI metrics is not supported\n");
3100 PMD_DRV_LOG(WARNING,
3101 "Failed to get ENI metrics, rc: %d\n", rc);
3110 * DPDK callback to retrieve names of extended device statistics
3113 * Pointer to Ethernet device structure.
3114 * @param[out] xstats_names
3115 * Buffer to insert names into.
3120 * Number of xstats names.
3122 static int ena_xstats_get_names(struct rte_eth_dev *dev,
3123 struct rte_eth_xstat_name *xstats_names,
3126 unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3127 unsigned int stat, i, count = 0;
3129 if (n < xstats_count || !xstats_names)
3130 return xstats_count;
3132 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
3133 strcpy(xstats_names[count].name,
3134 ena_stats_global_strings[stat].name);
3136 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
3137 strcpy(xstats_names[count].name,
3138 ena_stats_eni_strings[stat].name);
3140 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
3141 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
3142 snprintf(xstats_names[count].name,
3143 sizeof(xstats_names[count].name),
3145 ena_stats_rx_strings[stat].name);
3147 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
3148 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
3149 snprintf(xstats_names[count].name,
3150 sizeof(xstats_names[count].name),
3152 ena_stats_tx_strings[stat].name);
3154 return xstats_count;
3158 * DPDK callback to get extended device statistics.
3161 * Pointer to Ethernet device structure.
3163 * Stats table output buffer.
3165 * The size of the stats table.
3168 * Number of xstats on success, negative on failure.
3170 static int ena_xstats_get(struct rte_eth_dev *dev,
3171 struct rte_eth_xstat *xstats,
3174 struct ena_adapter *adapter = dev->data->dev_private;
3175 unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3176 struct ena_stats_eni eni_stats;
3177 unsigned int stat, i, count = 0;
3181 if (n < xstats_count)
3182 return xstats_count;
3187 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
3188 stat_offset = ena_stats_global_strings[stat].stat_offset;
3189 stats_begin = &adapter->dev_stats;
3191 xstats[count].id = count;
3192 xstats[count].value = *((uint64_t *)
3193 ((char *)stats_begin + stat_offset));
3196 /* Even if the function below fails, we should copy previous (or initial
3197 * values) to keep structure of rte_eth_xstat consistent.
3199 ena_copy_eni_stats(adapter, &eni_stats);
3200 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
3201 stat_offset = ena_stats_eni_strings[stat].stat_offset;
3202 stats_begin = &eni_stats;
3204 xstats[count].id = count;
3205 xstats[count].value = *((uint64_t *)
3206 ((char *)stats_begin + stat_offset));
3209 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
3210 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
3211 stat_offset = ena_stats_rx_strings[stat].stat_offset;
3212 stats_begin = &adapter->rx_ring[i].rx_stats;
3214 xstats[count].id = count;
3215 xstats[count].value = *((uint64_t *)
3216 ((char *)stats_begin + stat_offset));
3220 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
3221 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
3222 stat_offset = ena_stats_tx_strings[stat].stat_offset;
3223 stats_begin = &adapter->tx_ring[i].rx_stats;
3225 xstats[count].id = count;
3226 xstats[count].value = *((uint64_t *)
3227 ((char *)stats_begin + stat_offset));
3234 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
3235 const uint64_t *ids,
3239 struct ena_adapter *adapter = dev->data->dev_private;
3240 struct ena_stats_eni eni_stats;
3242 uint64_t rx_entries, tx_entries;
3246 bool was_eni_copied = false;
3248 for (i = 0; i < n; ++i) {
3250 /* Check if id belongs to global statistics */
3251 if (id < ENA_STATS_ARRAY_GLOBAL) {
3252 values[i] = *((uint64_t *)&adapter->dev_stats + id);
3257 /* Check if id belongs to ENI statistics */
3258 id -= ENA_STATS_ARRAY_GLOBAL;
3259 if (id < ENA_STATS_ARRAY_ENI) {
3260 /* Avoid reading ENI stats multiple times in a single
3261 * function call, as it requires communication with the
3264 if (!was_eni_copied) {
3265 was_eni_copied = true;
3266 ena_copy_eni_stats(adapter, &eni_stats);
3268 values[i] = *((uint64_t *)&eni_stats + id);
3273 /* Check if id belongs to rx queue statistics */
3274 id -= ENA_STATS_ARRAY_ENI;
3275 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
3276 if (id < rx_entries) {
3277 qid = id % dev->data->nb_rx_queues;
3278 id /= dev->data->nb_rx_queues;
3279 values[i] = *((uint64_t *)
3280 &adapter->rx_ring[qid].rx_stats + id);
3284 /* Check if id belongs to rx queue statistics */
3286 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
3287 if (id < tx_entries) {
3288 qid = id % dev->data->nb_tx_queues;
3289 id /= dev->data->nb_tx_queues;
3290 values[i] = *((uint64_t *)
3291 &adapter->tx_ring[qid].tx_stats + id);
3300 static int ena_process_bool_devarg(const char *key,
3304 struct ena_adapter *adapter = opaque;
3307 /* Parse the value. */
3308 if (strcmp(value, "1") == 0) {
3310 } else if (strcmp(value, "0") == 0) {
3314 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3319 /* Now, assign it to the proper adapter field. */
3320 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3321 adapter->use_large_llq_hdr = bool_value;
3326 static int ena_parse_devargs(struct ena_adapter *adapter,
3327 struct rte_devargs *devargs)
3329 static const char * const allowed_args[] = {
3330 ENA_DEVARG_LARGE_LLQ_HDR,
3333 struct rte_kvargs *kvlist;
3336 if (devargs == NULL)
3339 kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3340 if (kvlist == NULL) {
3341 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3346 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3347 ena_process_bool_devarg, adapter);
3349 rte_kvargs_free(kvlist);
3354 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3356 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3357 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3359 uint16_t vectors_nb, i;
3360 bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3362 if (!rx_intr_requested)
3365 if (!rte_intr_cap_multiple(intr_handle)) {
3367 "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3371 /* Disable interrupt mapping before the configuration starts. */
3372 rte_intr_disable(intr_handle);
3374 /* Verify if there are enough vectors available. */
3375 vectors_nb = dev->data->nb_rx_queues;
3376 if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3378 "Too many Rx interrupts requested, maximum number: %d\n",
3379 RTE_MAX_RXTX_INTR_VEC_ID);
3384 /* Allocate the vector list */
3385 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3386 dev->data->nb_rx_queues)) {
3388 "Failed to allocate interrupt vector for %d queues\n",
3389 dev->data->nb_rx_queues);
3394 rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3398 if (!rte_intr_allow_others(intr_handle)) {
3400 "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3401 goto disable_intr_efd;
3404 for (i = 0; i < vectors_nb; ++i)
3405 if (rte_intr_vec_list_index_set(intr_handle, i,
3406 RTE_INTR_VEC_RXTX_OFFSET + i))
3407 goto disable_intr_efd;
3409 rte_intr_enable(intr_handle);
3413 rte_intr_efd_disable(intr_handle);
3415 rte_intr_vec_list_free(intr_handle);
3417 rte_intr_enable(intr_handle);
3421 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3425 struct ena_adapter *adapter = dev->data->dev_private;
3426 struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3427 struct ena_eth_io_intr_reg intr_reg;
3429 ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3430 ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3433 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3436 ena_rx_queue_intr_set(dev, queue_id, true);
3441 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3444 ena_rx_queue_intr_set(dev, queue_id, false);
3449 static int ena_configure_aenq(struct ena_adapter *adapter)
3451 uint32_t aenq_groups = adapter->all_aenq_groups;
3454 /* All_aenq_groups holds all AENQ functions supported by the device and
3455 * the HW, so at first we need to be sure the LSC request is valid.
3457 if (adapter->edev_data->dev_conf.intr_conf.lsc != 0) {
3458 if (!(aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) {
3460 "LSC requested, but it's not supported by the AENQ\n");
3464 /* If LSC wasn't enabled by the app, let's enable all supported
3465 * AENQ procedures except the LSC.
3467 aenq_groups &= ~BIT(ENA_ADMIN_LINK_CHANGE);
3470 rc = ena_com_set_aenq_config(&adapter->ena_dev, aenq_groups);
3472 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc=%d\n", rc);
3476 adapter->active_aenq_groups = aenq_groups;
3481 int ena_mp_indirect_table_set(struct ena_adapter *adapter)
3483 return ENA_PROXY(adapter, ena_com_indirect_table_set, &adapter->ena_dev);
3486 int ena_mp_indirect_table_get(struct ena_adapter *adapter,
3487 uint32_t *indirect_table)
3489 return ENA_PROXY(adapter, ena_com_indirect_table_get, &adapter->ena_dev,
3493 /*********************************************************************
3494 * ena_plat_dpdk.h functions implementations
3495 *********************************************************************/
3497 const struct rte_memzone *
3498 ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size,
3499 int socket_id, unsigned int alignment, void **virt_addr,
3500 dma_addr_t *phys_addr)
3502 char z_name[RTE_MEMZONE_NAMESIZE];
3503 struct ena_adapter *adapter = data->dev_private;
3504 const struct rte_memzone *memzone;
3507 rc = snprintf(z_name, RTE_MEMZONE_NAMESIZE, "ena_p%d_mz%" PRIu64 "",
3508 data->port_id, adapter->memzone_cnt);
3509 if (rc >= RTE_MEMZONE_NAMESIZE) {
3511 "Name for the ena_com memzone is too long. Port: %d, mz_num: %" PRIu64 "\n",
3512 data->port_id, adapter->memzone_cnt);
3515 adapter->memzone_cnt++;
3517 memzone = rte_memzone_reserve_aligned(z_name, size, socket_id,
3518 RTE_MEMZONE_IOVA_CONTIG, alignment);
3519 if (memzone == NULL) {
3520 PMD_DRV_LOG(ERR, "Failed to allocate ena_com memzone: %s\n",
3525 memset(memzone->addr, 0, size);
3526 *virt_addr = memzone->addr;
3527 *phys_addr = memzone->iova;
3539 /*********************************************************************
3541 *********************************************************************/
3542 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3543 struct rte_pci_device *pci_dev)
3545 return rte_eth_dev_pci_generic_probe(pci_dev,
3546 sizeof(struct ena_adapter), eth_ena_dev_init);
3549 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3551 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3554 static struct rte_pci_driver rte_ena_pmd = {
3555 .id_table = pci_id_ena_map,
3556 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3557 RTE_PCI_DRV_WC_ACTIVATE,
3558 .probe = eth_ena_pci_probe,
3559 .remove = eth_ena_pci_remove,
3562 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3563 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3564 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3565 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3566 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3567 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3568 #ifdef RTE_ETHDEV_DEBUG_RX
3569 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3571 #ifdef RTE_ETHDEV_DEBUG_TX
3572 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3574 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3576 /******************************************************************************
3577 ******************************** AENQ Handlers *******************************
3578 *****************************************************************************/
3579 static void ena_update_on_link_change(void *adapter_data,
3580 struct ena_admin_aenq_entry *aenq_e)
3582 struct rte_eth_dev *eth_dev = adapter_data;
3583 struct ena_adapter *adapter = eth_dev->data->dev_private;
3584 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3587 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3589 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3590 adapter->link_status = status;
3592 ena_link_update(eth_dev, 0);
3593 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3596 static void ena_notification(void *adapter_data,
3597 struct ena_admin_aenq_entry *aenq_e)
3599 struct rte_eth_dev *eth_dev = adapter_data;
3600 struct ena_adapter *adapter = eth_dev->data->dev_private;
3601 struct ena_admin_ena_hw_hints *hints;
3603 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3604 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3605 aenq_e->aenq_common_desc.group,
3606 ENA_ADMIN_NOTIFICATION);
3608 switch (aenq_e->aenq_common_desc.syndrome) {
3609 case ENA_ADMIN_UPDATE_HINTS:
3610 hints = (struct ena_admin_ena_hw_hints *)
3611 (&aenq_e->inline_data_w4);
3612 ena_update_hints(adapter, hints);
3615 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3616 aenq_e->aenq_common_desc.syndrome);
3620 static void ena_keep_alive(void *adapter_data,
3621 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3623 struct rte_eth_dev *eth_dev = adapter_data;
3624 struct ena_adapter *adapter = eth_dev->data->dev_private;
3625 struct ena_admin_aenq_keep_alive_desc *desc;
3629 adapter->timestamp_wd = rte_get_timer_cycles();
3631 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3632 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3633 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3635 adapter->drv_stats->rx_drops = rx_drops;
3636 adapter->dev_stats.tx_drops = tx_drops;
3640 * This handler will called for unknown event group or unimplemented handlers
3642 static void unimplemented_aenq_handler(__rte_unused void *data,
3643 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3646 "Unknown event was received or event with unimplemented handler\n");
3649 static struct ena_aenq_handlers aenq_handlers = {
3651 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3652 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3653 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3655 .unimplemented_handler = unimplemented_aenq_handler
3658 /*********************************************************************
3659 * Multi-Process communication request handling (in primary)
3660 *********************************************************************/
3662 ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)
3664 const struct ena_mp_body *req =
3665 (const struct ena_mp_body *)mp_msg->param;
3666 struct ena_adapter *adapter;
3667 struct ena_com_dev *ena_dev;
3668 struct ena_mp_body *rsp;
3669 struct rte_mp_msg mp_rsp;
3670 struct rte_eth_dev *dev;
3673 rsp = (struct ena_mp_body *)&mp_rsp.param;
3674 mp_msg_init(&mp_rsp, req->type, req->port_id);
3676 if (!rte_eth_dev_is_valid_port(req->port_id)) {
3679 PMD_DRV_LOG(ERR, "Unknown port %d in request %d\n",
3680 req->port_id, req->type);
3683 dev = &rte_eth_devices[req->port_id];
3684 adapter = dev->data->dev_private;
3685 ena_dev = &adapter->ena_dev;
3687 switch (req->type) {
3688 case ENA_MP_DEV_STATS_GET:
3689 res = ena_com_get_dev_basic_stats(ena_dev,
3690 &adapter->basic_stats);
3692 case ENA_MP_ENI_STATS_GET:
3693 res = ena_com_get_eni_stats(ena_dev,
3694 (struct ena_admin_eni_stats *)&adapter->eni_stats);
3696 case ENA_MP_MTU_SET:
3697 res = ena_com_set_dev_mtu(ena_dev, req->args.mtu);
3699 case ENA_MP_IND_TBL_GET:
3700 res = ena_com_indirect_table_get(ena_dev,
3701 adapter->indirect_table);
3703 case ENA_MP_IND_TBL_SET:
3704 res = ena_com_indirect_table_set(ena_dev);
3707 PMD_DRV_LOG(ERR, "Unknown request type %d\n", req->type);
3713 /* Save processing result in the reply */
3715 /* Return just IPC processing status */
3716 return rte_mp_reply(&mp_rsp, peer);