4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 0
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 #define ENA_MAX_RING_DESC ENA_DEFAULT_RING_SIZE
89 #define ENA_MIN_RING_DESC 128
91 enum ethtool_stringset {
97 char name[ETH_GSTRING_LEN];
101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
103 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
106 #define ENA_STAT_ENTRY(stat, stat_type) { \
108 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
111 #define ENA_STAT_RX_ENTRY(stat) \
112 ENA_STAT_ENTRY(stat, rx)
114 #define ENA_STAT_TX_ENTRY(stat) \
115 ENA_STAT_ENTRY(stat, tx)
117 #define ENA_STAT_GLOBAL_ENTRY(stat) \
118 ENA_STAT_ENTRY(stat, dev)
121 * Each rte_memzone should have unique name.
122 * To satisfy it, count number of allocation and add it to name.
124 uint32_t ena_alloc_cnt;
126 static const struct ena_stats ena_stats_global_strings[] = {
127 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
128 ENA_STAT_GLOBAL_ENTRY(io_suspend),
129 ENA_STAT_GLOBAL_ENTRY(io_resume),
130 ENA_STAT_GLOBAL_ENTRY(wd_expired),
131 ENA_STAT_GLOBAL_ENTRY(interface_up),
132 ENA_STAT_GLOBAL_ENTRY(interface_down),
133 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
136 static const struct ena_stats ena_stats_tx_strings[] = {
137 ENA_STAT_TX_ENTRY(cnt),
138 ENA_STAT_TX_ENTRY(bytes),
139 ENA_STAT_TX_ENTRY(queue_stop),
140 ENA_STAT_TX_ENTRY(queue_wakeup),
141 ENA_STAT_TX_ENTRY(dma_mapping_err),
142 ENA_STAT_TX_ENTRY(linearize),
143 ENA_STAT_TX_ENTRY(linearize_failed),
144 ENA_STAT_TX_ENTRY(tx_poll),
145 ENA_STAT_TX_ENTRY(doorbells),
146 ENA_STAT_TX_ENTRY(prepare_ctx_err),
147 ENA_STAT_TX_ENTRY(missing_tx_comp),
148 ENA_STAT_TX_ENTRY(bad_req_id),
151 static const struct ena_stats ena_stats_rx_strings[] = {
152 ENA_STAT_RX_ENTRY(cnt),
153 ENA_STAT_RX_ENTRY(bytes),
154 ENA_STAT_RX_ENTRY(refil_partial),
155 ENA_STAT_RX_ENTRY(bad_csum),
156 ENA_STAT_RX_ENTRY(page_alloc_fail),
157 ENA_STAT_RX_ENTRY(skb_alloc_fail),
158 ENA_STAT_RX_ENTRY(dma_mapping_err),
159 ENA_STAT_RX_ENTRY(bad_desc_num),
160 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
163 static const struct ena_stats ena_stats_ena_com_strings[] = {
164 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
165 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
166 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
167 ENA_STAT_ENA_COM_ENTRY(out_of_space),
168 ENA_STAT_ENA_COM_ENTRY(no_completion),
171 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
172 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
173 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
177 DEV_TX_OFFLOAD_UDP_CKSUM |\
178 DEV_TX_OFFLOAD_IPV4_CKSUM |\
179 DEV_TX_OFFLOAD_TCP_TSO)
180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
184 /** Vendor ID used by Amazon devices */
185 #define PCI_VENDOR_ID_AMAZON 0x1D0F
186 /** Amazon devices */
187 #define PCI_DEVICE_ID_ENA_VF 0xEC20
188 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
190 #define ENA_TX_OFFLOAD_MASK (\
195 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
196 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
198 int ena_logtype_init;
199 int ena_logtype_driver;
201 static const struct rte_pci_id pci_id_ena_map[] = {
202 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
203 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
207 static struct ena_aenq_handlers aenq_handlers;
209 static int ena_device_init(struct ena_com_dev *ena_dev,
210 struct ena_com_dev_get_features_ctx *get_feat_ctx,
212 static int ena_dev_configure(struct rte_eth_dev *dev);
213 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
215 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
217 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
218 uint16_t nb_desc, unsigned int socket_id,
219 const struct rte_eth_txconf *tx_conf);
220 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
221 uint16_t nb_desc, unsigned int socket_id,
222 const struct rte_eth_rxconf *rx_conf,
223 struct rte_mempool *mp);
224 static uint16_t eth_ena_recv_pkts(void *rx_queue,
225 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
226 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
227 static void ena_init_rings(struct ena_adapter *adapter);
228 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
229 static int ena_start(struct rte_eth_dev *dev);
230 static void ena_stop(struct rte_eth_dev *dev);
231 static void ena_close(struct rte_eth_dev *dev);
232 static int ena_dev_reset(struct rte_eth_dev *dev);
233 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
234 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
235 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
236 static void ena_rx_queue_release(void *queue);
237 static void ena_tx_queue_release(void *queue);
238 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
239 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
240 static int ena_link_update(struct rte_eth_dev *dev,
241 int wait_to_complete);
242 static int ena_queue_restart(struct ena_ring *ring);
243 static int ena_queue_restart_all(struct rte_eth_dev *dev,
244 enum ena_ring_type ring_type);
245 static void ena_stats_restart(struct rte_eth_dev *dev);
246 static void ena_infos_get(struct rte_eth_dev *dev,
247 struct rte_eth_dev_info *dev_info);
248 static int ena_rss_reta_update(struct rte_eth_dev *dev,
249 struct rte_eth_rss_reta_entry64 *reta_conf,
251 static int ena_rss_reta_query(struct rte_eth_dev *dev,
252 struct rte_eth_rss_reta_entry64 *reta_conf,
254 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
255 static void ena_interrupt_handler_rte(void *cb_arg);
256 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
258 static const struct eth_dev_ops ena_dev_ops = {
259 .dev_configure = ena_dev_configure,
260 .dev_infos_get = ena_infos_get,
261 .rx_queue_setup = ena_rx_queue_setup,
262 .tx_queue_setup = ena_tx_queue_setup,
263 .dev_start = ena_start,
264 .dev_stop = ena_stop,
265 .link_update = ena_link_update,
266 .stats_get = ena_stats_get,
267 .mtu_set = ena_mtu_set,
268 .rx_queue_release = ena_rx_queue_release,
269 .tx_queue_release = ena_tx_queue_release,
270 .dev_close = ena_close,
271 .dev_reset = ena_dev_reset,
272 .reta_update = ena_rss_reta_update,
273 .reta_query = ena_rss_reta_query,
276 #define NUMA_NO_NODE SOCKET_ID_ANY
278 static inline int ena_cpu_to_node(int cpu)
280 struct rte_config *config = rte_eal_get_configuration();
281 struct rte_fbarray *arr = &config->mem_config->memzones;
282 const struct rte_memzone *mz;
284 if (unlikely(cpu >= RTE_MAX_MEMZONE))
287 mz = rte_fbarray_get(arr, cpu);
289 return mz->socket_id;
292 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
293 struct ena_com_rx_ctx *ena_rx_ctx)
295 uint64_t ol_flags = 0;
296 uint32_t packet_type = 0;
298 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
299 packet_type |= RTE_PTYPE_L4_TCP;
300 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
301 packet_type |= RTE_PTYPE_L4_UDP;
303 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
304 packet_type |= RTE_PTYPE_L3_IPV4;
305 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
306 packet_type |= RTE_PTYPE_L3_IPV6;
308 if (unlikely(ena_rx_ctx->l4_csum_err))
309 ol_flags |= PKT_RX_L4_CKSUM_BAD;
310 if (unlikely(ena_rx_ctx->l3_csum_err))
311 ol_flags |= PKT_RX_IP_CKSUM_BAD;
313 mbuf->ol_flags = ol_flags;
314 mbuf->packet_type = packet_type;
317 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
318 struct ena_com_tx_ctx *ena_tx_ctx,
319 uint64_t queue_offloads)
321 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
323 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
324 (queue_offloads & QUEUE_OFFLOADS)) {
325 /* check if TSO is required */
326 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
327 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
328 ena_tx_ctx->tso_enable = true;
330 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
333 /* check if L3 checksum is needed */
334 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
335 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
336 ena_tx_ctx->l3_csum_enable = true;
338 if (mbuf->ol_flags & PKT_TX_IPV6) {
339 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
341 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
343 /* set don't fragment (DF) flag */
344 if (mbuf->packet_type &
345 (RTE_PTYPE_L4_NONFRAG
346 | RTE_PTYPE_INNER_L4_NONFRAG))
347 ena_tx_ctx->df = true;
350 /* check if L4 checksum is needed */
351 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
352 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
353 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
354 ena_tx_ctx->l4_csum_enable = true;
355 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
356 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
357 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
358 ena_tx_ctx->l4_csum_enable = true;
360 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
361 ena_tx_ctx->l4_csum_enable = false;
364 ena_meta->mss = mbuf->tso_segsz;
365 ena_meta->l3_hdr_len = mbuf->l3_len;
366 ena_meta->l3_hdr_offset = mbuf->l2_len;
368 ena_tx_ctx->meta_valid = true;
370 ena_tx_ctx->meta_valid = false;
374 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
376 if (likely(req_id < rx_ring->ring_size))
379 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
381 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
382 rx_ring->adapter->trigger_reset = true;
387 static void ena_config_host_info(struct ena_com_dev *ena_dev)
389 struct ena_admin_host_info *host_info;
392 /* Allocate only the host info */
393 rc = ena_com_allocate_host_info(ena_dev);
395 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
399 host_info = ena_dev->host_attr.host_info;
401 host_info->os_type = ENA_ADMIN_OS_DPDK;
402 host_info->kernel_ver = RTE_VERSION;
403 snprintf((char *)host_info->kernel_ver_str,
404 sizeof(host_info->kernel_ver_str),
405 "%s", rte_version());
406 host_info->os_dist = RTE_VERSION;
407 snprintf((char *)host_info->os_dist_str,
408 sizeof(host_info->os_dist_str),
409 "%s", rte_version());
410 host_info->driver_version =
411 (DRV_MODULE_VER_MAJOR) |
412 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
413 (DRV_MODULE_VER_SUBMINOR <<
414 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
416 rc = ena_com_set_host_attributes(ena_dev);
418 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
419 if (rc != -ENA_COM_UNSUPPORTED)
426 ena_com_delete_host_info(ena_dev);
430 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
432 if (sset != ETH_SS_STATS)
435 /* Workaround for clang:
436 * touch internal structures to prevent
439 ENA_TOUCH(ena_stats_global_strings);
440 ENA_TOUCH(ena_stats_tx_strings);
441 ENA_TOUCH(ena_stats_rx_strings);
442 ENA_TOUCH(ena_stats_ena_com_strings);
444 return dev->data->nb_tx_queues *
445 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
446 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
449 static void ena_config_debug_area(struct ena_adapter *adapter)
454 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
456 RTE_LOG(ERR, PMD, "SS count is negative\n");
460 /* allocate 32 bytes for each string and 64bit for the value */
461 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
463 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
465 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
469 rc = ena_com_set_host_attributes(&adapter->ena_dev);
471 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
472 if (rc != -ENA_COM_UNSUPPORTED)
478 ena_com_delete_debug_area(&adapter->ena_dev);
481 static void ena_close(struct rte_eth_dev *dev)
483 struct ena_adapter *adapter =
484 (struct ena_adapter *)(dev->data->dev_private);
487 adapter->state = ENA_ADAPTER_STATE_CLOSED;
489 ena_rx_queue_release_all(dev);
490 ena_tx_queue_release_all(dev);
494 ena_dev_reset(struct rte_eth_dev *dev)
496 struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
497 struct rte_eth_dev *eth_dev;
498 struct rte_pci_device *pci_dev;
499 struct rte_intr_handle *intr_handle;
500 struct ena_com_dev *ena_dev;
501 struct ena_com_dev_get_features_ctx get_feat_ctx;
502 struct ena_adapter *adapter;
507 adapter = (struct ena_adapter *)(dev->data->dev_private);
508 ena_dev = &adapter->ena_dev;
509 eth_dev = adapter->rte_dev;
510 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
511 intr_handle = &pci_dev->intr_handle;
512 nb_queues = eth_dev->data->nb_rx_queues;
514 ena_com_set_admin_running_state(ena_dev, false);
516 ena_com_dev_reset(ena_dev, adapter->reset_reason);
518 for (i = 0; i < nb_queues; i++)
519 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
521 ena_rx_queue_release_all(eth_dev);
522 ena_tx_queue_release_all(eth_dev);
524 rte_intr_disable(intr_handle);
526 ena_com_abort_admin_commands(ena_dev);
527 ena_com_wait_for_abort_completion(ena_dev);
528 ena_com_admin_destroy(ena_dev);
529 ena_com_mmio_reg_read_request_destroy(ena_dev);
531 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
533 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
536 adapter->wd_state = wd_state;
538 rte_intr_enable(intr_handle);
539 ena_com_set_admin_polling_mode(ena_dev, false);
540 ena_com_admin_aenq_enable(ena_dev);
542 for (i = 0; i < nb_queues; ++i)
543 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
546 for (i = 0; i < nb_queues; ++i)
547 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
549 adapter->trigger_reset = false;
554 static int ena_rss_reta_update(struct rte_eth_dev *dev,
555 struct rte_eth_rss_reta_entry64 *reta_conf,
558 struct ena_adapter *adapter =
559 (struct ena_adapter *)(dev->data->dev_private);
560 struct ena_com_dev *ena_dev = &adapter->ena_dev;
566 if ((reta_size == 0) || (reta_conf == NULL))
569 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
570 RTE_LOG(WARNING, PMD,
571 "indirection table %d is bigger than supported (%d)\n",
572 reta_size, ENA_RX_RSS_TABLE_SIZE);
577 for (i = 0 ; i < reta_size ; i++) {
578 /* each reta_conf is for 64 entries.
579 * to support 128 we use 2 conf of 64
581 conf_idx = i / RTE_RETA_GROUP_SIZE;
582 idx = i % RTE_RETA_GROUP_SIZE;
583 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
585 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
586 ret = ena_com_indirect_table_fill_entry(ena_dev,
589 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
591 "Cannot fill indirect table\n");
598 ret = ena_com_indirect_table_set(ena_dev);
599 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
600 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
605 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
606 __func__, reta_size, adapter->rte_dev->data->port_id);
611 /* Query redirection table. */
612 static int ena_rss_reta_query(struct rte_eth_dev *dev,
613 struct rte_eth_rss_reta_entry64 *reta_conf,
616 struct ena_adapter *adapter =
617 (struct ena_adapter *)(dev->data->dev_private);
618 struct ena_com_dev *ena_dev = &adapter->ena_dev;
621 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
625 if (reta_size == 0 || reta_conf == NULL ||
626 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
629 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
630 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
631 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
636 for (i = 0 ; i < reta_size ; i++) {
637 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
638 reta_idx = i % RTE_RETA_GROUP_SIZE;
639 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
640 reta_conf[reta_conf_idx].reta[reta_idx] =
641 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
647 static int ena_rss_init_default(struct ena_adapter *adapter)
649 struct ena_com_dev *ena_dev = &adapter->ena_dev;
650 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
654 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
656 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
660 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
661 val = i % nb_rx_queues;
662 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
663 ENA_IO_RXQ_IDX(val));
664 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
665 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
670 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
671 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
672 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
673 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
677 rc = ena_com_set_default_hash_ctrl(ena_dev);
678 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
679 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
683 rc = ena_com_indirect_table_set(ena_dev);
684 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
685 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
688 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
689 adapter->rte_dev->data->port_id);
694 ena_com_rss_destroy(ena_dev);
700 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
702 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
703 int nb_queues = dev->data->nb_rx_queues;
706 for (i = 0; i < nb_queues; i++)
707 ena_rx_queue_release(queues[i]);
710 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
712 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
713 int nb_queues = dev->data->nb_tx_queues;
716 for (i = 0; i < nb_queues; i++)
717 ena_tx_queue_release(queues[i]);
720 static void ena_rx_queue_release(void *queue)
722 struct ena_ring *ring = (struct ena_ring *)queue;
723 struct ena_adapter *adapter = ring->adapter;
726 ena_assert_msg(ring->configured,
727 "API violation - releasing not configured queue");
728 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
731 /* Destroy HW queue */
732 ena_qid = ENA_IO_RXQ_IDX(ring->id);
733 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
736 ena_rx_queue_release_bufs(ring);
738 /* Free ring resources */
739 if (ring->rx_buffer_info)
740 rte_free(ring->rx_buffer_info);
741 ring->rx_buffer_info = NULL;
743 if (ring->empty_rx_reqs)
744 rte_free(ring->empty_rx_reqs);
745 ring->empty_rx_reqs = NULL;
747 ring->configured = 0;
749 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
750 ring->port_id, ring->id);
753 static void ena_tx_queue_release(void *queue)
755 struct ena_ring *ring = (struct ena_ring *)queue;
756 struct ena_adapter *adapter = ring->adapter;
759 ena_assert_msg(ring->configured,
760 "API violation. Releasing not configured queue");
761 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
764 /* Destroy HW queue */
765 ena_qid = ENA_IO_TXQ_IDX(ring->id);
766 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
769 ena_tx_queue_release_bufs(ring);
771 /* Free ring resources */
772 if (ring->tx_buffer_info)
773 rte_free(ring->tx_buffer_info);
775 if (ring->empty_tx_reqs)
776 rte_free(ring->empty_tx_reqs);
778 ring->empty_tx_reqs = NULL;
779 ring->tx_buffer_info = NULL;
781 ring->configured = 0;
783 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
784 ring->port_id, ring->id);
787 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
789 unsigned int ring_mask = ring->ring_size - 1;
791 while (ring->next_to_clean != ring->next_to_use) {
793 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
796 rte_mbuf_raw_free(m);
798 ring->next_to_clean++;
802 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
806 for (i = 0; i < ring->ring_size; ++i) {
807 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
810 rte_pktmbuf_free(tx_buf->mbuf);
812 ring->next_to_clean++;
816 static int ena_link_update(struct rte_eth_dev *dev,
817 __rte_unused int wait_to_complete)
819 struct rte_eth_link *link = &dev->data->dev_link;
820 struct ena_adapter *adapter;
822 adapter = (struct ena_adapter *)(dev->data->dev_private);
824 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
825 link->link_speed = ETH_SPEED_NUM_10G;
826 link->link_duplex = ETH_LINK_FULL_DUPLEX;
831 static int ena_queue_restart_all(struct rte_eth_dev *dev,
832 enum ena_ring_type ring_type)
834 struct ena_adapter *adapter =
835 (struct ena_adapter *)(dev->data->dev_private);
836 struct ena_ring *queues = NULL;
841 if (ring_type == ENA_RING_TYPE_RX) {
842 queues = adapter->rx_ring;
843 nb_queues = dev->data->nb_rx_queues;
845 queues = adapter->tx_ring;
846 nb_queues = dev->data->nb_tx_queues;
848 for (i = 0; i < nb_queues; i++) {
849 if (queues[i].configured) {
850 if (ring_type == ENA_RING_TYPE_RX) {
852 dev->data->rx_queues[i] == &queues[i],
853 "Inconsistent state of rx queues\n");
856 dev->data->tx_queues[i] == &queues[i],
857 "Inconsistent state of tx queues\n");
860 rc = ena_queue_restart(&queues[i]);
864 "failed to restart queue %d type(%d)",
874 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
876 uint32_t max_frame_len = adapter->max_mtu;
878 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
879 DEV_RX_OFFLOAD_JUMBO_FRAME)
881 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
883 return max_frame_len;
886 static int ena_check_valid_conf(struct ena_adapter *adapter)
888 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
890 if (max_frame_len > adapter->max_mtu) {
891 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
899 ena_calc_queue_size(struct ena_com_dev *ena_dev,
900 u16 *max_tx_sgl_size,
901 struct ena_com_dev_get_features_ctx *get_feat_ctx)
903 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
905 queue_size = RTE_MIN(queue_size,
906 get_feat_ctx->max_queues.max_cq_depth);
907 queue_size = RTE_MIN(queue_size,
908 get_feat_ctx->max_queues.max_sq_depth);
910 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
911 queue_size = RTE_MIN(queue_size,
912 get_feat_ctx->max_queues.max_llq_depth);
914 /* Round down to power of 2 */
915 if (!rte_is_power_of_2(queue_size))
916 queue_size = rte_align32pow2(queue_size >> 1);
918 if (queue_size == 0) {
919 PMD_INIT_LOG(ERR, "Invalid queue size");
923 *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
924 get_feat_ctx->max_queues.max_packet_tx_descs);
929 static void ena_stats_restart(struct rte_eth_dev *dev)
931 struct ena_adapter *adapter =
932 (struct ena_adapter *)(dev->data->dev_private);
934 rte_atomic64_init(&adapter->drv_stats->ierrors);
935 rte_atomic64_init(&adapter->drv_stats->oerrors);
936 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
939 static int ena_stats_get(struct rte_eth_dev *dev,
940 struct rte_eth_stats *stats)
942 struct ena_admin_basic_stats ena_stats;
943 struct ena_adapter *adapter =
944 (struct ena_adapter *)(dev->data->dev_private);
945 struct ena_com_dev *ena_dev = &adapter->ena_dev;
948 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
951 memset(&ena_stats, 0, sizeof(ena_stats));
952 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
954 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
958 /* Set of basic statistics from ENA */
959 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
960 ena_stats.rx_pkts_low);
961 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
962 ena_stats.tx_pkts_low);
963 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
964 ena_stats.rx_bytes_low);
965 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
966 ena_stats.tx_bytes_low);
967 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
968 ena_stats.rx_drops_low);
970 /* Driver related stats */
971 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
972 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
973 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
977 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
979 struct ena_adapter *adapter;
980 struct ena_com_dev *ena_dev;
983 ena_assert_msg(dev->data != NULL, "Uninitialized device");
984 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
985 adapter = (struct ena_adapter *)(dev->data->dev_private);
987 ena_dev = &adapter->ena_dev;
988 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
990 if (mtu > ena_get_mtu_conf(adapter)) {
992 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
993 mtu, ena_get_mtu_conf(adapter));
998 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1000 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1002 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1008 static int ena_start(struct rte_eth_dev *dev)
1010 struct ena_adapter *adapter =
1011 (struct ena_adapter *)(dev->data->dev_private);
1015 rc = ena_check_valid_conf(adapter);
1019 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1023 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1027 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1028 ETH_MQ_RX_RSS_FLAG) {
1029 rc = ena_rss_init_default(adapter);
1034 ena_stats_restart(dev);
1036 adapter->timestamp_wd = rte_get_timer_cycles();
1037 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1039 ticks = rte_get_timer_hz();
1040 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1041 ena_timer_wd_callback, adapter);
1043 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1048 static void ena_stop(struct rte_eth_dev *dev)
1050 struct ena_adapter *adapter =
1051 (struct ena_adapter *)(dev->data->dev_private);
1053 rte_timer_stop_sync(&adapter->timer_wd);
1055 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1058 static int ena_queue_restart(struct ena_ring *ring)
1062 ena_assert_msg(ring->configured == 1,
1063 "Trying to restart unconfigured queue\n");
1065 ring->next_to_clean = 0;
1066 ring->next_to_use = 0;
1068 if (ring->type == ENA_RING_TYPE_TX)
1071 bufs_num = ring->ring_size - 1;
1072 rc = ena_populate_rx_queue(ring, bufs_num);
1073 if (rc != bufs_num) {
1074 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1081 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1084 __rte_unused unsigned int socket_id,
1085 const struct rte_eth_txconf *tx_conf)
1087 struct ena_com_create_io_ctx ctx =
1088 /* policy set to _HOST just to satisfy icc compiler */
1089 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1090 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1091 struct ena_ring *txq = NULL;
1092 struct ena_adapter *adapter =
1093 (struct ena_adapter *)(dev->data->dev_private);
1097 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1099 txq = &adapter->tx_ring[queue_idx];
1101 if (txq->configured) {
1103 "API violation. Queue %d is already configured\n",
1108 if (!rte_is_power_of_2(nb_desc)) {
1110 "Unsupported size of RX queue: %d is not a power of 2.",
1115 if (nb_desc > adapter->tx_ring_size) {
1117 "Unsupported size of TX queue (max size: %d)\n",
1118 adapter->tx_ring_size);
1122 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1124 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1126 ctx.msix_vector = -1; /* admin interrupts not used */
1127 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1128 ctx.queue_size = adapter->tx_ring_size;
1129 ctx.numa_node = ena_cpu_to_node(queue_idx);
1131 rc = ena_com_create_io_queue(ena_dev, &ctx);
1134 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1135 queue_idx, ena_qid, rc);
1137 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1138 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1140 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1141 &txq->ena_com_io_sq,
1142 &txq->ena_com_io_cq);
1145 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1147 ena_com_destroy_io_queue(ena_dev, ena_qid);
1151 txq->port_id = dev->data->port_id;
1152 txq->next_to_clean = 0;
1153 txq->next_to_use = 0;
1154 txq->ring_size = nb_desc;
1156 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1157 sizeof(struct ena_tx_buffer) *
1159 RTE_CACHE_LINE_SIZE);
1160 if (!txq->tx_buffer_info) {
1161 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1165 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1166 sizeof(u16) * txq->ring_size,
1167 RTE_CACHE_LINE_SIZE);
1168 if (!txq->empty_tx_reqs) {
1169 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1170 rte_free(txq->tx_buffer_info);
1173 for (i = 0; i < txq->ring_size; i++)
1174 txq->empty_tx_reqs[i] = i;
1176 if (tx_conf != NULL) {
1178 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1181 /* Store pointer to this queue in upper layer */
1182 txq->configured = 1;
1183 dev->data->tx_queues[queue_idx] = txq;
1188 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1191 __rte_unused unsigned int socket_id,
1192 __rte_unused const struct rte_eth_rxconf *rx_conf,
1193 struct rte_mempool *mp)
1195 struct ena_com_create_io_ctx ctx =
1196 /* policy set to _HOST just to satisfy icc compiler */
1197 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1198 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1199 struct ena_adapter *adapter =
1200 (struct ena_adapter *)(dev->data->dev_private);
1201 struct ena_ring *rxq = NULL;
1202 uint16_t ena_qid = 0;
1204 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1206 rxq = &adapter->rx_ring[queue_idx];
1207 if (rxq->configured) {
1209 "API violation. Queue %d is already configured\n",
1214 if (!rte_is_power_of_2(nb_desc)) {
1216 "Unsupported size of TX queue: %d is not a power of 2.",
1221 if (nb_desc > adapter->rx_ring_size) {
1223 "Unsupported size of RX queue (max size: %d)\n",
1224 adapter->rx_ring_size);
1228 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1231 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1232 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1233 ctx.msix_vector = -1; /* admin interrupts not used */
1234 ctx.queue_size = adapter->rx_ring_size;
1235 ctx.numa_node = ena_cpu_to_node(queue_idx);
1237 rc = ena_com_create_io_queue(ena_dev, &ctx);
1239 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1242 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1243 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1245 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1246 &rxq->ena_com_io_sq,
1247 &rxq->ena_com_io_cq);
1250 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1252 ena_com_destroy_io_queue(ena_dev, ena_qid);
1255 rxq->port_id = dev->data->port_id;
1256 rxq->next_to_clean = 0;
1257 rxq->next_to_use = 0;
1258 rxq->ring_size = nb_desc;
1261 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1262 sizeof(struct rte_mbuf *) * nb_desc,
1263 RTE_CACHE_LINE_SIZE);
1264 if (!rxq->rx_buffer_info) {
1265 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1269 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1270 sizeof(uint16_t) * nb_desc,
1271 RTE_CACHE_LINE_SIZE);
1272 if (!rxq->empty_rx_reqs) {
1273 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1274 rte_free(rxq->rx_buffer_info);
1275 rxq->rx_buffer_info = NULL;
1279 for (i = 0; i < nb_desc; i++)
1280 rxq->empty_tx_reqs[i] = i;
1282 /* Store pointer to this queue in upper layer */
1283 rxq->configured = 1;
1284 dev->data->rx_queues[queue_idx] = rxq;
1289 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1293 uint16_t ring_size = rxq->ring_size;
1294 uint16_t ring_mask = ring_size - 1;
1295 uint16_t next_to_use = rxq->next_to_use;
1296 uint16_t in_use, req_id;
1297 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1299 if (unlikely(!count))
1302 in_use = rxq->next_to_use - rxq->next_to_clean;
1303 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1305 count = RTE_MIN(count,
1306 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1308 /* get resources for incoming packets */
1309 rc = rte_mempool_get_bulk(rxq->mb_pool,
1310 (void **)(&mbufs[next_to_use & ring_mask]),
1312 if (unlikely(rc < 0)) {
1313 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1314 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1318 for (i = 0; i < count; i++) {
1319 uint16_t next_to_use_masked = next_to_use & ring_mask;
1320 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1321 struct ena_com_buf ebuf;
1323 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1325 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1326 /* prepare physical address for DMA transaction */
1327 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1328 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1329 /* pass resource to device */
1330 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1333 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1335 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1341 /* When we submitted free recources to device... */
1343 /* ...let HW know that it can fill buffers with data */
1345 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1347 rxq->next_to_use = next_to_use;
1353 static int ena_device_init(struct ena_com_dev *ena_dev,
1354 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1357 uint32_t aenq_groups;
1359 bool readless_supported;
1361 /* Initialize mmio registers */
1362 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1364 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1368 /* The PCIe configuration space revision id indicate if mmio reg
1371 readless_supported =
1372 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1373 & ENA_MMIO_DISABLE_REG_READ);
1374 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1377 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1379 RTE_LOG(ERR, PMD, "cannot reset device\n");
1380 goto err_mmio_read_less;
1383 /* check FW version */
1384 rc = ena_com_validate_version(ena_dev);
1386 RTE_LOG(ERR, PMD, "device version is too low\n");
1387 goto err_mmio_read_less;
1390 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1392 /* ENA device administration layer init */
1393 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1396 "cannot initialize ena admin queue with device\n");
1397 goto err_mmio_read_less;
1400 /* To enable the msix interrupts the driver needs to know the number
1401 * of queues. So the driver uses polling mode to retrieve this
1404 ena_com_set_admin_polling_mode(ena_dev, true);
1406 ena_config_host_info(ena_dev);
1408 /* Get Device Attributes and features */
1409 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1412 "cannot get attribute for ena device rc= %d\n", rc);
1413 goto err_admin_init;
1416 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1417 BIT(ENA_ADMIN_NOTIFICATION) |
1418 BIT(ENA_ADMIN_KEEP_ALIVE);
1420 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1421 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1423 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1424 goto err_admin_init;
1427 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1432 ena_com_admin_destroy(ena_dev);
1435 ena_com_mmio_reg_read_request_destroy(ena_dev);
1440 static void ena_interrupt_handler_rte(void *cb_arg)
1442 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1443 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1445 ena_com_admin_q_comp_intr_handler(ena_dev);
1446 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1447 ena_com_aenq_intr_handler(ena_dev, adapter);
1450 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1452 if (!adapter->wd_state)
1455 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1458 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1459 adapter->keep_alive_timeout)) {
1460 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1461 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1462 adapter->trigger_reset = true;
1466 /* Check if admin queue is enabled */
1467 static void check_for_admin_com_state(struct ena_adapter *adapter)
1469 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1470 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1471 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1472 adapter->trigger_reset = true;
1476 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1479 struct ena_adapter *adapter = (struct ena_adapter *)arg;
1480 struct rte_eth_dev *dev = adapter->rte_dev;
1482 check_for_missing_keep_alive(adapter);
1483 check_for_admin_com_state(adapter);
1485 if (unlikely(adapter->trigger_reset)) {
1486 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1487 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1492 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1494 struct rte_pci_device *pci_dev;
1495 struct rte_intr_handle *intr_handle;
1496 struct ena_adapter *adapter =
1497 (struct ena_adapter *)(eth_dev->data->dev_private);
1498 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1499 struct ena_com_dev_get_features_ctx get_feat_ctx;
1501 u16 tx_sgl_size = 0;
1503 static int adapters_found;
1506 memset(adapter, 0, sizeof(struct ena_adapter));
1507 ena_dev = &adapter->ena_dev;
1509 eth_dev->dev_ops = &ena_dev_ops;
1510 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1511 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1512 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1513 adapter->rte_eth_dev_data = eth_dev->data;
1514 adapter->rte_dev = eth_dev;
1516 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1519 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1520 adapter->pdev = pci_dev;
1522 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1523 pci_dev->addr.domain,
1525 pci_dev->addr.devid,
1526 pci_dev->addr.function);
1528 intr_handle = &pci_dev->intr_handle;
1530 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1531 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1533 if (!adapter->regs) {
1534 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1539 ena_dev->reg_bar = adapter->regs;
1540 ena_dev->dmadev = adapter->pdev;
1542 adapter->id_number = adapters_found;
1544 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1545 adapter->id_number);
1547 /* device specific initialization routine */
1548 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1550 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1553 adapter->wd_state = wd_state;
1555 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1556 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1558 queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1559 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1562 adapter->tx_ring_size = queue_size;
1563 adapter->rx_ring_size = queue_size;
1565 adapter->max_tx_sgl_size = tx_sgl_size;
1567 /* prepare ring structures */
1568 ena_init_rings(adapter);
1570 ena_config_debug_area(adapter);
1572 /* Set max MTU for this device */
1573 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1575 /* set device support for TSO */
1576 adapter->tso4_supported = get_feat_ctx.offload.tx &
1577 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1579 /* Copy MAC address and point DPDK to it */
1580 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1581 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1582 (struct ether_addr *)adapter->mac_addr);
1584 adapter->drv_stats = rte_zmalloc("adapter stats",
1585 sizeof(*adapter->drv_stats),
1586 RTE_CACHE_LINE_SIZE);
1587 if (!adapter->drv_stats) {
1588 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1592 rte_intr_callback_register(intr_handle,
1593 ena_interrupt_handler_rte,
1595 rte_intr_enable(intr_handle);
1596 ena_com_set_admin_polling_mode(ena_dev, false);
1597 ena_com_admin_aenq_enable(ena_dev);
1599 if (adapters_found == 0)
1600 rte_timer_subsystem_init();
1601 rte_timer_init(&adapter->timer_wd);
1604 adapter->state = ENA_ADAPTER_STATE_INIT;
1609 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1611 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1612 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1613 struct ena_adapter *adapter =
1614 (struct ena_adapter *)(eth_dev->data->dev_private);
1616 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1619 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1622 eth_dev->dev_ops = NULL;
1623 eth_dev->rx_pkt_burst = NULL;
1624 eth_dev->tx_pkt_burst = NULL;
1625 eth_dev->tx_pkt_prepare = NULL;
1627 rte_free(adapter->drv_stats);
1628 adapter->drv_stats = NULL;
1630 rte_intr_disable(intr_handle);
1631 rte_intr_callback_unregister(intr_handle,
1632 ena_interrupt_handler_rte,
1635 adapter->state = ENA_ADAPTER_STATE_FREE;
1640 static int ena_dev_configure(struct rte_eth_dev *dev)
1642 struct ena_adapter *adapter =
1643 (struct ena_adapter *)(dev->data->dev_private);
1645 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1647 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1648 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1652 static void ena_init_rings(struct ena_adapter *adapter)
1656 for (i = 0; i < adapter->num_queues; i++) {
1657 struct ena_ring *ring = &adapter->tx_ring[i];
1659 ring->configured = 0;
1660 ring->type = ENA_RING_TYPE_TX;
1661 ring->adapter = adapter;
1663 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1664 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1665 ring->sgl_size = adapter->max_tx_sgl_size;
1668 for (i = 0; i < adapter->num_queues; i++) {
1669 struct ena_ring *ring = &adapter->rx_ring[i];
1671 ring->configured = 0;
1672 ring->type = ENA_RING_TYPE_RX;
1673 ring->adapter = adapter;
1678 static void ena_infos_get(struct rte_eth_dev *dev,
1679 struct rte_eth_dev_info *dev_info)
1681 struct ena_adapter *adapter;
1682 struct ena_com_dev *ena_dev;
1683 struct ena_com_dev_get_features_ctx feat;
1684 uint64_t rx_feat = 0, tx_feat = 0;
1687 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1688 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1689 adapter = (struct ena_adapter *)(dev->data->dev_private);
1691 ena_dev = &adapter->ena_dev;
1692 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1694 dev_info->speed_capa =
1696 ETH_LINK_SPEED_2_5G |
1698 ETH_LINK_SPEED_10G |
1699 ETH_LINK_SPEED_25G |
1700 ETH_LINK_SPEED_40G |
1701 ETH_LINK_SPEED_50G |
1702 ETH_LINK_SPEED_100G;
1704 /* Get supported features from HW */
1705 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1708 "Cannot get attribute for ena device rc= %d\n", rc);
1712 /* Set Tx & Rx features available for device */
1713 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1714 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1716 if (feat.offload.tx &
1717 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1718 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1719 DEV_TX_OFFLOAD_UDP_CKSUM |
1720 DEV_TX_OFFLOAD_TCP_CKSUM;
1722 if (feat.offload.rx_supported &
1723 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1724 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1725 DEV_RX_OFFLOAD_UDP_CKSUM |
1726 DEV_RX_OFFLOAD_TCP_CKSUM;
1728 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1730 /* Inform framework about available features */
1731 dev_info->rx_offload_capa = rx_feat;
1732 dev_info->rx_queue_offload_capa = rx_feat;
1733 dev_info->tx_offload_capa = tx_feat;
1734 dev_info->tx_queue_offload_capa = tx_feat;
1736 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1737 dev_info->max_rx_pktlen = adapter->max_mtu;
1738 dev_info->max_mac_addrs = 1;
1740 dev_info->max_rx_queues = adapter->num_queues;
1741 dev_info->max_tx_queues = adapter->num_queues;
1742 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1744 adapter->tx_supported_offloads = tx_feat;
1745 adapter->rx_supported_offloads = rx_feat;
1747 dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1748 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1750 dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1751 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1752 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1753 feat.max_queues.max_packet_tx_descs);
1754 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1755 feat.max_queues.max_packet_tx_descs);
1758 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1761 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1762 unsigned int ring_size = rx_ring->ring_size;
1763 unsigned int ring_mask = ring_size - 1;
1764 uint16_t next_to_clean = rx_ring->next_to_clean;
1765 uint16_t desc_in_use = 0;
1767 unsigned int recv_idx = 0;
1768 struct rte_mbuf *mbuf = NULL;
1769 struct rte_mbuf *mbuf_head = NULL;
1770 struct rte_mbuf *mbuf_prev = NULL;
1771 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1772 unsigned int completed;
1774 struct ena_com_rx_ctx ena_rx_ctx;
1777 /* Check adapter state */
1778 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1780 "Trying to receive pkts while device is NOT running\n");
1784 desc_in_use = rx_ring->next_to_use - next_to_clean;
1785 if (unlikely(nb_pkts > desc_in_use))
1786 nb_pkts = desc_in_use;
1788 for (completed = 0; completed < nb_pkts; completed++) {
1791 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1792 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1793 ena_rx_ctx.descs = 0;
1794 /* receive packet context */
1795 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1796 rx_ring->ena_com_io_sq,
1799 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1803 if (unlikely(ena_rx_ctx.descs == 0))
1806 while (segments < ena_rx_ctx.descs) {
1807 req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1808 rc = validate_rx_req_id(rx_ring, req_id);
1812 mbuf = rx_buff_info[req_id];
1813 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1814 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1817 if (segments == 0) {
1818 mbuf->nb_segs = ena_rx_ctx.descs;
1819 mbuf->port = rx_ring->port_id;
1823 /* for multi-segment pkts create mbuf chain */
1824 mbuf_prev->next = mbuf;
1826 mbuf_head->pkt_len += mbuf->data_len;
1829 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1835 /* fill mbuf attributes if any */
1836 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1837 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1839 /* pass to DPDK application head mbuf */
1840 rx_pkts[recv_idx] = mbuf_head;
1844 rx_ring->next_to_clean = next_to_clean;
1846 desc_in_use = desc_in_use - completed + 1;
1847 /* Burst refill to save doorbells, memory barriers, const interval */
1848 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1849 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1855 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1861 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1862 struct ipv4_hdr *ip_hdr;
1864 uint16_t frag_field;
1866 for (i = 0; i != nb_pkts; i++) {
1868 ol_flags = m->ol_flags;
1870 if (!(ol_flags & PKT_TX_IPV4))
1873 /* If there was not L2 header length specified, assume it is
1874 * length of the ethernet header.
1876 if (unlikely(m->l2_len == 0))
1877 m->l2_len = sizeof(struct ether_hdr);
1879 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1881 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1883 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1884 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1886 /* If IPv4 header has DF flag enabled and TSO support is
1887 * disabled, partial chcecksum should not be calculated.
1889 if (!tx_ring->adapter->tso4_supported)
1893 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1894 (ol_flags & PKT_TX_L4_MASK) ==
1895 PKT_TX_SCTP_CKSUM) {
1896 rte_errno = -ENOTSUP;
1900 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1901 ret = rte_validate_tx_offload(m);
1908 /* In case we are supposed to TSO and have DF not set (DF=0)
1909 * hardware must be provided with partial checksum, otherwise
1910 * it will take care of necessary calculations.
1913 ret = rte_net_intel_cksum_flags_prepare(m,
1914 ol_flags & ~PKT_TX_TCP_SEG);
1924 static void ena_update_hints(struct ena_adapter *adapter,
1925 struct ena_admin_ena_hw_hints *hints)
1927 if (hints->admin_completion_tx_timeout)
1928 adapter->ena_dev.admin_queue.completion_timeout =
1929 hints->admin_completion_tx_timeout * 1000;
1931 if (hints->mmio_read_timeout)
1932 /* convert to usec */
1933 adapter->ena_dev.mmio_read.reg_read_to =
1934 hints->mmio_read_timeout * 1000;
1936 if (hints->driver_watchdog_timeout) {
1937 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1938 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1940 // Convert msecs to ticks
1941 adapter->keep_alive_timeout =
1942 (hints->driver_watchdog_timeout *
1943 rte_get_timer_hz()) / 1000;
1947 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
1948 struct rte_mbuf *mbuf)
1950 int num_segments, rc;
1952 num_segments = mbuf->nb_segs;
1954 if (likely(num_segments < tx_ring->sgl_size))
1957 rc = rte_pktmbuf_linearize(mbuf);
1959 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
1964 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1967 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1968 uint16_t next_to_use = tx_ring->next_to_use;
1969 uint16_t next_to_clean = tx_ring->next_to_clean;
1970 struct rte_mbuf *mbuf;
1971 unsigned int ring_size = tx_ring->ring_size;
1972 unsigned int ring_mask = ring_size - 1;
1973 struct ena_com_tx_ctx ena_tx_ctx;
1974 struct ena_tx_buffer *tx_info;
1975 struct ena_com_buf *ebuf;
1976 uint16_t rc, req_id, total_tx_descs = 0;
1977 uint16_t sent_idx = 0, empty_tx_reqs;
1980 /* Check adapter state */
1981 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1983 "Trying to xmit pkts while device is NOT running\n");
1987 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1988 if (nb_pkts > empty_tx_reqs)
1989 nb_pkts = empty_tx_reqs;
1991 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1992 mbuf = tx_pkts[sent_idx];
1994 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
1998 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1999 tx_info = &tx_ring->tx_buffer_info[req_id];
2000 tx_info->mbuf = mbuf;
2001 tx_info->num_of_bufs = 0;
2002 ebuf = tx_info->bufs;
2004 /* Prepare TX context */
2005 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2006 memset(&ena_tx_ctx.ena_meta, 0x0,
2007 sizeof(struct ena_com_tx_meta));
2008 ena_tx_ctx.ena_bufs = ebuf;
2009 ena_tx_ctx.req_id = req_id;
2010 if (tx_ring->tx_mem_queue_type ==
2011 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2012 /* prepare the push buffer with
2013 * virtual address of the data
2015 ena_tx_ctx.header_len =
2016 RTE_MIN(mbuf->data_len,
2017 tx_ring->tx_max_header_size);
2018 ena_tx_ctx.push_header =
2019 (void *)((char *)mbuf->buf_addr +
2021 } /* there's no else as we take advantage of memset zeroing */
2023 /* Set TX offloads flags, if applicable */
2024 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2026 if (unlikely(mbuf->ol_flags &
2027 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2028 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2030 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2032 /* Process first segment taking into
2033 * consideration pushed header
2035 if (mbuf->data_len > ena_tx_ctx.header_len) {
2036 ebuf->paddr = mbuf->buf_iova +
2038 ena_tx_ctx.header_len;
2039 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2041 tx_info->num_of_bufs++;
2044 while ((mbuf = mbuf->next) != NULL) {
2045 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2046 ebuf->len = mbuf->data_len;
2048 tx_info->num_of_bufs++;
2051 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2053 /* Write data to device */
2054 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2055 &ena_tx_ctx, &nb_hw_desc);
2059 tx_info->tx_descs = nb_hw_desc;
2064 /* If there are ready packets to be xmitted... */
2066 /* ...let HW do its best :-) */
2068 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2070 tx_ring->next_to_use = next_to_use;
2073 /* Clear complete packets */
2074 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2075 /* Get Tx info & store how many descs were processed */
2076 tx_info = &tx_ring->tx_buffer_info[req_id];
2077 total_tx_descs += tx_info->tx_descs;
2079 /* Free whole mbuf chain */
2080 mbuf = tx_info->mbuf;
2081 rte_pktmbuf_free(mbuf);
2082 tx_info->mbuf = NULL;
2084 /* Put back descriptor to the ring for reuse */
2085 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2088 /* If too many descs to clean, leave it for another run */
2089 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2093 if (total_tx_descs > 0) {
2094 /* acknowledge completion of sent packets */
2095 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2096 tx_ring->next_to_clean = next_to_clean;
2102 /*********************************************************************
2104 *********************************************************************/
2105 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2106 struct rte_pci_device *pci_dev)
2108 return rte_eth_dev_pci_generic_probe(pci_dev,
2109 sizeof(struct ena_adapter), eth_ena_dev_init);
2112 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2114 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2117 static struct rte_pci_driver rte_ena_pmd = {
2118 .id_table = pci_id_ena_map,
2119 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2120 .probe = eth_ena_pci_probe,
2121 .remove = eth_ena_pci_remove,
2124 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2125 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2126 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2128 RTE_INIT(ena_init_log);
2132 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2133 if (ena_logtype_init >= 0)
2134 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2135 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2136 if (ena_logtype_driver >= 0)
2137 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2140 /******************************************************************************
2141 ******************************** AENQ Handlers *******************************
2142 *****************************************************************************/
2143 static void ena_update_on_link_change(void *adapter_data,
2144 struct ena_admin_aenq_entry *aenq_e)
2146 struct rte_eth_dev *eth_dev;
2147 struct ena_adapter *adapter;
2148 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2151 adapter = (struct ena_adapter *)adapter_data;
2152 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2153 eth_dev = adapter->rte_dev;
2155 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2156 adapter->link_status = status;
2158 ena_link_update(eth_dev, 0);
2159 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2162 static void ena_notification(void *data,
2163 struct ena_admin_aenq_entry *aenq_e)
2165 struct ena_adapter *adapter = (struct ena_adapter *)data;
2166 struct ena_admin_ena_hw_hints *hints;
2168 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2169 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2170 aenq_e->aenq_common_desc.group,
2171 ENA_ADMIN_NOTIFICATION);
2173 switch (aenq_e->aenq_common_desc.syndrom) {
2174 case ENA_ADMIN_UPDATE_HINTS:
2175 hints = (struct ena_admin_ena_hw_hints *)
2176 (&aenq_e->inline_data_w4);
2177 ena_update_hints(adapter, hints);
2180 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2181 aenq_e->aenq_common_desc.syndrom);
2185 static void ena_keep_alive(void *adapter_data,
2186 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2188 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2190 adapter->timestamp_wd = rte_get_timer_cycles();
2194 * This handler will called for unknown event group or unimplemented handlers
2196 static void unimplemented_aenq_handler(__rte_unused void *data,
2197 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2199 // Unimplemented handler
2202 static struct ena_aenq_handlers aenq_handlers = {
2204 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2205 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2206 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2208 .unimplemented_handler = unimplemented_aenq_handler