drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    5
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 struct ena_stats {
  42         char name[ETH_GSTRING_LEN];
  43         int stat_offset;
  44 };
  45
  46 #define ENA_STAT_ENTRY(stat, stat_type) { \
  47         .name = #stat, \
  48         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  49 }
  50
  51 #define ENA_STAT_RX_ENTRY(stat) \
  52         ENA_STAT_ENTRY(stat, rx)
  53
  54 #define ENA_STAT_TX_ENTRY(stat) \
  55         ENA_STAT_ENTRY(stat, tx)
  56
  57 #define ENA_STAT_ENI_ENTRY(stat) \
  58         ENA_STAT_ENTRY(stat, eni)
  59
  60 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  61         ENA_STAT_ENTRY(stat, dev)
  62
  63 /* Device arguments */
  64 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  65 /* Timeout in seconds after which a single uncompleted Tx packet should be
  66  * considered as a missing.
  67  */
  68 #define ENA_DEVARG_MISS_TXC_TO "miss_txc_to"
  69
  70 /*
  71  * Each rte_memzone should have unique name.
  72  * To satisfy it, count number of allocation and add it to name.
  73  */
  74 rte_atomic64_t ena_alloc_cnt;
  75
  76 static const struct ena_stats ena_stats_global_strings[] = {
  77         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  78         ENA_STAT_GLOBAL_ENTRY(dev_start),
  79         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  80         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  81 };
  82
  83 static const struct ena_stats ena_stats_eni_strings[] = {
  84         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  85         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  86         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  87         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  88         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  89 };
  90
  91 static const struct ena_stats ena_stats_tx_strings[] = {
  92         ENA_STAT_TX_ENTRY(cnt),
  93         ENA_STAT_TX_ENTRY(bytes),
  94         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  95         ENA_STAT_TX_ENTRY(tx_poll),
  96         ENA_STAT_TX_ENTRY(doorbells),
  97         ENA_STAT_TX_ENTRY(bad_req_id),
  98         ENA_STAT_TX_ENTRY(available_desc),
  99         ENA_STAT_TX_ENTRY(missed_tx),
 100 };
 101
 102 static const struct ena_stats ena_stats_rx_strings[] = {
 103         ENA_STAT_RX_ENTRY(cnt),
 104         ENA_STAT_RX_ENTRY(bytes),
 105         ENA_STAT_RX_ENTRY(refill_partial),
 106         ENA_STAT_RX_ENTRY(l3_csum_bad),
 107         ENA_STAT_RX_ENTRY(l4_csum_bad),
 108         ENA_STAT_RX_ENTRY(l4_csum_good),
 109         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 110         ENA_STAT_RX_ENTRY(bad_desc_num),
 111         ENA_STAT_RX_ENTRY(bad_req_id),
 112 };
 113
 114 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 115 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 116 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 117 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 118
 119 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
 120                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
 121                         RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
 122                         RTE_ETH_TX_OFFLOAD_TCP_TSO)
 123 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
 124                        RTE_MBUF_F_TX_IP_CKSUM |\
 125                        RTE_MBUF_F_TX_TCP_SEG)
 126
 127 /** Vendor ID used by Amazon devices */
 128 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 129 /** Amazon devices */
 130 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 131 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 132
 133 #define ENA_TX_OFFLOAD_MASK     (RTE_MBUF_F_TX_L4_MASK |         \
 134         RTE_MBUF_F_TX_IPV6 |            \
 135         RTE_MBUF_F_TX_IPV4 |            \
 136         RTE_MBUF_F_TX_IP_CKSUM |        \
 137         RTE_MBUF_F_TX_TCP_SEG)
 138
 139 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 140         (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 141
 142 /** HW specific offloads capabilities. */
 143 /* IPv4 checksum offload. */
 144 #define ENA_L3_IPV4_CSUM                0x0001
 145 /* TCP/UDP checksum offload for IPv4 packets. */
 146 #define ENA_L4_IPV4_CSUM                0x0002
 147 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 148 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 149 /* TCP/UDP checksum offload for IPv6 packets. */
 150 #define ENA_L4_IPV6_CSUM                0x0008
 151 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 152 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 153 /* TSO support for IPv4 packets. */
 154 #define ENA_IPV4_TSO                    0x0020
 155
 156 /* Device supports setting RSS hash. */
 157 #define ENA_RX_RSS_HASH                 0x0040
 158
 159 static const struct rte_pci_id pci_id_ena_map[] = {
 160         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 161         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 162         { .device_id = 0 },
 163 };
 164
 165 static struct ena_aenq_handlers aenq_handlers;
 166
 167 static int ena_device_init(struct ena_adapter *adapter,
 168                            struct rte_pci_device *pdev,
 169                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 170 static int ena_dev_configure(struct rte_eth_dev *dev);
 171 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 172         struct ena_tx_buffer *tx_info,
 173         struct rte_mbuf *mbuf,
 174         void **push_header,
 175         uint16_t *header_len);
 176 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 177 static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt);
 178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 179                                   uint16_t nb_pkts);
 180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                 uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 190 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 191                                     struct ena_com_rx_buf_info *ena_bufs,
 192                                     uint32_t descs,
 193                                     uint16_t *next_to_clean,
 194                                     uint8_t offset);
 195 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 196                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 197 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 198                                   struct rte_mbuf *mbuf, uint16_t id);
 199 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 200 static void ena_init_rings(struct ena_adapter *adapter,
 201                            bool disable_meta_caching);
 202 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 203 static int ena_start(struct rte_eth_dev *dev);
 204 static int ena_stop(struct rte_eth_dev *dev);
 205 static int ena_close(struct rte_eth_dev *dev);
 206 static int ena_dev_reset(struct rte_eth_dev *dev);
 207 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 208 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 209 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 210 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 211 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 212 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 213 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 214 static int ena_link_update(struct rte_eth_dev *dev,
 215                            int wait_to_complete);
 216 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 217 static void ena_queue_stop(struct ena_ring *ring);
 218 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 219                               enum ena_ring_type ring_type);
 220 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 221 static int ena_queue_start_all(struct rte_eth_dev *dev,
 222                                enum ena_ring_type ring_type);
 223 static void ena_stats_restart(struct rte_eth_dev *dev);
 224 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
 225 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
 226 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
 227 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
 228 static int ena_infos_get(struct rte_eth_dev *dev,
 229                          struct rte_eth_dev_info *dev_info);
 230 static void ena_interrupt_handler_rte(void *cb_arg);
 231 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 232 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 233 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 234 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 235                                 struct rte_eth_xstat_name *xstats_names,
 236                                 unsigned int n);
 237 static int ena_xstats_get_names_by_id(struct rte_eth_dev *dev,
 238                                       const uint64_t *ids,
 239                                       struct rte_eth_xstat_name *xstats_names,
 240                                       unsigned int size);
 241 static int ena_xstats_get(struct rte_eth_dev *dev,
 242                           struct rte_eth_xstat *stats,
 243                           unsigned int n);
 244 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 245                                 const uint64_t *ids,
 246                                 uint64_t *values,
 247                                 unsigned int n);
 248 static int ena_process_bool_devarg(const char *key,
 249                                    const char *value,
 250                                    void *opaque);
 251 static int ena_parse_devargs(struct ena_adapter *adapter,
 252                              struct rte_devargs *devargs);
 253 static int ena_copy_eni_stats(struct ena_adapter *adapter,
 254                               struct ena_stats_eni *stats);
 255 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 256 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                     uint16_t queue_id);
 258 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                      uint16_t queue_id);
 260 static int ena_configure_aenq(struct ena_adapter *adapter);
 261 static int ena_mp_primary_handle(const struct rte_mp_msg *mp_msg,
 262                                  const void *peer);
 263
 264 static const struct eth_dev_ops ena_dev_ops = {
 265         .dev_configure          = ena_dev_configure,
 266         .dev_infos_get          = ena_infos_get,
 267         .rx_queue_setup         = ena_rx_queue_setup,
 268         .tx_queue_setup         = ena_tx_queue_setup,
 269         .dev_start              = ena_start,
 270         .dev_stop               = ena_stop,
 271         .link_update            = ena_link_update,
 272         .stats_get              = ena_stats_get,
 273         .xstats_get_names       = ena_xstats_get_names,
 274         .xstats_get_names_by_id = ena_xstats_get_names_by_id,
 275         .xstats_get             = ena_xstats_get,
 276         .xstats_get_by_id       = ena_xstats_get_by_id,
 277         .mtu_set                = ena_mtu_set,
 278         .rx_queue_release       = ena_rx_queue_release,
 279         .tx_queue_release       = ena_tx_queue_release,
 280         .dev_close              = ena_close,
 281         .dev_reset              = ena_dev_reset,
 282         .reta_update            = ena_rss_reta_update,
 283         .reta_query             = ena_rss_reta_query,
 284         .rx_queue_intr_enable   = ena_rx_queue_intr_enable,
 285         .rx_queue_intr_disable  = ena_rx_queue_intr_disable,
 286         .rss_hash_update        = ena_rss_hash_update,
 287         .rss_hash_conf_get      = ena_rss_hash_conf_get,
 288         .tx_done_cleanup        = ena_tx_cleanup,
 289 };
 290
 291 /*********************************************************************
 292  *  Multi-Process communication bits
 293  *********************************************************************/
 294 /* rte_mp IPC message name */
 295 #define ENA_MP_NAME     "net_ena_mp"
 296 /* Request timeout in seconds */
 297 #define ENA_MP_REQ_TMO  5
 298
 299 /** Proxy request type */
 300 enum ena_mp_req {
 301         ENA_MP_DEV_STATS_GET,
 302         ENA_MP_ENI_STATS_GET,
 303         ENA_MP_MTU_SET,
 304         ENA_MP_IND_TBL_GET,
 305         ENA_MP_IND_TBL_SET
 306 };
 307
 308 /** Proxy message body. Shared between requests and responses. */
 309 struct ena_mp_body {
 310         /* Message type */
 311         enum ena_mp_req type;
 312         int port_id;
 313         /* Processing result. Set in replies. 0 if message succeeded, negative
 314          * error code otherwise.
 315          */
 316         int result;
 317         union {
 318                 int mtu; /* For ENA_MP_MTU_SET */
 319         } args;
 320 };
 321
 322 /**
 323  * Initialize IPC message.
 324  *
 325  * @param[out] msg
 326  *   Pointer to the message to initialize.
 327  * @param[in] type
 328  *   Message type.
 329  * @param[in] port_id
 330  *   Port ID of target device.
 331  *
 332  */
 333 static void
 334 mp_msg_init(struct rte_mp_msg *msg, enum ena_mp_req type, int port_id)
 335 {
 336         struct ena_mp_body *body = (struct ena_mp_body *)&msg->param;
 337
 338         memset(msg, 0, sizeof(*msg));
 339         strlcpy(msg->name, ENA_MP_NAME, sizeof(msg->name));
 340         msg->len_param = sizeof(*body);
 341         body->type = type;
 342         body->port_id = port_id;
 343 }
 344
 345 /*********************************************************************
 346  *  Multi-Process communication PMD API
 347  *********************************************************************/
 348 /**
 349  * Define proxy request descriptor
 350  *
 351  * Used to define all structures and functions required for proxying a given
 352  * function to the primary process including the code to perform to prepare the
 353  * request and process the response.
 354  *
 355  * @param[in] f
 356  *   Name of the function to proxy
 357  * @param[in] t
 358  *   Message type to use
 359  * @param[in] prep
 360  *   Body of a function to prepare the request in form of a statement
 361  *   expression. It is passed all the original function arguments along with two
 362  *   extra ones:
 363  *   - struct ena_adapter *adapter - PMD data of the device calling the proxy.
 364  *   - struct ena_mp_body *req - body of a request to prepare.
 365  * @param[in] proc
 366  *   Body of a function to process the response in form of a statement
 367  *   expression. It is passed all the original function arguments along with two
 368  *   extra ones:
 369  *   - struct ena_adapter *adapter - PMD data of the device calling the proxy.
 370  *   - struct ena_mp_body *rsp - body of a response to process.
 371  * @param ...
 372  *   Proxied function's arguments
 373  *
 374  * @note Inside prep and proc any parameters which aren't used should be marked
 375  *       as such (with ENA_TOUCH or __rte_unused).
 376  */
 377 #define ENA_PROXY_DESC(f, t, prep, proc, ...)                   \
 378         static const enum ena_mp_req mp_type_ ## f =  t;        \
 379         static const char *mp_name_ ## f = #t;                  \
 380         static void mp_prep_ ## f(struct ena_adapter *adapter,  \
 381                                   struct ena_mp_body *req,      \
 382                                   __VA_ARGS__)                  \
 383         {                                                       \
 384                 prep;                                           \
 385         }                                                       \
 386         static void mp_proc_ ## f(struct ena_adapter *adapter,  \
 387                                   struct ena_mp_body *rsp,      \
 388                                   __VA_ARGS__)                  \
 389         {                                                       \
 390                 proc;                                           \
 391         }
 392
 393 /**
 394  * Proxy wrapper for calling primary functions in a secondary process.
 395  *
 396  * Depending on whether called in primary or secondary process, calls the
 397  * @p func directly or proxies the call to the primary process via rte_mp IPC.
 398  * This macro requires a proxy request descriptor to be defined for @p func
 399  * using ENA_PROXY_DESC() macro.
 400  *
 401  * @param[in/out] a
 402  *   Device PMD data. Used for sending the message and sharing message results
 403  *   between primary and secondary.
 404  * @param[in] f
 405  *   Function to proxy.
 406  * @param ...
 407  *   Arguments of @p func.
 408  *
 409  * @return
 410  *   - 0: Processing succeeded and response handler was called.
 411  *   - -EPERM: IPC is unavailable on this platform. This means only primary
 412  *             process may call the proxied function.
 413  *   - -EIO:   IPC returned error on request send. Inspect rte_errno detailed
 414  *             error code.
 415  *   - Negative error code from the proxied function.
 416  *
 417  * @note This mechanism is geared towards control-path tasks. Avoid calling it
 418  *       in fast-path unless unbound delays are allowed. This is due to the IPC
 419  *       mechanism itself (socket based).
 420  * @note Due to IPC parameter size limitations the proxy logic shares call
 421  *       results through the struct ena_adapter shared memory. This makes the
 422  *       proxy mechanism strictly single-threaded. Therefore be sure to make all
 423  *       calls to the same proxied function under the same lock.
 424  */
 425 #define ENA_PROXY(a, f, ...)                                            \
 426 ({                                                                      \
 427         struct ena_adapter *_a = (a);                                   \
 428         struct timespec ts = { .tv_sec = ENA_MP_REQ_TMO };              \
 429         struct ena_mp_body *req, *rsp;                                  \
 430         struct rte_mp_reply mp_rep;                                     \
 431         struct rte_mp_msg mp_req;                                       \
 432         int ret;                                                        \
 433                                                                         \
 434         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {               \
 435                 ret = f(__VA_ARGS__);                                   \
 436         } else {                                                        \
 437                 /* Prepare and send request */                          \
 438                 req = (struct ena_mp_body *)&mp_req.param;              \
 439                 mp_msg_init(&mp_req, mp_type_ ## f, _a->edev_data->port_id); \
 440                 mp_prep_ ## f(_a, req, ## __VA_ARGS__);                 \
 441                                                                         \
 442                 ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);       \
 443                 if (likely(!ret)) {                                     \
 444                         RTE_ASSERT(mp_rep.nb_received == 1);            \
 445                         rsp = (struct ena_mp_body *)&mp_rep.msgs[0].param; \
 446                         ret = rsp->result;                              \
 447                         if (ret == 0) {                                 \
 448                                 mp_proc_##f(_a, rsp, ## __VA_ARGS__);   \
 449                         } else {                                        \
 450                                 PMD_DRV_LOG(ERR,                        \
 451                                             "%s returned error: %d\n",  \
 452                                             mp_name_ ## f, rsp->result);\
 453                         }                                               \
 454                         free(mp_rep.msgs);                              \
 455                 } else if (rte_errno == ENOTSUP) {                      \
 456                         PMD_DRV_LOG(ERR,                                \
 457                                     "No IPC, can't proxy to primary\n");\
 458                         ret = -rte_errno;                               \
 459                 } else {                                                \
 460                         PMD_DRV_LOG(ERR, "Request %s failed: %s\n",     \
 461                                     mp_name_ ## f,                      \
 462                                     rte_strerror(rte_errno));           \
 463                         ret = -EIO;                                     \
 464                 }                                                       \
 465         }                                                               \
 466         ret;                                                            \
 467 })
 468
 469 /*********************************************************************
 470  *  Multi-Process communication request descriptors
 471  *********************************************************************/
 472
 473 ENA_PROXY_DESC(ena_com_get_dev_basic_stats, ENA_MP_DEV_STATS_GET,
 474 ({
 475         ENA_TOUCH(adapter);
 476         ENA_TOUCH(req);
 477         ENA_TOUCH(ena_dev);
 478         ENA_TOUCH(stats);
 479 }),
 480 ({
 481         ENA_TOUCH(rsp);
 482         ENA_TOUCH(ena_dev);
 483         if (stats != &adapter->basic_stats)
 484                 rte_memcpy(stats, &adapter->basic_stats, sizeof(*stats));
 485 }),
 486         struct ena_com_dev *ena_dev, struct ena_admin_basic_stats *stats);
 487
 488 ENA_PROXY_DESC(ena_com_get_eni_stats, ENA_MP_ENI_STATS_GET,
 489 ({
 490         ENA_TOUCH(adapter);
 491         ENA_TOUCH(req);
 492         ENA_TOUCH(ena_dev);
 493         ENA_TOUCH(stats);
 494 }),
 495 ({
 496         ENA_TOUCH(rsp);
 497         ENA_TOUCH(ena_dev);
 498         if (stats != (struct ena_admin_eni_stats *)&adapter->eni_stats)
 499                 rte_memcpy(stats, &adapter->eni_stats, sizeof(*stats));
 500 }),
 501         struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats);
 502
 503 ENA_PROXY_DESC(ena_com_set_dev_mtu, ENA_MP_MTU_SET,
 504 ({
 505         ENA_TOUCH(adapter);
 506         ENA_TOUCH(ena_dev);
 507         req->args.mtu = mtu;
 508 }),
 509 ({
 510         ENA_TOUCH(adapter);
 511         ENA_TOUCH(rsp);
 512         ENA_TOUCH(ena_dev);
 513         ENA_TOUCH(mtu);
 514 }),
 515         struct ena_com_dev *ena_dev, int mtu);
 516
 517 ENA_PROXY_DESC(ena_com_indirect_table_set, ENA_MP_IND_TBL_SET,
 518 ({
 519         ENA_TOUCH(adapter);
 520         ENA_TOUCH(req);
 521         ENA_TOUCH(ena_dev);
 522 }),
 523 ({
 524         ENA_TOUCH(adapter);
 525         ENA_TOUCH(rsp);
 526         ENA_TOUCH(ena_dev);
 527 }),
 528         struct ena_com_dev *ena_dev);
 529
 530 ENA_PROXY_DESC(ena_com_indirect_table_get, ENA_MP_IND_TBL_GET,
 531 ({
 532         ENA_TOUCH(adapter);
 533         ENA_TOUCH(req);
 534         ENA_TOUCH(ena_dev);
 535         ENA_TOUCH(ind_tbl);
 536 }),
 537 ({
 538         ENA_TOUCH(rsp);
 539         ENA_TOUCH(ena_dev);
 540         if (ind_tbl != adapter->indirect_table)
 541                 rte_memcpy(ind_tbl, adapter->indirect_table,
 542                            sizeof(adapter->indirect_table));
 543 }),
 544         struct ena_com_dev *ena_dev, u32 *ind_tbl);
 545
 546 static inline void ena_trigger_reset(struct ena_adapter *adapter,
 547                                      enum ena_regs_reset_reason_types reason)
 548 {
 549         if (likely(!adapter->trigger_reset)) {
 550                 adapter->reset_reason = reason;
 551                 adapter->trigger_reset = true;
 552         }
 553 }
 554
 555 static inline void ena_rx_mbuf_prepare(struct ena_ring *rx_ring,
 556                                        struct rte_mbuf *mbuf,
 557                                        struct ena_com_rx_ctx *ena_rx_ctx,
 558                                        bool fill_hash)
 559 {
 560         struct ena_stats_rx *rx_stats = &rx_ring->rx_stats;
 561         uint64_t ol_flags = 0;
 562         uint32_t packet_type = 0;
 563
 564         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 565                 packet_type |= RTE_PTYPE_L4_TCP;
 566         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 567                 packet_type |= RTE_PTYPE_L4_UDP;
 568
 569         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 570                 packet_type |= RTE_PTYPE_L3_IPV4;
 571                 if (unlikely(ena_rx_ctx->l3_csum_err)) {
 572                         ++rx_stats->l3_csum_bad;
 573                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 574                 } else {
 575                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 576                 }
 577         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 578                 packet_type |= RTE_PTYPE_L3_IPV6;
 579         }
 580
 581         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) {
 582                 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
 583         } else {
 584                 if (unlikely(ena_rx_ctx->l4_csum_err)) {
 585                         ++rx_stats->l4_csum_bad;
 586                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 587                 } else {
 588                         ++rx_stats->l4_csum_good;
 589                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 590                 }
 591         }
 592
 593         if (fill_hash &&
 594             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 595                 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 596                 mbuf->hash.rss = ena_rx_ctx->hash;
 597         }
 598
 599         mbuf->ol_flags = ol_flags;
 600         mbuf->packet_type = packet_type;
 601 }
 602
 603 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 604                                        struct ena_com_tx_ctx *ena_tx_ctx,
 605                                        uint64_t queue_offloads,
 606                                        bool disable_meta_caching)
 607 {
 608         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 609
 610         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 611             (queue_offloads & QUEUE_OFFLOADS)) {
 612                 /* check if TSO is required */
 613                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
 614                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
 615                         ena_tx_ctx->tso_enable = true;
 616
 617                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 618                 }
 619
 620                 /* check if L3 checksum is needed */
 621                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
 622                     (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
 623                         ena_tx_ctx->l3_csum_enable = true;
 624
 625                 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
 626                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 627                 } else {
 628                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 629
 630                         /* set don't fragment (DF) flag */
 631                         if (mbuf->packet_type &
 632                                 (RTE_PTYPE_L4_NONFRAG
 633                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 634                                 ena_tx_ctx->df = true;
 635                 }
 636
 637                 /* check if L4 checksum is needed */
 638                 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
 639                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
 640                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 641                         ena_tx_ctx->l4_csum_enable = true;
 642                 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
 643                                 RTE_MBUF_F_TX_UDP_CKSUM) &&
 644                                 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
 645                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 646                         ena_tx_ctx->l4_csum_enable = true;
 647                 } else {
 648                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 649                         ena_tx_ctx->l4_csum_enable = false;
 650                 }
 651
 652                 ena_meta->mss = mbuf->tso_segsz;
 653                 ena_meta->l3_hdr_len = mbuf->l3_len;
 654                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 655
 656                 ena_tx_ctx->meta_valid = true;
 657         } else if (disable_meta_caching) {
 658                 memset(ena_meta, 0, sizeof(*ena_meta));
 659                 ena_tx_ctx->meta_valid = true;
 660         } else {
 661                 ena_tx_ctx->meta_valid = false;
 662         }
 663 }
 664
 665 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 666 {
 667         struct ena_tx_buffer *tx_info = NULL;
 668
 669         if (likely(req_id < tx_ring->ring_size)) {
 670                 tx_info = &tx_ring->tx_buffer_info[req_id];
 671                 if (likely(tx_info->mbuf))
 672                         return 0;
 673         }
 674
 675         if (tx_info)
 676                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 677         else
 678                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 679
 680         /* Trigger device reset */
 681         ++tx_ring->tx_stats.bad_req_id;
 682         ena_trigger_reset(tx_ring->adapter, ENA_REGS_RESET_INV_TX_REQ_ID);
 683         return -EFAULT;
 684 }
 685
 686 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 687 {
 688         struct ena_admin_host_info *host_info;
 689         int rc;
 690
 691         /* Allocate only the host info */
 692         rc = ena_com_allocate_host_info(ena_dev);
 693         if (rc) {
 694                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 695                 return;
 696         }
 697
 698         host_info = ena_dev->host_attr.host_info;
 699
 700         host_info->os_type = ENA_ADMIN_OS_DPDK;
 701         host_info->kernel_ver = RTE_VERSION;
 702         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 703                 sizeof(host_info->kernel_ver_str));
 704         host_info->os_dist = RTE_VERSION;
 705         strlcpy((char *)host_info->os_dist_str, rte_version(),
 706                 sizeof(host_info->os_dist_str));
 707         host_info->driver_version =
 708                 (DRV_MODULE_VER_MAJOR) |
 709                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 710                 (DRV_MODULE_VER_SUBMINOR <<
 711                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 712         host_info->num_cpus = rte_lcore_count();
 713
 714         host_info->driver_supported_features =
 715                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 716                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 717
 718         rc = ena_com_set_host_attributes(ena_dev);
 719         if (rc) {
 720                 if (rc == -ENA_COM_UNSUPPORTED)
 721                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 722                 else
 723                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 724
 725                 goto err;
 726         }
 727
 728         return;
 729
 730 err:
 731         ena_com_delete_host_info(ena_dev);
 732 }
 733
 734 /* This function calculates the number of xstats based on the current config */
 735 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 736 {
 737         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 738                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 739                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 740 }
 741
 742 static void ena_config_debug_area(struct ena_adapter *adapter)
 743 {
 744         u32 debug_area_size;
 745         int rc, ss_count;
 746
 747         ss_count = ena_xstats_calc_num(adapter->edev_data);
 748
 749         /* allocate 32 bytes for each string and 64bit for the value */
 750         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 751
 752         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 753         if (rc) {
 754                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 755                 return;
 756         }
 757
 758         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 759         if (rc) {
 760                 if (rc == -ENA_COM_UNSUPPORTED)
 761                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 762                 else
 763                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 764
 765                 goto err;
 766         }
 767
 768         return;
 769 err:
 770         ena_com_delete_debug_area(&adapter->ena_dev);
 771 }
 772
 773 static int ena_close(struct rte_eth_dev *dev)
 774 {
 775         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 776         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 777         struct ena_adapter *adapter = dev->data->dev_private;
 778         int ret = 0;
 779
 780         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 781                 return 0;
 782
 783         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 784                 ret = ena_stop(dev);
 785         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 786
 787         ena_rx_queue_release_all(dev);
 788         ena_tx_queue_release_all(dev);
 789
 790         rte_free(adapter->drv_stats);
 791         adapter->drv_stats = NULL;
 792
 793         rte_intr_disable(intr_handle);
 794         rte_intr_callback_unregister(intr_handle,
 795                                      ena_interrupt_handler_rte,
 796                                      dev);
 797
 798         /*
 799          * MAC is not allocated dynamically. Setting NULL should prevent from
 800          * release of the resource in the rte_eth_dev_release_port().
 801          */
 802         dev->data->mac_addrs = NULL;
 803
 804         return ret;
 805 }
 806
 807 static int
 808 ena_dev_reset(struct rte_eth_dev *dev)
 809 {
 810         int rc = 0;
 811
 812         /* Cannot release memory in secondary process */
 813         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 814                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 815                 return -EPERM;
 816         }
 817
 818         ena_destroy_device(dev);
 819         rc = eth_ena_dev_init(dev);
 820         if (rc)
 821                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 822
 823         return rc;
 824 }
 825
 826 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 827 {
 828         int nb_queues = dev->data->nb_rx_queues;
 829         int i;
 830
 831         for (i = 0; i < nb_queues; i++)
 832                 ena_rx_queue_release(dev, i);
 833 }
 834
 835 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 836 {
 837         int nb_queues = dev->data->nb_tx_queues;
 838         int i;
 839
 840         for (i = 0; i < nb_queues; i++)
 841                 ena_tx_queue_release(dev, i);
 842 }
 843
 844 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 845 {
 846         struct ena_ring *ring = dev->data->rx_queues[qid];
 847
 848         /* Free ring resources */
 849         rte_free(ring->rx_buffer_info);
 850         ring->rx_buffer_info = NULL;
 851
 852         rte_free(ring->rx_refill_buffer);
 853         ring->rx_refill_buffer = NULL;
 854
 855         rte_free(ring->empty_rx_reqs);
 856         ring->empty_rx_reqs = NULL;
 857
 858         ring->configured = 0;
 859
 860         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 861                 ring->port_id, ring->id);
 862 }
 863
 864 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 865 {
 866         struct ena_ring *ring = dev->data->tx_queues[qid];
 867
 868         /* Free ring resources */
 869         rte_free(ring->push_buf_intermediate_buf);
 870
 871         rte_free(ring->tx_buffer_info);
 872
 873         rte_free(ring->empty_tx_reqs);
 874
 875         ring->empty_tx_reqs = NULL;
 876         ring->tx_buffer_info = NULL;
 877         ring->push_buf_intermediate_buf = NULL;
 878
 879         ring->configured = 0;
 880
 881         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 882                 ring->port_id, ring->id);
 883 }
 884
 885 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 886 {
 887         unsigned int i;
 888
 889         for (i = 0; i < ring->ring_size; ++i) {
 890                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 891                 if (rx_info->mbuf) {
 892                         rte_mbuf_raw_free(rx_info->mbuf);
 893                         rx_info->mbuf = NULL;
 894                 }
 895         }
 896 }
 897
 898 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 899 {
 900         unsigned int i;
 901
 902         for (i = 0; i < ring->ring_size; ++i) {
 903                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 904
 905                 if (tx_buf->mbuf) {
 906                         rte_pktmbuf_free(tx_buf->mbuf);
 907                         tx_buf->mbuf = NULL;
 908                 }
 909         }
 910 }
 911
 912 static int ena_link_update(struct rte_eth_dev *dev,
 913                            __rte_unused int wait_to_complete)
 914 {
 915         struct rte_eth_link *link = &dev->data->dev_link;
 916         struct ena_adapter *adapter = dev->data->dev_private;
 917
 918         link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
 919         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
 920         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 921
 922         return 0;
 923 }
 924
 925 static int ena_queue_start_all(struct rte_eth_dev *dev,
 926                                enum ena_ring_type ring_type)
 927 {
 928         struct ena_adapter *adapter = dev->data->dev_private;
 929         struct ena_ring *queues = NULL;
 930         int nb_queues;
 931         int i = 0;
 932         int rc = 0;
 933
 934         if (ring_type == ENA_RING_TYPE_RX) {
 935                 queues = adapter->rx_ring;
 936                 nb_queues = dev->data->nb_rx_queues;
 937         } else {
 938                 queues = adapter->tx_ring;
 939                 nb_queues = dev->data->nb_tx_queues;
 940         }
 941         for (i = 0; i < nb_queues; i++) {
 942                 if (queues[i].configured) {
 943                         if (ring_type == ENA_RING_TYPE_RX) {
 944                                 ena_assert_msg(
 945                                         dev->data->rx_queues[i] == &queues[i],
 946                                         "Inconsistent state of Rx queues\n");
 947                         } else {
 948                                 ena_assert_msg(
 949                                         dev->data->tx_queues[i] == &queues[i],
 950                                         "Inconsistent state of Tx queues\n");
 951                         }
 952
 953                         rc = ena_queue_start(dev, &queues[i]);
 954
 955                         if (rc) {
 956                                 PMD_INIT_LOG(ERR,
 957                                         "Failed to start queue[%d] of type(%d)\n",
 958                                         i, ring_type);
 959                                 goto err;
 960                         }
 961                 }
 962         }
 963
 964         return 0;
 965
 966 err:
 967         while (i--)
 968                 if (queues[i].configured)
 969                         ena_queue_stop(&queues[i]);
 970
 971         return rc;
 972 }
 973
 974 static int ena_check_valid_conf(struct ena_adapter *adapter)
 975 {
 976         uint32_t mtu = adapter->edev_data->mtu;
 977
 978         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 979                 PMD_INIT_LOG(ERR,
 980                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 981                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 982                 return ENA_COM_UNSUPPORTED;
 983         }
 984
 985         return 0;
 986 }
 987
 988 static int
 989 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 990                        bool use_large_llq_hdr)
 991 {
 992         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 993         struct ena_com_dev *ena_dev = ctx->ena_dev;
 994         uint32_t max_tx_queue_size;
 995         uint32_t max_rx_queue_size;
 996
 997         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 998                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 999                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
1000                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
1001                         max_queue_ext->max_rx_sq_depth);
1002                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
1003
1004                 if (ena_dev->tx_mem_queue_type ==
1005                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1006                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1007                                 llq->max_llq_depth);
1008                 } else {
1009                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1010                                 max_queue_ext->max_tx_sq_depth);
1011                 }
1012
1013                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1014                         max_queue_ext->max_per_packet_rx_descs);
1015                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1016                         max_queue_ext->max_per_packet_tx_descs);
1017         } else {
1018                 struct ena_admin_queue_feature_desc *max_queues =
1019                         &ctx->get_feat_ctx->max_queues;
1020                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
1021                         max_queues->max_sq_depth);
1022                 max_tx_queue_size = max_queues->max_cq_depth;
1023
1024                 if (ena_dev->tx_mem_queue_type ==
1025                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1026                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1027                                 llq->max_llq_depth);
1028                 } else {
1029                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1030                                 max_queues->max_sq_depth);
1031                 }
1032
1033                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1034                         max_queues->max_packet_rx_descs);
1035                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1036                         max_queues->max_packet_tx_descs);
1037         }
1038
1039         /* Round down to the nearest power of 2 */
1040         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
1041         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
1042
1043         if (use_large_llq_hdr) {
1044                 if ((llq->entry_size_ctrl_supported &
1045                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
1046                     (ena_dev->tx_mem_queue_type ==
1047                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
1048                         max_tx_queue_size /= 2;
1049                         PMD_INIT_LOG(INFO,
1050                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
1051                                 max_tx_queue_size);
1052                 } else {
1053                         PMD_INIT_LOG(ERR,
1054                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
1055                 }
1056         }
1057
1058         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
1059                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
1060                 return -EFAULT;
1061         }
1062
1063         ctx->max_tx_queue_size = max_tx_queue_size;
1064         ctx->max_rx_queue_size = max_rx_queue_size;
1065
1066         return 0;
1067 }
1068
1069 static void ena_stats_restart(struct rte_eth_dev *dev)
1070 {
1071         struct ena_adapter *adapter = dev->data->dev_private;
1072
1073         rte_atomic64_init(&adapter->drv_stats->ierrors);
1074         rte_atomic64_init(&adapter->drv_stats->oerrors);
1075         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
1076         adapter->drv_stats->rx_drops = 0;
1077 }
1078
1079 static int ena_stats_get(struct rte_eth_dev *dev,
1080                           struct rte_eth_stats *stats)
1081 {
1082         struct ena_admin_basic_stats ena_stats;
1083         struct ena_adapter *adapter = dev->data->dev_private;
1084         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1085         int rc;
1086         int i;
1087         int max_rings_stats;
1088
1089         memset(&ena_stats, 0, sizeof(ena_stats));
1090
1091         rte_spinlock_lock(&adapter->admin_lock);
1092         rc = ENA_PROXY(adapter, ena_com_get_dev_basic_stats, ena_dev,
1093                        &ena_stats);
1094         rte_spinlock_unlock(&adapter->admin_lock);
1095         if (unlikely(rc)) {
1096                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
1097                 return rc;
1098         }
1099
1100         /* Set of basic statistics from ENA */
1101         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1102                                           ena_stats.rx_pkts_low);
1103         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1104                                           ena_stats.tx_pkts_low);
1105         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1106                                         ena_stats.rx_bytes_low);
1107         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1108                                         ena_stats.tx_bytes_low);
1109
1110         /* Driver related stats */
1111         stats->imissed = adapter->drv_stats->rx_drops;
1112         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1113         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1114         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1115
1116         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1117                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1118         for (i = 0; i < max_rings_stats; ++i) {
1119                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1120
1121                 stats->q_ibytes[i] = rx_stats->bytes;
1122                 stats->q_ipackets[i] = rx_stats->cnt;
1123                 stats->q_errors[i] = rx_stats->bad_desc_num +
1124                         rx_stats->bad_req_id;
1125         }
1126
1127         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1128                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1129         for (i = 0; i < max_rings_stats; ++i) {
1130                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1131
1132                 stats->q_obytes[i] = tx_stats->bytes;
1133                 stats->q_opackets[i] = tx_stats->cnt;
1134         }
1135
1136         return 0;
1137 }
1138
1139 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1140 {
1141         struct ena_adapter *adapter;
1142         struct ena_com_dev *ena_dev;
1143         int rc = 0;
1144
1145         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1146         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1147         adapter = dev->data->dev_private;
1148
1149         ena_dev = &adapter->ena_dev;
1150         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1151
1152         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
1153                 PMD_DRV_LOG(ERR,
1154                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
1155                         mtu, adapter->max_mtu, ENA_MIN_MTU);
1156                 return -EINVAL;
1157         }
1158
1159         rc = ENA_PROXY(adapter, ena_com_set_dev_mtu, ena_dev, mtu);
1160         if (rc)
1161                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1162         else
1163                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
1164
1165         return rc;
1166 }
1167
1168 static int ena_start(struct rte_eth_dev *dev)
1169 {
1170         struct ena_adapter *adapter = dev->data->dev_private;
1171         uint64_t ticks;
1172         int rc = 0;
1173
1174         /* Cannot allocate memory in secondary process */
1175         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1176                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
1177                 return -EPERM;
1178         }
1179
1180         rc = ena_check_valid_conf(adapter);
1181         if (rc)
1182                 return rc;
1183
1184         rc = ena_setup_rx_intr(dev);
1185         if (rc)
1186                 return rc;
1187
1188         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1189         if (rc)
1190                 return rc;
1191
1192         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1193         if (rc)
1194                 goto err_start_tx;
1195
1196         if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
1197                 rc = ena_rss_configure(adapter);
1198                 if (rc)
1199                         goto err_rss_init;
1200         }
1201
1202         ena_stats_restart(dev);
1203
1204         adapter->timestamp_wd = rte_get_timer_cycles();
1205         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1206
1207         ticks = rte_get_timer_hz();
1208         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1209                         ena_timer_wd_callback, dev);
1210
1211         ++adapter->dev_stats.dev_start;
1212         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1213
1214         return 0;
1215
1216 err_rss_init:
1217         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1218 err_start_tx:
1219         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1220         return rc;
1221 }
1222
1223 static int ena_stop(struct rte_eth_dev *dev)
1224 {
1225         struct ena_adapter *adapter = dev->data->dev_private;
1226         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1227         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1228         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1229         int rc;
1230
1231         /* Cannot free memory in secondary process */
1232         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1233                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
1234                 return -EPERM;
1235         }
1236
1237         rte_timer_stop_sync(&adapter->timer_wd);
1238         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1239         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1240
1241         if (adapter->trigger_reset) {
1242                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1243                 if (rc)
1244                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
1245         }
1246
1247         rte_intr_disable(intr_handle);
1248
1249         rte_intr_efd_disable(intr_handle);
1250
1251         /* Cleanup vector list */
1252         rte_intr_vec_list_free(intr_handle);
1253
1254         rte_intr_enable(intr_handle);
1255
1256         ++adapter->dev_stats.dev_stop;
1257         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1258         dev->data->dev_started = 0;
1259
1260         return 0;
1261 }
1262
1263 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
1264 {
1265         struct ena_adapter *adapter = ring->adapter;
1266         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1267         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1268         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1269         struct ena_com_create_io_ctx ctx =
1270                 /* policy set to _HOST just to satisfy icc compiler */
1271                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1272                   0, 0, 0, 0, 0 };
1273         uint16_t ena_qid;
1274         unsigned int i;
1275         int rc;
1276
1277         ctx.msix_vector = -1;
1278         if (ring->type == ENA_RING_TYPE_TX) {
1279                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1280                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1281                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1282                 for (i = 0; i < ring->ring_size; i++)
1283                         ring->empty_tx_reqs[i] = i;
1284         } else {
1285                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1286                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1287                 if (rte_intr_dp_is_en(intr_handle))
1288                         ctx.msix_vector =
1289                                 rte_intr_vec_list_index_get(intr_handle,
1290                                                                    ring->id);
1291
1292                 for (i = 0; i < ring->ring_size; i++)
1293                         ring->empty_rx_reqs[i] = i;
1294         }
1295         ctx.queue_size = ring->ring_size;
1296         ctx.qid = ena_qid;
1297         ctx.numa_node = ring->numa_socket_id;
1298
1299         rc = ena_com_create_io_queue(ena_dev, &ctx);
1300         if (rc) {
1301                 PMD_DRV_LOG(ERR,
1302                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1303                         ring->id, ena_qid, rc);
1304                 return rc;
1305         }
1306
1307         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1308                                      &ring->ena_com_io_sq,
1309                                      &ring->ena_com_io_cq);
1310         if (rc) {
1311                 PMD_DRV_LOG(ERR,
1312                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1313                         ring->id, rc);
1314                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1315                 return rc;
1316         }
1317
1318         if (ring->type == ENA_RING_TYPE_TX)
1319                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1320
1321         /* Start with Rx interrupts being masked. */
1322         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1323                 ena_rx_queue_intr_disable(dev, ring->id);
1324
1325         return 0;
1326 }
1327
1328 static void ena_queue_stop(struct ena_ring *ring)
1329 {
1330         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1331
1332         if (ring->type == ENA_RING_TYPE_RX) {
1333                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1334                 ena_rx_queue_release_bufs(ring);
1335         } else {
1336                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1337                 ena_tx_queue_release_bufs(ring);
1338         }
1339 }
1340
1341 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1342                               enum ena_ring_type ring_type)
1343 {
1344         struct ena_adapter *adapter = dev->data->dev_private;
1345         struct ena_ring *queues = NULL;
1346         uint16_t nb_queues, i;
1347
1348         if (ring_type == ENA_RING_TYPE_RX) {
1349                 queues = adapter->rx_ring;
1350                 nb_queues = dev->data->nb_rx_queues;
1351         } else {
1352                 queues = adapter->tx_ring;
1353                 nb_queues = dev->data->nb_tx_queues;
1354         }
1355
1356         for (i = 0; i < nb_queues; ++i)
1357                 if (queues[i].configured)
1358                         ena_queue_stop(&queues[i]);
1359 }
1360
1361 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1362 {
1363         int rc, bufs_num;
1364
1365         ena_assert_msg(ring->configured == 1,
1366                        "Trying to start unconfigured queue\n");
1367
1368         rc = ena_create_io_queue(dev, ring);
1369         if (rc) {
1370                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1371                 return rc;
1372         }
1373
1374         ring->next_to_clean = 0;
1375         ring->next_to_use = 0;
1376
1377         if (ring->type == ENA_RING_TYPE_TX) {
1378                 ring->tx_stats.available_desc =
1379                         ena_com_free_q_entries(ring->ena_com_io_sq);
1380                 return 0;
1381         }
1382
1383         bufs_num = ring->ring_size - 1;
1384         rc = ena_populate_rx_queue(ring, bufs_num);
1385         if (rc != bufs_num) {
1386                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1387                                          ENA_IO_RXQ_IDX(ring->id));
1388                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1389                 return ENA_COM_FAULT;
1390         }
1391         /* Flush per-core RX buffers pools cache as they can be used on other
1392          * cores as well.
1393          */
1394         rte_mempool_cache_flush(NULL, ring->mb_pool);
1395
1396         return 0;
1397 }
1398
1399 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1400                               uint16_t queue_idx,
1401                               uint16_t nb_desc,
1402                               unsigned int socket_id,
1403                               const struct rte_eth_txconf *tx_conf)
1404 {
1405         struct ena_ring *txq = NULL;
1406         struct ena_adapter *adapter = dev->data->dev_private;
1407         unsigned int i;
1408         uint16_t dyn_thresh;
1409
1410         txq = &adapter->tx_ring[queue_idx];
1411
1412         if (txq->configured) {
1413                 PMD_DRV_LOG(CRIT,
1414                         "API violation. Queue[%d] is already configured\n",
1415                         queue_idx);
1416                 return ENA_COM_FAULT;
1417         }
1418
1419         if (!rte_is_power_of_2(nb_desc)) {
1420                 PMD_DRV_LOG(ERR,
1421                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1422                         nb_desc);
1423                 return -EINVAL;
1424         }
1425
1426         if (nb_desc > adapter->max_tx_ring_size) {
1427                 PMD_DRV_LOG(ERR,
1428                         "Unsupported size of Tx queue (max size: %d)\n",
1429                         adapter->max_tx_ring_size);
1430                 return -EINVAL;
1431         }
1432
1433         txq->port_id = dev->data->port_id;
1434         txq->next_to_clean = 0;
1435         txq->next_to_use = 0;
1436         txq->ring_size = nb_desc;
1437         txq->size_mask = nb_desc - 1;
1438         txq->numa_socket_id = socket_id;
1439         txq->pkts_without_db = false;
1440         txq->last_cleanup_ticks = 0;
1441
1442         txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1443                 sizeof(struct ena_tx_buffer) * txq->ring_size,
1444                 RTE_CACHE_LINE_SIZE,
1445                 socket_id);
1446         if (!txq->tx_buffer_info) {
1447                 PMD_DRV_LOG(ERR,
1448                         "Failed to allocate memory for Tx buffer info\n");
1449                 return -ENOMEM;
1450         }
1451
1452         txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1453                 sizeof(uint16_t) * txq->ring_size,
1454                 RTE_CACHE_LINE_SIZE,
1455                 socket_id);
1456         if (!txq->empty_tx_reqs) {
1457                 PMD_DRV_LOG(ERR,
1458                         "Failed to allocate memory for empty Tx requests\n");
1459                 rte_free(txq->tx_buffer_info);
1460                 return -ENOMEM;
1461         }
1462
1463         txq->push_buf_intermediate_buf =
1464                 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1465                         txq->tx_max_header_size,
1466                         RTE_CACHE_LINE_SIZE,
1467                         socket_id);
1468         if (!txq->push_buf_intermediate_buf) {
1469                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1470                 rte_free(txq->tx_buffer_info);
1471                 rte_free(txq->empty_tx_reqs);
1472                 return -ENOMEM;
1473         }
1474
1475         for (i = 0; i < txq->ring_size; i++)
1476                 txq->empty_tx_reqs[i] = i;
1477
1478         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1479
1480         /* Check if caller provided the Tx cleanup threshold value. */
1481         if (tx_conf->tx_free_thresh != 0) {
1482                 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1483         } else {
1484                 dyn_thresh = txq->ring_size -
1485                         txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1486                 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1487                         txq->ring_size - ENA_REFILL_THRESH_PACKET);
1488         }
1489
1490         txq->missing_tx_completion_threshold =
1491                 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1492
1493         /* Store pointer to this queue in upper layer */
1494         txq->configured = 1;
1495         dev->data->tx_queues[queue_idx] = txq;
1496
1497         return 0;
1498 }
1499
1500 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1501                               uint16_t queue_idx,
1502                               uint16_t nb_desc,
1503                               unsigned int socket_id,
1504                               const struct rte_eth_rxconf *rx_conf,
1505                               struct rte_mempool *mp)
1506 {
1507         struct ena_adapter *adapter = dev->data->dev_private;
1508         struct ena_ring *rxq = NULL;
1509         size_t buffer_size;
1510         int i;
1511         uint16_t dyn_thresh;
1512
1513         rxq = &adapter->rx_ring[queue_idx];
1514         if (rxq->configured) {
1515                 PMD_DRV_LOG(CRIT,
1516                         "API violation. Queue[%d] is already configured\n",
1517                         queue_idx);
1518                 return ENA_COM_FAULT;
1519         }
1520
1521         if (!rte_is_power_of_2(nb_desc)) {
1522                 PMD_DRV_LOG(ERR,
1523                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1524                         nb_desc);
1525                 return -EINVAL;
1526         }
1527
1528         if (nb_desc > adapter->max_rx_ring_size) {
1529                 PMD_DRV_LOG(ERR,
1530                         "Unsupported size of Rx queue (max size: %d)\n",
1531                         adapter->max_rx_ring_size);
1532                 return -EINVAL;
1533         }
1534
1535         /* ENA isn't supporting buffers smaller than 1400 bytes */
1536         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1537         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1538                 PMD_DRV_LOG(ERR,
1539                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1540                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1541                 return -EINVAL;
1542         }
1543
1544         rxq->port_id = dev->data->port_id;
1545         rxq->next_to_clean = 0;
1546         rxq->next_to_use = 0;
1547         rxq->ring_size = nb_desc;
1548         rxq->size_mask = nb_desc - 1;
1549         rxq->numa_socket_id = socket_id;
1550         rxq->mb_pool = mp;
1551
1552         rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1553                 sizeof(struct ena_rx_buffer) * nb_desc,
1554                 RTE_CACHE_LINE_SIZE,
1555                 socket_id);
1556         if (!rxq->rx_buffer_info) {
1557                 PMD_DRV_LOG(ERR,
1558                         "Failed to allocate memory for Rx buffer info\n");
1559                 return -ENOMEM;
1560         }
1561
1562         rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1563                 sizeof(struct rte_mbuf *) * nb_desc,
1564                 RTE_CACHE_LINE_SIZE,
1565                 socket_id);
1566         if (!rxq->rx_refill_buffer) {
1567                 PMD_DRV_LOG(ERR,
1568                         "Failed to allocate memory for Rx refill buffer\n");
1569                 rte_free(rxq->rx_buffer_info);
1570                 rxq->rx_buffer_info = NULL;
1571                 return -ENOMEM;
1572         }
1573
1574         rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1575                 sizeof(uint16_t) * nb_desc,
1576                 RTE_CACHE_LINE_SIZE,
1577                 socket_id);
1578         if (!rxq->empty_rx_reqs) {
1579                 PMD_DRV_LOG(ERR,
1580                         "Failed to allocate memory for empty Rx requests\n");
1581                 rte_free(rxq->rx_buffer_info);
1582                 rxq->rx_buffer_info = NULL;
1583                 rte_free(rxq->rx_refill_buffer);
1584                 rxq->rx_refill_buffer = NULL;
1585                 return -ENOMEM;
1586         }
1587
1588         for (i = 0; i < nb_desc; i++)
1589                 rxq->empty_rx_reqs[i] = i;
1590
1591         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1592
1593         if (rx_conf->rx_free_thresh != 0) {
1594                 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1595         } else {
1596                 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1597                 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1598                         (uint16_t)(ENA_REFILL_THRESH_PACKET));
1599         }
1600
1601         /* Store pointer to this queue in upper layer */
1602         rxq->configured = 1;
1603         dev->data->rx_queues[queue_idx] = rxq;
1604
1605         return 0;
1606 }
1607
1608 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1609                                   struct rte_mbuf *mbuf, uint16_t id)
1610 {
1611         struct ena_com_buf ebuf;
1612         int rc;
1613
1614         /* prepare physical address for DMA transaction */
1615         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1616         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1617
1618         /* pass resource to device */
1619         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1620         if (unlikely(rc != 0))
1621                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1622
1623         return rc;
1624 }
1625
1626 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1627 {
1628         unsigned int i;
1629         int rc;
1630         uint16_t next_to_use = rxq->next_to_use;
1631         uint16_t req_id;
1632 #ifdef RTE_ETHDEV_DEBUG_RX
1633         uint16_t in_use;
1634 #endif
1635         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1636
1637         if (unlikely(!count))
1638                 return 0;
1639
1640 #ifdef RTE_ETHDEV_DEBUG_RX
1641         in_use = rxq->ring_size - 1 -
1642                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1643         if (unlikely((in_use + count) >= rxq->ring_size))
1644                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1645 #endif
1646
1647         /* get resources for incoming packets */
1648         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1649         if (unlikely(rc < 0)) {
1650                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1651                 ++rxq->rx_stats.mbuf_alloc_fail;
1652                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1653                 return 0;
1654         }
1655
1656         for (i = 0; i < count; i++) {
1657                 struct rte_mbuf *mbuf = mbufs[i];
1658                 struct ena_rx_buffer *rx_info;
1659
1660                 if (likely((i + 4) < count))
1661                         rte_prefetch0(mbufs[i + 4]);
1662
1663                 req_id = rxq->empty_rx_reqs[next_to_use];
1664                 rx_info = &rxq->rx_buffer_info[req_id];
1665
1666                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1667                 if (unlikely(rc != 0))
1668                         break;
1669
1670                 rx_info->mbuf = mbuf;
1671                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1672         }
1673
1674         if (unlikely(i < count)) {
1675                 PMD_RX_LOG(WARNING,
1676                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1677                         rxq->id, i, count);
1678                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1679                 ++rxq->rx_stats.refill_partial;
1680         }
1681
1682         /* When we submitted free resources to device... */
1683         if (likely(i > 0)) {
1684                 /* ...let HW know that it can fill buffers with data. */
1685                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1686
1687                 rxq->next_to_use = next_to_use;
1688         }
1689
1690         return i;
1691 }
1692
1693 static int ena_device_init(struct ena_adapter *adapter,
1694                            struct rte_pci_device *pdev,
1695                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1696 {
1697         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1698         uint32_t aenq_groups;
1699         int rc;
1700         bool readless_supported;
1701
1702         /* Initialize mmio registers */
1703         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1704         if (rc) {
1705                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1706                 return rc;
1707         }
1708
1709         /* The PCIe configuration space revision id indicate if mmio reg
1710          * read is disabled.
1711          */
1712         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1713         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1714
1715         /* reset device */
1716         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1717         if (rc) {
1718                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1719                 goto err_mmio_read_less;
1720         }
1721
1722         /* check FW version */
1723         rc = ena_com_validate_version(ena_dev);
1724         if (rc) {
1725                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1726                 goto err_mmio_read_less;
1727         }
1728
1729         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1730
1731         /* ENA device administration layer init */
1732         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1733         if (rc) {
1734                 PMD_DRV_LOG(ERR,
1735                         "Cannot initialize ENA admin queue\n");
1736                 goto err_mmio_read_less;
1737         }
1738
1739         /* To enable the msix interrupts the driver needs to know the number
1740          * of queues. So the driver uses polling mode to retrieve this
1741          * information.
1742          */
1743         ena_com_set_admin_polling_mode(ena_dev, true);
1744
1745         ena_config_host_info(ena_dev);
1746
1747         /* Get Device Attributes and features */
1748         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1749         if (rc) {
1750                 PMD_DRV_LOG(ERR,
1751                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1752                 goto err_admin_init;
1753         }
1754
1755         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1756                       BIT(ENA_ADMIN_NOTIFICATION) |
1757                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1758                       BIT(ENA_ADMIN_FATAL_ERROR) |
1759                       BIT(ENA_ADMIN_WARNING);
1760
1761         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1762
1763         adapter->all_aenq_groups = aenq_groups;
1764
1765         return 0;
1766
1767 err_admin_init:
1768         ena_com_admin_destroy(ena_dev);
1769
1770 err_mmio_read_less:
1771         ena_com_mmio_reg_read_request_destroy(ena_dev);
1772
1773         return rc;
1774 }
1775
1776 static void ena_interrupt_handler_rte(void *cb_arg)
1777 {
1778         struct rte_eth_dev *dev = cb_arg;
1779         struct ena_adapter *adapter = dev->data->dev_private;
1780         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1781
1782         ena_com_admin_q_comp_intr_handler(ena_dev);
1783         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1784                 ena_com_aenq_intr_handler(ena_dev, dev);
1785 }
1786
1787 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1788 {
1789         if (!(adapter->active_aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)))
1790                 return;
1791
1792         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1793                 return;
1794
1795         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1796             adapter->keep_alive_timeout)) {
1797                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1798                 ena_trigger_reset(adapter, ENA_REGS_RESET_KEEP_ALIVE_TO);
1799                 ++adapter->dev_stats.wd_expired;
1800         }
1801 }
1802
1803 /* Check if admin queue is enabled */
1804 static void check_for_admin_com_state(struct ena_adapter *adapter)
1805 {
1806         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1807                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1808                 ena_trigger_reset(adapter, ENA_REGS_RESET_ADMIN_TO);
1809         }
1810 }
1811
1812 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1813                                             struct ena_ring *tx_ring)
1814 {
1815         struct ena_tx_buffer *tx_buf;
1816         uint64_t timestamp;
1817         uint64_t completion_delay;
1818         uint32_t missed_tx = 0;
1819         unsigned int i;
1820         int rc = 0;
1821
1822         for (i = 0; i < tx_ring->ring_size; ++i) {
1823                 tx_buf = &tx_ring->tx_buffer_info[i];
1824                 timestamp = tx_buf->timestamp;
1825
1826                 if (timestamp == 0)
1827                         continue;
1828
1829                 completion_delay = rte_get_timer_cycles() - timestamp;
1830                 if (completion_delay > adapter->missing_tx_completion_to) {
1831                         if (unlikely(!tx_buf->print_once)) {
1832                                 PMD_TX_LOG(WARNING,
1833                                         "Found a Tx that wasn't completed on time, qid %d, index %d. "
1834                                         "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1835                                         tx_ring->id, i, completion_delay /
1836                                         rte_get_timer_hz() * 1000);
1837                                 tx_buf->print_once = true;
1838                         }
1839                         ++missed_tx;
1840                 }
1841         }
1842
1843         if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1844                 PMD_DRV_LOG(ERR,
1845                         "The number of lost Tx completions is above the threshold (%d > %d). "
1846                         "Trigger the device reset.\n",
1847                         missed_tx,
1848                         tx_ring->missing_tx_completion_threshold);
1849                 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1850                 adapter->trigger_reset = true;
1851                 rc = -EIO;
1852         }
1853
1854         tx_ring->tx_stats.missed_tx += missed_tx;
1855
1856         return rc;
1857 }
1858
1859 static void check_for_tx_completions(struct ena_adapter *adapter)
1860 {
1861         struct ena_ring *tx_ring;
1862         uint64_t tx_cleanup_delay;
1863         size_t qid;
1864         int budget;
1865         uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1866
1867         if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1868                 return;
1869
1870         nb_tx_queues = adapter->edev_data->nb_tx_queues;
1871         budget = adapter->missing_tx_completion_budget;
1872
1873         qid = adapter->last_tx_comp_qid;
1874         while (budget-- > 0) {
1875                 tx_ring = &adapter->tx_ring[qid];
1876
1877                 /* Tx cleanup is called only by the burst function and can be
1878                  * called dynamically by the application. Also cleanup is
1879                  * limited by the threshold. To avoid false detection of the
1880                  * missing HW Tx completion, get the delay since last cleanup
1881                  * function was called.
1882                  */
1883                 tx_cleanup_delay = rte_get_timer_cycles() -
1884                         tx_ring->last_cleanup_ticks;
1885                 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1886                         check_for_tx_completion_in_queue(adapter, tx_ring);
1887                 qid = (qid + 1) % nb_tx_queues;
1888         }
1889
1890         adapter->last_tx_comp_qid = qid;
1891 }
1892
1893 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1894                                   void *arg)
1895 {
1896         struct rte_eth_dev *dev = arg;
1897         struct ena_adapter *adapter = dev->data->dev_private;
1898
1899         if (unlikely(adapter->trigger_reset))
1900                 return;
1901
1902         check_for_missing_keep_alive(adapter);
1903         check_for_admin_com_state(adapter);
1904         check_for_tx_completions(adapter);
1905
1906         if (unlikely(adapter->trigger_reset)) {
1907                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1908                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1909                         NULL);
1910         }
1911 }
1912
1913 static inline void
1914 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1915                                struct ena_admin_feature_llq_desc *llq,
1916                                bool use_large_llq_hdr)
1917 {
1918         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1919         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1920         llq_config->llq_num_decs_before_header =
1921                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1922
1923         if (use_large_llq_hdr &&
1924             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1925                 llq_config->llq_ring_entry_size =
1926                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1927                 llq_config->llq_ring_entry_size_value = 256;
1928         } else {
1929                 llq_config->llq_ring_entry_size =
1930                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1931                 llq_config->llq_ring_entry_size_value = 128;
1932         }
1933 }
1934
1935 static int
1936 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1937                                 struct ena_com_dev *ena_dev,
1938                                 struct ena_admin_feature_llq_desc *llq,
1939                                 struct ena_llq_configurations *llq_default_configurations)
1940 {
1941         int rc;
1942         u32 llq_feature_mask;
1943
1944         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1945         if (!(ena_dev->supported_features & llq_feature_mask)) {
1946                 PMD_DRV_LOG(INFO,
1947                         "LLQ is not supported. Fallback to host mode policy.\n");
1948                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1949                 return 0;
1950         }
1951
1952         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1953         if (unlikely(rc)) {
1954                 PMD_INIT_LOG(WARNING,
1955                         "Failed to config dev mode. Fallback to host mode policy.\n");
1956                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1957                 return 0;
1958         }
1959
1960         /* Nothing to config, exit */
1961         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1962                 return 0;
1963
1964         if (!adapter->dev_mem_base) {
1965                 PMD_DRV_LOG(ERR,
1966                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1967                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1968                 return 0;
1969         }
1970
1971         ena_dev->mem_bar = adapter->dev_mem_base;
1972
1973         return 0;
1974 }
1975
1976 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1977         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1978 {
1979         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1980
1981         /* Regular queues capabilities */
1982         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1983                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1984                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1985                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1986                                     max_queue_ext->max_rx_cq_num);
1987                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1988                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1989         } else {
1990                 struct ena_admin_queue_feature_desc *max_queues =
1991                         &get_feat_ctx->max_queues;
1992                 io_tx_sq_num = max_queues->max_sq_num;
1993                 io_tx_cq_num = max_queues->max_cq_num;
1994                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1995         }
1996
1997         /* In case of LLQ use the llq number in the get feature cmd */
1998         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1999                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
2000
2001         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
2002         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
2003         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
2004
2005         if (unlikely(max_num_io_queues == 0)) {
2006                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
2007                 return -EFAULT;
2008         }
2009
2010         return max_num_io_queues;
2011 }
2012
2013 static void
2014 ena_set_offloads(struct ena_offloads *offloads,
2015                  struct ena_admin_feature_offload_desc *offload_desc)
2016 {
2017         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2018                 offloads->tx_offloads |= ENA_IPV4_TSO;
2019
2020         /* Tx IPv4 checksum offloads */
2021         if (offload_desc->tx &
2022             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
2023                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
2024         if (offload_desc->tx &
2025             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
2026                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
2027         if (offload_desc->tx &
2028             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2029                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
2030
2031         /* Tx IPv6 checksum offloads */
2032         if (offload_desc->tx &
2033             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
2034                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
2035         if (offload_desc->tx &
2036              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2037                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
2038
2039         /* Rx IPv4 checksum offloads */
2040         if (offload_desc->rx_supported &
2041             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
2042                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
2043         if (offload_desc->rx_supported &
2044             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2045                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
2046
2047         /* Rx IPv6 checksum offloads */
2048         if (offload_desc->rx_supported &
2049             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2050                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
2051
2052         if (offload_desc->rx_supported &
2053             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
2054                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
2055 }
2056
2057 static int ena_init_once(void)
2058 {
2059         static bool init_done;
2060
2061         if (init_done)
2062                 return 0;
2063
2064         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2065                 /* Init timer subsystem for the ENA timer service. */
2066                 rte_timer_subsystem_init();
2067                 /* Register handler for requests from secondary processes. */
2068                 rte_mp_action_register(ENA_MP_NAME, ena_mp_primary_handle);
2069         }
2070
2071         init_done = true;
2072         return 0;
2073 }
2074
2075 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
2076 {
2077         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
2078         struct rte_pci_device *pci_dev;
2079         struct rte_intr_handle *intr_handle;
2080         struct ena_adapter *adapter = eth_dev->data->dev_private;
2081         struct ena_com_dev *ena_dev = &adapter->ena_dev;
2082         struct ena_com_dev_get_features_ctx get_feat_ctx;
2083         struct ena_llq_configurations llq_config;
2084         const char *queue_type_str;
2085         uint32_t max_num_io_queues;
2086         int rc;
2087         static int adapters_found;
2088         bool disable_meta_caching;
2089
2090         eth_dev->dev_ops = &ena_dev_ops;
2091         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
2092         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
2093         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
2094
2095         rc = ena_init_once();
2096         if (rc != 0)
2097                 return rc;
2098
2099         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2100                 return 0;
2101
2102         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2103
2104         memset(adapter, 0, sizeof(struct ena_adapter));
2105         ena_dev = &adapter->ena_dev;
2106
2107         adapter->edev_data = eth_dev->data;
2108
2109         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2110
2111         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
2112                      pci_dev->addr.domain,
2113                      pci_dev->addr.bus,
2114                      pci_dev->addr.devid,
2115                      pci_dev->addr.function);
2116
2117         intr_handle = pci_dev->intr_handle;
2118
2119         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
2120         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
2121
2122         if (!adapter->regs) {
2123                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
2124                              ENA_REGS_BAR);
2125                 return -ENXIO;
2126         }
2127
2128         ena_dev->reg_bar = adapter->regs;
2129         /* Pass device data as a pointer which can be passed to the IO functions
2130          * by the ena_com (for example - the memory allocation).
2131          */
2132         ena_dev->dmadev = eth_dev->data;
2133
2134         adapter->id_number = adapters_found;
2135
2136         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
2137                  adapter->id_number);
2138
2139         adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2140
2141         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
2142         if (rc != 0) {
2143                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
2144                 goto err;
2145         }
2146
2147         /* device specific initialization routine */
2148         rc = ena_device_init(adapter, pci_dev, &get_feat_ctx);
2149         if (rc) {
2150                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
2151                 goto err;
2152         }
2153
2154         /* Check if device supports LSC */
2155         if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE)))
2156                 adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
2157
2158         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
2159                 adapter->use_large_llq_hdr);
2160         rc = ena_set_queues_placement_policy(adapter, ena_dev,
2161                                              &get_feat_ctx.llq, &llq_config);
2162         if (unlikely(rc)) {
2163                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
2164                 return rc;
2165         }
2166
2167         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
2168                 queue_type_str = "Regular";
2169         else
2170                 queue_type_str = "Low latency";
2171         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
2172
2173         calc_queue_ctx.ena_dev = ena_dev;
2174         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
2175
2176         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
2177         rc = ena_calc_io_queue_size(&calc_queue_ctx,
2178                 adapter->use_large_llq_hdr);
2179         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
2180                 rc = -EFAULT;
2181                 goto err_device_destroy;
2182         }
2183
2184         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
2185         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
2186         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
2187         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
2188         adapter->max_num_io_queues = max_num_io_queues;
2189
2190         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2191                 disable_meta_caching =
2192                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
2193                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
2194         } else {
2195                 disable_meta_caching = false;
2196         }
2197
2198         /* prepare ring structures */
2199         ena_init_rings(adapter, disable_meta_caching);
2200
2201         ena_config_debug_area(adapter);
2202
2203         /* Set max MTU for this device */
2204         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
2205
2206         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
2207
2208         /* Copy MAC address and point DPDK to it */
2209         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
2210         rte_ether_addr_copy((struct rte_ether_addr *)
2211                         get_feat_ctx.dev_attr.mac_addr,
2212                         (struct rte_ether_addr *)adapter->mac_addr);
2213
2214         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2215         if (unlikely(rc != 0)) {
2216                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
2217                 goto err_delete_debug_area;
2218         }
2219
2220         adapter->drv_stats = rte_zmalloc("adapter stats",
2221                                          sizeof(*adapter->drv_stats),
2222                                          RTE_CACHE_LINE_SIZE);
2223         if (!adapter->drv_stats) {
2224                 PMD_DRV_LOG(ERR,
2225                         "Failed to allocate memory for adapter statistics\n");
2226                 rc = -ENOMEM;
2227                 goto err_rss_destroy;
2228         }
2229
2230         rte_spinlock_init(&adapter->admin_lock);
2231
2232         rte_intr_callback_register(intr_handle,
2233                                    ena_interrupt_handler_rte,
2234                                    eth_dev);
2235         rte_intr_enable(intr_handle);
2236         ena_com_set_admin_polling_mode(ena_dev, false);
2237         ena_com_admin_aenq_enable(ena_dev);
2238
2239         rte_timer_init(&adapter->timer_wd);
2240
2241         adapters_found++;
2242         adapter->state = ENA_ADAPTER_STATE_INIT;
2243
2244         return 0;
2245
2246 err_rss_destroy:
2247         ena_com_rss_destroy(ena_dev);
2248 err_delete_debug_area:
2249         ena_com_delete_debug_area(ena_dev);
2250
2251 err_device_destroy:
2252         ena_com_delete_host_info(ena_dev);
2253         ena_com_admin_destroy(ena_dev);
2254
2255 err:
2256         return rc;
2257 }
2258
2259 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
2260 {
2261         struct ena_adapter *adapter = eth_dev->data->dev_private;
2262         struct ena_com_dev *ena_dev = &adapter->ena_dev;
2263
2264         if (adapter->state == ENA_ADAPTER_STATE_FREE)
2265                 return;
2266
2267         ena_com_set_admin_running_state(ena_dev, false);
2268
2269         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
2270                 ena_close(eth_dev);
2271
2272         ena_com_rss_destroy(ena_dev);
2273
2274         ena_com_delete_debug_area(ena_dev);
2275         ena_com_delete_host_info(ena_dev);
2276
2277         ena_com_abort_admin_commands(ena_dev);
2278         ena_com_wait_for_abort_completion(ena_dev);
2279         ena_com_admin_destroy(ena_dev);
2280         ena_com_mmio_reg_read_request_destroy(ena_dev);
2281
2282         adapter->state = ENA_ADAPTER_STATE_FREE;
2283 }
2284
2285 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
2286 {
2287         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2288                 return 0;
2289
2290         ena_destroy_device(eth_dev);
2291
2292         return 0;
2293 }
2294
2295 static int ena_dev_configure(struct rte_eth_dev *dev)
2296 {
2297         struct ena_adapter *adapter = dev->data->dev_private;
2298         int rc;
2299
2300         adapter->state = ENA_ADAPTER_STATE_CONFIG;
2301
2302         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2303                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2304         dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2305
2306         /* Scattered Rx cannot be turned off in the HW, so this capability must
2307          * be forced.
2308          */
2309         dev->data->scattered_rx = 1;
2310
2311         adapter->last_tx_comp_qid = 0;
2312
2313         adapter->missing_tx_completion_budget =
2314                 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2315
2316         /* To avoid detection of the spurious Tx completion timeout due to
2317          * application not calling the Tx cleanup function, set timeout for the
2318          * Tx queue which should be half of the missing completion timeout for a
2319          * safety. If there will be a lot of missing Tx completions in the
2320          * queue, they will be detected sooner or later.
2321          */
2322         adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2323
2324         rc = ena_configure_aenq(adapter);
2325
2326         return rc;
2327 }
2328
2329 static void ena_init_rings(struct ena_adapter *adapter,
2330                            bool disable_meta_caching)
2331 {
2332         size_t i;
2333
2334         for (i = 0; i < adapter->max_num_io_queues; i++) {
2335                 struct ena_ring *ring = &adapter->tx_ring[i];
2336
2337                 ring->configured = 0;
2338                 ring->type = ENA_RING_TYPE_TX;
2339                 ring->adapter = adapter;
2340                 ring->id = i;
2341                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2342                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2343                 ring->sgl_size = adapter->max_tx_sgl_size;
2344                 ring->disable_meta_caching = disable_meta_caching;
2345         }
2346
2347         for (i = 0; i < adapter->max_num_io_queues; i++) {
2348                 struct ena_ring *ring = &adapter->rx_ring[i];
2349
2350                 ring->configured = 0;
2351                 ring->type = ENA_RING_TYPE_RX;
2352                 ring->adapter = adapter;
2353                 ring->id = i;
2354                 ring->sgl_size = adapter->max_rx_sgl_size;
2355         }
2356 }
2357
2358 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2359 {
2360         uint64_t port_offloads = 0;
2361
2362         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2363                 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2364
2365         if (adapter->offloads.rx_offloads &
2366             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2367                 port_offloads |=
2368                         RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2369
2370         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2371                 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2372
2373         port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2374
2375         return port_offloads;
2376 }
2377
2378 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2379 {
2380         uint64_t port_offloads = 0;
2381
2382         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2383                 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2384
2385         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2386                 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2387         if (adapter->offloads.tx_offloads &
2388             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2389              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2390                 port_offloads |=
2391                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2392
2393         port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2394
2395         return port_offloads;
2396 }
2397
2398 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2399 {
2400         RTE_SET_USED(adapter);
2401
2402         return 0;
2403 }
2404
2405 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2406 {
2407         RTE_SET_USED(adapter);
2408
2409         return 0;
2410 }
2411
2412 static int ena_infos_get(struct rte_eth_dev *dev,
2413                           struct rte_eth_dev_info *dev_info)
2414 {
2415         struct ena_adapter *adapter;
2416         struct ena_com_dev *ena_dev;
2417
2418         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2419         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2420         adapter = dev->data->dev_private;
2421
2422         ena_dev = &adapter->ena_dev;
2423         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2424
2425         dev_info->speed_capa =
2426                         RTE_ETH_LINK_SPEED_1G   |
2427                         RTE_ETH_LINK_SPEED_2_5G |
2428                         RTE_ETH_LINK_SPEED_5G   |
2429                         RTE_ETH_LINK_SPEED_10G  |
2430                         RTE_ETH_LINK_SPEED_25G  |
2431                         RTE_ETH_LINK_SPEED_40G  |
2432                         RTE_ETH_LINK_SPEED_50G  |
2433                         RTE_ETH_LINK_SPEED_100G;
2434
2435         /* Inform framework about available features */
2436         dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2437         dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2438         dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2439         dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2440
2441         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2442         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2443
2444         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2445         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2446                 RTE_ETHER_CRC_LEN;
2447         dev_info->min_mtu = ENA_MIN_MTU;
2448         dev_info->max_mtu = adapter->max_mtu;
2449         dev_info->max_mac_addrs = 1;
2450
2451         dev_info->max_rx_queues = adapter->max_num_io_queues;
2452         dev_info->max_tx_queues = adapter->max_num_io_queues;
2453         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2454
2455         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2456         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2457         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2458                                         adapter->max_rx_sgl_size);
2459         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2460                                         adapter->max_rx_sgl_size);
2461
2462         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2463         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2464         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2465                                         adapter->max_tx_sgl_size);
2466         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2467                                         adapter->max_tx_sgl_size);
2468
2469         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2470         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2471
2472         return 0;
2473 }
2474
2475 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2476 {
2477         mbuf->data_len = len;
2478         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2479         mbuf->refcnt = 1;
2480         mbuf->next = NULL;
2481 }
2482
2483 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2484                                     struct ena_com_rx_buf_info *ena_bufs,
2485                                     uint32_t descs,
2486                                     uint16_t *next_to_clean,
2487                                     uint8_t offset)
2488 {
2489         struct rte_mbuf *mbuf;
2490         struct rte_mbuf *mbuf_head;
2491         struct ena_rx_buffer *rx_info;
2492         int rc;
2493         uint16_t ntc, len, req_id, buf = 0;
2494
2495         if (unlikely(descs == 0))
2496                 return NULL;
2497
2498         ntc = *next_to_clean;
2499
2500         len = ena_bufs[buf].len;
2501         req_id = ena_bufs[buf].req_id;
2502
2503         rx_info = &rx_ring->rx_buffer_info[req_id];
2504
2505         mbuf = rx_info->mbuf;
2506         RTE_ASSERT(mbuf != NULL);
2507
2508         ena_init_rx_mbuf(mbuf, len);
2509
2510         /* Fill the mbuf head with the data specific for 1st segment. */
2511         mbuf_head = mbuf;
2512         mbuf_head->nb_segs = descs;
2513         mbuf_head->port = rx_ring->port_id;
2514         mbuf_head->pkt_len = len;
2515         mbuf_head->data_off += offset;
2516
2517         rx_info->mbuf = NULL;
2518         rx_ring->empty_rx_reqs[ntc] = req_id;
2519         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2520
2521         while (--descs) {
2522                 ++buf;
2523                 len = ena_bufs[buf].len;
2524                 req_id = ena_bufs[buf].req_id;
2525
2526                 rx_info = &rx_ring->rx_buffer_info[req_id];
2527                 RTE_ASSERT(rx_info->mbuf != NULL);
2528
2529                 if (unlikely(len == 0)) {
2530                         /*
2531                          * Some devices can pass descriptor with the length 0.
2532                          * To avoid confusion, the PMD is simply putting the
2533                          * descriptor back, as it was never used. We'll avoid
2534                          * mbuf allocation that way.
2535                          */
2536                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2537                                 rx_info->mbuf, req_id);
2538                         if (unlikely(rc != 0)) {
2539                                 /* Free the mbuf in case of an error. */
2540                                 rte_mbuf_raw_free(rx_info->mbuf);
2541                         } else {
2542                                 /*
2543                                  * If there was no error, just exit the loop as
2544                                  * 0 length descriptor is always the last one.
2545                                  */
2546                                 break;
2547                         }
2548                 } else {
2549                         /* Create an mbuf chain. */
2550                         mbuf->next = rx_info->mbuf;
2551                         mbuf = mbuf->next;
2552
2553                         ena_init_rx_mbuf(mbuf, len);
2554                         mbuf_head->pkt_len += len;
2555                 }
2556
2557                 /*
2558                  * Mark the descriptor as depleted and perform necessary
2559                  * cleanup.
2560                  * This code will execute in two cases:
2561                  *  1. Descriptor len was greater than 0 - normal situation.
2562                  *  2. Descriptor len was 0 and we failed to add the descriptor
2563                  *     to the device. In that situation, we should try to add
2564                  *     the mbuf again in the populate routine and mark the
2565                  *     descriptor as used up by the device.
2566                  */
2567                 rx_info->mbuf = NULL;
2568                 rx_ring->empty_rx_reqs[ntc] = req_id;
2569                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2570         }
2571
2572         *next_to_clean = ntc;
2573
2574         return mbuf_head;
2575 }
2576
2577 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2578                                   uint16_t nb_pkts)
2579 {
2580         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2581         unsigned int free_queue_entries;
2582         uint16_t next_to_clean = rx_ring->next_to_clean;
2583         uint16_t descs_in_use;
2584         struct rte_mbuf *mbuf;
2585         uint16_t completed;
2586         struct ena_com_rx_ctx ena_rx_ctx;
2587         int i, rc = 0;
2588         bool fill_hash;
2589
2590 #ifdef RTE_ETHDEV_DEBUG_RX
2591         /* Check adapter state */
2592         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2593                 PMD_RX_LOG(ALERT,
2594                         "Trying to receive pkts while device is NOT running\n");
2595                 return 0;
2596         }
2597 #endif
2598
2599         fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2600
2601         descs_in_use = rx_ring->ring_size -
2602                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2603         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2604
2605         for (completed = 0; completed < nb_pkts; completed++) {
2606                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2607                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2608                 ena_rx_ctx.descs = 0;
2609                 ena_rx_ctx.pkt_offset = 0;
2610                 /* receive packet context */
2611                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2612                                     rx_ring->ena_com_io_sq,
2613                                     &ena_rx_ctx);
2614                 if (unlikely(rc)) {
2615                         PMD_RX_LOG(ERR,
2616                                 "Failed to get the packet from the device, rc: %d\n",
2617                                 rc);
2618                         if (rc == ENA_COM_NO_SPACE) {
2619                                 ++rx_ring->rx_stats.bad_desc_num;
2620                                 ena_trigger_reset(rx_ring->adapter,
2621                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS);
2622                         } else {
2623                                 ++rx_ring->rx_stats.bad_req_id;
2624                                 ena_trigger_reset(rx_ring->adapter,
2625                                         ENA_REGS_RESET_INV_RX_REQ_ID);
2626                         }
2627                         return 0;
2628                 }
2629
2630                 mbuf = ena_rx_mbuf(rx_ring,
2631                         ena_rx_ctx.ena_bufs,
2632                         ena_rx_ctx.descs,
2633                         &next_to_clean,
2634                         ena_rx_ctx.pkt_offset);
2635                 if (unlikely(mbuf == NULL)) {
2636                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2637                                 rx_ring->empty_rx_reqs[next_to_clean] =
2638                                         rx_ring->ena_bufs[i].req_id;
2639                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2640                                         next_to_clean, rx_ring->size_mask);
2641                         }
2642                         break;
2643                 }
2644
2645                 /* fill mbuf attributes if any */
2646                 ena_rx_mbuf_prepare(rx_ring, mbuf, &ena_rx_ctx, fill_hash);
2647
2648                 if (unlikely(mbuf->ol_flags &
2649                                 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD)))
2650                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2651
2652                 rx_pkts[completed] = mbuf;
2653                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2654         }
2655
2656         rx_ring->rx_stats.cnt += completed;
2657         rx_ring->next_to_clean = next_to_clean;
2658
2659         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2660
2661         /* Burst refill to save doorbells, memory barriers, const interval */
2662         if (free_queue_entries >= rx_ring->rx_free_thresh) {
2663                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2664                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2665         }
2666
2667         return completed;
2668 }
2669
2670 static uint16_t
2671 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2672                 uint16_t nb_pkts)
2673 {
2674         int32_t ret;
2675         uint32_t i;
2676         struct rte_mbuf *m;
2677         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2678         struct ena_adapter *adapter = tx_ring->adapter;
2679         struct rte_ipv4_hdr *ip_hdr;
2680         uint64_t ol_flags;
2681         uint64_t l4_csum_flag;
2682         uint64_t dev_offload_capa;
2683         uint16_t frag_field;
2684         bool need_pseudo_csum;
2685
2686         dev_offload_capa = adapter->offloads.tx_offloads;
2687         for (i = 0; i != nb_pkts; i++) {
2688                 m = tx_pkts[i];
2689                 ol_flags = m->ol_flags;
2690
2691                 /* Check if any offload flag was set */
2692                 if (ol_flags == 0)
2693                         continue;
2694
2695                 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2696                 /* SCTP checksum offload is not supported by the ENA. */
2697                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2698                     l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2699                         PMD_TX_LOG(DEBUG,
2700                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2701                                 i, ol_flags);
2702                         rte_errno = ENOTSUP;
2703                         return i;
2704                 }
2705
2706                 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2707                     !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2708                       m->nb_segs == tx_ring->sgl_size &&
2709                       m->data_len < tx_ring->tx_max_header_size))) {
2710                         PMD_TX_LOG(DEBUG,
2711                                 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2712                                 i, m->nb_segs);
2713                         rte_errno = EINVAL;
2714                         return i;
2715                 }
2716
2717 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2718                 /* Check if requested offload is also enabled for the queue */
2719                 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2720                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2721                     (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2722                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2723                     (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2724                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2725                         PMD_TX_LOG(DEBUG,
2726                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2727                                 i, m->nb_segs, tx_ring->id);
2728                         rte_errno = EINVAL;
2729                         return i;
2730                 }
2731
2732                 /* The caller is obligated to set l2 and l3 len if any cksum
2733                  * offload is enabled.
2734                  */
2735                 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2736                     (m->l2_len == 0 || m->l3_len == 0))) {
2737                         PMD_TX_LOG(DEBUG,
2738                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2739                                 i);
2740                         rte_errno = EINVAL;
2741                         return i;
2742                 }
2743                 ret = rte_validate_tx_offload(m);
2744                 if (ret != 0) {
2745                         rte_errno = -ret;
2746                         return i;
2747                 }
2748 #endif
2749
2750                 /* Verify HW support for requested offloads and determine if
2751                  * pseudo header checksum is needed.
2752                  */
2753                 need_pseudo_csum = false;
2754                 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2755                         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2756                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2757                                 rte_errno = ENOTSUP;
2758                                 return i;
2759                         }
2760
2761                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2762                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2763                                 rte_errno = ENOTSUP;
2764                                 return i;
2765                         }
2766
2767                         /* Check HW capabilities and if pseudo csum is needed
2768                          * for L4 offloads.
2769                          */
2770                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2771                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2772                                 if (dev_offload_capa &
2773                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2774                                         need_pseudo_csum = true;
2775                                 } else {
2776                                         rte_errno = ENOTSUP;
2777                                         return i;
2778                                 }
2779                         }
2780
2781                         /* Parse the DF flag */
2782                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2783                                 struct rte_ipv4_hdr *, m->l2_len);
2784                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2785                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2786                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2787                         } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2788                                 /* In case we are supposed to TSO and have DF
2789                                  * not set (DF=0) hardware must be provided with
2790                                  * partial checksum.
2791                                  */
2792                                 need_pseudo_csum = true;
2793                         }
2794                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2795                         /* There is no support for IPv6 TSO as for now. */
2796                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2797                                 rte_errno = ENOTSUP;
2798                                 return i;
2799                         }
2800
2801                         /* Check HW capabilities and if pseudo csum is needed */
2802                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2803                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2804                                 if (dev_offload_capa &
2805                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2806                                         need_pseudo_csum = true;
2807                                 } else {
2808                                         rte_errno = ENOTSUP;
2809                                         return i;
2810                                 }
2811                         }
2812                 }
2813
2814                 if (need_pseudo_csum) {
2815                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2816                         if (ret != 0) {
2817                                 rte_errno = -ret;
2818                                 return i;
2819                         }
2820                 }
2821         }
2822
2823         return i;
2824 }
2825
2826 static void ena_update_hints(struct ena_adapter *adapter,
2827                              struct ena_admin_ena_hw_hints *hints)
2828 {
2829         if (hints->admin_completion_tx_timeout)
2830                 adapter->ena_dev.admin_queue.completion_timeout =
2831                         hints->admin_completion_tx_timeout * 1000;
2832
2833         if (hints->mmio_read_timeout)
2834                 /* convert to usec */
2835                 adapter->ena_dev.mmio_read.reg_read_to =
2836                         hints->mmio_read_timeout * 1000;
2837
2838         if (hints->driver_watchdog_timeout) {
2839                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2840                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2841                 else
2842                         // Convert msecs to ticks
2843                         adapter->keep_alive_timeout =
2844                                 (hints->driver_watchdog_timeout *
2845                                 rte_get_timer_hz()) / 1000;
2846         }
2847 }
2848
2849 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2850         struct ena_tx_buffer *tx_info,
2851         struct rte_mbuf *mbuf,
2852         void **push_header,
2853         uint16_t *header_len)
2854 {
2855         struct ena_com_buf *ena_buf;
2856         uint16_t delta, seg_len, push_len;
2857
2858         delta = 0;
2859         seg_len = mbuf->data_len;
2860
2861         tx_info->mbuf = mbuf;
2862         ena_buf = tx_info->bufs;
2863
2864         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2865                 /*
2866                  * Tx header might be (and will be in most cases) smaller than
2867                  * tx_max_header_size. But it's not an issue to send more data
2868                  * to the device, than actually needed if the mbuf size is
2869                  * greater than tx_max_header_size.
2870                  */
2871                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2872                 *header_len = push_len;
2873
2874                 if (likely(push_len <= seg_len)) {
2875                         /* If the push header is in the single segment, then
2876                          * just point it to the 1st mbuf data.
2877                          */
2878                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2879                 } else {
2880                         /* If the push header lays in the several segments, copy
2881                          * it to the intermediate buffer.
2882                          */
2883                         rte_pktmbuf_read(mbuf, 0, push_len,
2884                                 tx_ring->push_buf_intermediate_buf);
2885                         *push_header = tx_ring->push_buf_intermediate_buf;
2886                         delta = push_len - seg_len;
2887                 }
2888         } else {
2889                 *push_header = NULL;
2890                 *header_len = 0;
2891                 push_len = 0;
2892         }
2893
2894         /* Process first segment taking into consideration pushed header */
2895         if (seg_len > push_len) {
2896                 ena_buf->paddr = mbuf->buf_iova +
2897                                 mbuf->data_off +
2898                                 push_len;
2899                 ena_buf->len = seg_len - push_len;
2900                 ena_buf++;
2901                 tx_info->num_of_bufs++;
2902         }
2903
2904         while ((mbuf = mbuf->next) != NULL) {
2905                 seg_len = mbuf->data_len;
2906
2907                 /* Skip mbufs if whole data is pushed as a header */
2908                 if (unlikely(delta > seg_len)) {
2909                         delta -= seg_len;
2910                         continue;
2911                 }
2912
2913                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2914                 ena_buf->len = seg_len - delta;
2915                 ena_buf++;
2916                 tx_info->num_of_bufs++;
2917
2918                 delta = 0;
2919         }
2920 }
2921
2922 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2923 {
2924         struct ena_tx_buffer *tx_info;
2925         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2926         uint16_t next_to_use;
2927         uint16_t header_len;
2928         uint16_t req_id;
2929         void *push_header;
2930         int nb_hw_desc;
2931         int rc;
2932
2933         /* Checking for space for 2 additional metadata descriptors due to
2934          * possible header split and metadata descriptor
2935          */
2936         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2937                                           mbuf->nb_segs + 2)) {
2938                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2939                 return ENA_COM_NO_MEM;
2940         }
2941
2942         next_to_use = tx_ring->next_to_use;
2943
2944         req_id = tx_ring->empty_tx_reqs[next_to_use];
2945         tx_info = &tx_ring->tx_buffer_info[req_id];
2946         tx_info->num_of_bufs = 0;
2947         RTE_ASSERT(tx_info->mbuf == NULL);
2948
2949         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2950
2951         ena_tx_ctx.ena_bufs = tx_info->bufs;
2952         ena_tx_ctx.push_header = push_header;
2953         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2954         ena_tx_ctx.req_id = req_id;
2955         ena_tx_ctx.header_len = header_len;
2956
2957         /* Set Tx offloads flags, if applicable */
2958         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2959                 tx_ring->disable_meta_caching);
2960
2961         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2962                         &ena_tx_ctx))) {
2963                 PMD_TX_LOG(DEBUG,
2964                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2965                         tx_ring->id);
2966                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2967                 tx_ring->tx_stats.doorbells++;
2968                 tx_ring->pkts_without_db = false;
2969         }
2970
2971         /* prepare the packet's descriptors to dma engine */
2972         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2973                 &nb_hw_desc);
2974         if (unlikely(rc)) {
2975                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2976                 ++tx_ring->tx_stats.prepare_ctx_err;
2977                 ena_trigger_reset(tx_ring->adapter,
2978                         ENA_REGS_RESET_DRIVER_INVALID_STATE);
2979                 return rc;
2980         }
2981
2982         tx_info->tx_descs = nb_hw_desc;
2983         tx_info->timestamp = rte_get_timer_cycles();
2984
2985         tx_ring->tx_stats.cnt++;
2986         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2987
2988         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2989                 tx_ring->size_mask);
2990
2991         return 0;
2992 }
2993
2994 static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt)
2995 {
2996         struct ena_ring *tx_ring = (struct ena_ring *)txp;
2997         unsigned int total_tx_descs = 0;
2998         unsigned int total_tx_pkts = 0;
2999         uint16_t cleanup_budget;
3000         uint16_t next_to_clean = tx_ring->next_to_clean;
3001
3002         /*
3003          * If free_pkt_cnt is equal to 0, it means that the user requested
3004          * full cleanup, so attempt to release all Tx descriptors
3005          * (ring_size - 1 -> size_mask)
3006          */
3007         cleanup_budget = (free_pkt_cnt == 0) ? tx_ring->size_mask : free_pkt_cnt;
3008
3009         while (likely(total_tx_pkts < cleanup_budget)) {
3010                 struct rte_mbuf *mbuf;
3011                 struct ena_tx_buffer *tx_info;
3012                 uint16_t req_id;
3013
3014                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
3015                         break;
3016
3017                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
3018                         break;
3019
3020                 /* Get Tx info & store how many descs were processed  */
3021                 tx_info = &tx_ring->tx_buffer_info[req_id];
3022                 tx_info->timestamp = 0;
3023
3024                 mbuf = tx_info->mbuf;
3025                 rte_pktmbuf_free(mbuf);
3026
3027                 tx_info->mbuf = NULL;
3028                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
3029
3030                 total_tx_descs += tx_info->tx_descs;
3031                 total_tx_pkts++;
3032
3033                 /* Put back descriptor to the ring for reuse */
3034                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
3035                         tx_ring->size_mask);
3036         }
3037
3038         if (likely(total_tx_descs > 0)) {
3039                 /* acknowledge completion of sent packets */
3040                 tx_ring->next_to_clean = next_to_clean;
3041                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
3042                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
3043         }
3044
3045         /* Notify completion handler that full cleanup was performed */
3046         if (free_pkt_cnt == 0 || total_tx_pkts < cleanup_budget)
3047                 tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
3048
3049         return total_tx_pkts;
3050 }
3051
3052 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
3053                                   uint16_t nb_pkts)
3054 {
3055         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
3056         int available_desc;
3057         uint16_t sent_idx = 0;
3058
3059 #ifdef RTE_ETHDEV_DEBUG_TX
3060         /* Check adapter state */
3061         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
3062                 PMD_TX_LOG(ALERT,
3063                         "Trying to xmit pkts while device is NOT running\n");
3064                 return 0;
3065         }
3066 #endif
3067
3068         available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3069         if (available_desc < tx_ring->tx_free_thresh)
3070                 ena_tx_cleanup((void *)tx_ring, 0);
3071
3072         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
3073                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
3074                         break;
3075                 tx_ring->pkts_without_db = true;
3076                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
3077                         tx_ring->size_mask)]);
3078         }
3079
3080         /* If there are ready packets to be xmitted... */
3081         if (likely(tx_ring->pkts_without_db)) {
3082                 /* ...let HW do its best :-) */
3083                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
3084                 tx_ring->tx_stats.doorbells++;
3085                 tx_ring->pkts_without_db = false;
3086         }
3087
3088         tx_ring->tx_stats.available_desc =
3089                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3090         tx_ring->tx_stats.tx_poll++;
3091
3092         return sent_idx;
3093 }
3094
3095 int ena_copy_eni_stats(struct ena_adapter *adapter, struct ena_stats_eni *stats)
3096 {
3097         int rc;
3098
3099         rte_spinlock_lock(&adapter->admin_lock);
3100         /* Retrieve and store the latest statistics from the AQ. This ensures
3101          * that previous value is returned in case of a com error.
3102          */
3103         rc = ENA_PROXY(adapter, ena_com_get_eni_stats, &adapter->ena_dev,
3104                 (struct ena_admin_eni_stats *)stats);
3105         rte_spinlock_unlock(&adapter->admin_lock);
3106         if (rc != 0) {
3107                 if (rc == ENA_COM_UNSUPPORTED) {
3108                         PMD_DRV_LOG(DEBUG,
3109                                 "Retrieving ENI metrics is not supported\n");
3110                 } else {
3111                         PMD_DRV_LOG(WARNING,
3112                                 "Failed to get ENI metrics, rc: %d\n", rc);
3113                 }
3114                 return rc;
3115         }
3116
3117         return 0;
3118 }
3119
3120 /**
3121  * DPDK callback to retrieve names of extended device statistics
3122  *
3123  * @param dev
3124  *   Pointer to Ethernet device structure.
3125  * @param[out] xstats_names
3126  *   Buffer to insert names into.
3127  * @param n
3128  *   Number of names.
3129  *
3130  * @return
3131  *   Number of xstats names.
3132  */
3133 static int ena_xstats_get_names(struct rte_eth_dev *dev,
3134                                 struct rte_eth_xstat_name *xstats_names,
3135                                 unsigned int n)
3136 {
3137         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3138         unsigned int stat, i, count = 0;
3139
3140         if (n < xstats_count || !xstats_names)
3141                 return xstats_count;
3142
3143         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
3144                 strcpy(xstats_names[count].name,
3145                         ena_stats_global_strings[stat].name);
3146
3147         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
3148                 strcpy(xstats_names[count].name,
3149                         ena_stats_eni_strings[stat].name);
3150
3151         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
3152                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
3153                         snprintf(xstats_names[count].name,
3154                                 sizeof(xstats_names[count].name),
3155                                 "rx_q%d_%s", i,
3156                                 ena_stats_rx_strings[stat].name);
3157
3158         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
3159                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
3160                         snprintf(xstats_names[count].name,
3161                                 sizeof(xstats_names[count].name),
3162                                 "tx_q%d_%s", i,
3163                                 ena_stats_tx_strings[stat].name);
3164
3165         return xstats_count;
3166 }
3167
3168 /**
3169  * DPDK callback to retrieve names of extended device statistics for the given
3170  * ids.
3171  *
3172  * @param dev
3173  *   Pointer to Ethernet device structure.
3174  * @param[out] xstats_names
3175  *   Buffer to insert names into.
3176  * @param ids
3177  *   IDs array for which the names should be retrieved.
3178  * @param size
3179  *   Number of ids.
3180  *
3181  * @return
3182  *   Positive value: number of xstats names. Negative value: error code.
3183  */
3184 static int ena_xstats_get_names_by_id(struct rte_eth_dev *dev,
3185                                       const uint64_t *ids,
3186                                       struct rte_eth_xstat_name *xstats_names,
3187                                       unsigned int size)
3188 {
3189         uint64_t xstats_count = ena_xstats_calc_num(dev->data);
3190         uint64_t id, qid;
3191         unsigned int i;
3192
3193         if (xstats_names == NULL)
3194                 return xstats_count;
3195
3196         for (i = 0; i < size; ++i) {
3197                 id = ids[i];
3198                 if (id > xstats_count) {
3199                         PMD_DRV_LOG(ERR,
3200                                 "ID value out of range: id=%" PRIu64 ", xstats_num=%" PRIu64 "\n",
3201                                  id, xstats_count);
3202                         return -EINVAL;
3203                 }
3204
3205                 if (id < ENA_STATS_ARRAY_GLOBAL) {
3206                         strcpy(xstats_names[i].name,
3207                                ena_stats_global_strings[id].name);
3208                         continue;
3209                 }
3210
3211                 id -= ENA_STATS_ARRAY_GLOBAL;
3212                 if (id < ENA_STATS_ARRAY_ENI) {
3213                         strcpy(xstats_names[i].name,
3214                                ena_stats_eni_strings[id].name);
3215                         continue;
3216                 }
3217
3218                 id -= ENA_STATS_ARRAY_ENI;
3219                 if (id < ENA_STATS_ARRAY_RX) {
3220                         qid = id / dev->data->nb_rx_queues;
3221                         id %= dev->data->nb_rx_queues;
3222                         snprintf(xstats_names[i].name,
3223                                  sizeof(xstats_names[i].name),
3224                                  "rx_q%" PRIu64 "d_%s",
3225                                  qid, ena_stats_rx_strings[id].name);
3226                         continue;
3227                 }
3228
3229                 id -= ENA_STATS_ARRAY_RX;
3230                 /* Although this condition is not needed, it was added for
3231                  * compatibility if new xstat structure would be ever added.
3232                  */
3233                 if (id < ENA_STATS_ARRAY_TX) {
3234                         qid = id / dev->data->nb_tx_queues;
3235                         id %= dev->data->nb_tx_queues;
3236                         snprintf(xstats_names[i].name,
3237                                  sizeof(xstats_names[i].name),
3238                                  "tx_q%" PRIu64 "_%s",
3239                                  qid, ena_stats_tx_strings[id].name);
3240                         continue;
3241                 }
3242         }
3243
3244         return i;
3245 }
3246
3247 /**
3248  * DPDK callback to get extended device statistics.
3249  *
3250  * @param dev
3251  *   Pointer to Ethernet device structure.
3252  * @param[out] stats
3253  *   Stats table output buffer.
3254  * @param n
3255  *   The size of the stats table.
3256  *
3257  * @return
3258  *   Number of xstats on success, negative on failure.
3259  */
3260 static int ena_xstats_get(struct rte_eth_dev *dev,
3261                           struct rte_eth_xstat *xstats,
3262                           unsigned int n)
3263 {
3264         struct ena_adapter *adapter = dev->data->dev_private;
3265         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3266         struct ena_stats_eni eni_stats;
3267         unsigned int stat, i, count = 0;
3268         int stat_offset;
3269         void *stats_begin;
3270
3271         if (n < xstats_count)
3272                 return xstats_count;
3273
3274         if (!xstats)
3275                 return 0;
3276
3277         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
3278                 stat_offset = ena_stats_global_strings[stat].stat_offset;
3279                 stats_begin = &adapter->dev_stats;
3280
3281                 xstats[count].id = count;
3282                 xstats[count].value = *((uint64_t *)
3283                         ((char *)stats_begin + stat_offset));
3284         }
3285
3286         /* Even if the function below fails, we should copy previous (or initial
3287          * values) to keep structure of rte_eth_xstat consistent.
3288          */
3289         ena_copy_eni_stats(adapter, &eni_stats);
3290         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
3291                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
3292                 stats_begin = &eni_stats;
3293
3294                 xstats[count].id = count;
3295                 xstats[count].value = *((uint64_t *)
3296                     ((char *)stats_begin + stat_offset));
3297         }
3298
3299         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
3300                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
3301                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
3302                         stats_begin = &adapter->rx_ring[i].rx_stats;
3303
3304                         xstats[count].id = count;
3305                         xstats[count].value = *((uint64_t *)
3306                                 ((char *)stats_begin + stat_offset));
3307                 }
3308         }
3309
3310         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
3311                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
3312                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
3313                         stats_begin = &adapter->tx_ring[i].rx_stats;
3314
3315                         xstats[count].id = count;
3316                         xstats[count].value = *((uint64_t *)
3317                                 ((char *)stats_begin + stat_offset));
3318                 }
3319         }
3320
3321         return count;
3322 }
3323
3324 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
3325                                 const uint64_t *ids,
3326                                 uint64_t *values,
3327                                 unsigned int n)
3328 {
3329         struct ena_adapter *adapter = dev->data->dev_private;
3330         struct ena_stats_eni eni_stats;
3331         uint64_t id;
3332         uint64_t rx_entries, tx_entries;
3333         unsigned int i;
3334         int qid;
3335         int valid = 0;
3336         bool was_eni_copied = false;
3337
3338         for (i = 0; i < n; ++i) {
3339                 id = ids[i];
3340                 /* Check if id belongs to global statistics */
3341                 if (id < ENA_STATS_ARRAY_GLOBAL) {
3342                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
3343                         ++valid;
3344                         continue;
3345                 }
3346
3347                 /* Check if id belongs to ENI statistics */
3348                 id -= ENA_STATS_ARRAY_GLOBAL;
3349                 if (id < ENA_STATS_ARRAY_ENI) {
3350                         /* Avoid reading ENI stats multiple times in a single
3351                          * function call, as it requires communication with the
3352                          * admin queue.
3353                          */
3354                         if (!was_eni_copied) {
3355                                 was_eni_copied = true;
3356                                 ena_copy_eni_stats(adapter, &eni_stats);
3357                         }
3358                         values[i] = *((uint64_t *)&eni_stats + id);
3359                         ++valid;
3360                         continue;
3361                 }
3362
3363                 /* Check if id belongs to rx queue statistics */
3364                 id -= ENA_STATS_ARRAY_ENI;
3365                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
3366                 if (id < rx_entries) {
3367                         qid = id % dev->data->nb_rx_queues;
3368                         id /= dev->data->nb_rx_queues;
3369                         values[i] = *((uint64_t *)
3370                                 &adapter->rx_ring[qid].rx_stats + id);
3371                         ++valid;
3372                         continue;
3373                 }
3374                                 /* Check if id belongs to rx queue statistics */
3375                 id -= rx_entries;
3376                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
3377                 if (id < tx_entries) {
3378                         qid = id % dev->data->nb_tx_queues;
3379                         id /= dev->data->nb_tx_queues;
3380                         values[i] = *((uint64_t *)
3381                                 &adapter->tx_ring[qid].tx_stats + id);
3382                         ++valid;
3383                         continue;
3384                 }
3385         }
3386
3387         return valid;
3388 }
3389
3390 static int ena_process_uint_devarg(const char *key,
3391                                   const char *value,
3392                                   void *opaque)
3393 {
3394         struct ena_adapter *adapter = opaque;
3395         char *str_end;
3396         uint64_t uint_value;
3397
3398         uint_value = strtoull(value, &str_end, 10);
3399         if (value == str_end) {
3400                 PMD_INIT_LOG(ERR,
3401                         "Invalid value for key '%s'. Only uint values are accepted.\n",
3402                         key);
3403                 return -EINVAL;
3404         }
3405
3406         if (strcmp(key, ENA_DEVARG_MISS_TXC_TO) == 0) {
3407                 if (uint_value > ENA_MAX_TX_TIMEOUT_SECONDS) {
3408                         PMD_INIT_LOG(ERR,
3409                                 "Tx timeout too high: %" PRIu64 " sec. Maximum allowed: %d sec.\n",
3410                                 uint_value, ENA_MAX_TX_TIMEOUT_SECONDS);
3411                         return -EINVAL;
3412                 } else if (uint_value == 0) {
3413                         PMD_INIT_LOG(INFO,
3414                                 "Check for missing Tx completions has been disabled.\n");
3415                         adapter->missing_tx_completion_to =
3416                                 ENA_HW_HINTS_NO_TIMEOUT;
3417                 } else {
3418                         PMD_INIT_LOG(INFO,
3419                                 "Tx packet completion timeout set to %" PRIu64 " seconds.\n",
3420                                 uint_value);
3421                         adapter->missing_tx_completion_to =
3422                                 uint_value * rte_get_timer_hz();
3423                 }
3424         }
3425
3426         return 0;
3427 }
3428
3429 static int ena_process_bool_devarg(const char *key,
3430                                    const char *value,
3431                                    void *opaque)
3432 {
3433         struct ena_adapter *adapter = opaque;
3434         bool bool_value;
3435
3436         /* Parse the value. */
3437         if (strcmp(value, "1") == 0) {
3438                 bool_value = true;
3439         } else if (strcmp(value, "0") == 0) {
3440                 bool_value = false;
3441         } else {
3442                 PMD_INIT_LOG(ERR,
3443                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3444                         value, key);
3445                 return -EINVAL;
3446         }
3447
3448         /* Now, assign it to the proper adapter field. */
3449         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3450                 adapter->use_large_llq_hdr = bool_value;
3451
3452         return 0;
3453 }
3454
3455 static int ena_parse_devargs(struct ena_adapter *adapter,
3456                              struct rte_devargs *devargs)
3457 {
3458         static const char * const allowed_args[] = {
3459                 ENA_DEVARG_LARGE_LLQ_HDR,
3460                 ENA_DEVARG_MISS_TXC_TO,
3461                 NULL,
3462         };
3463         struct rte_kvargs *kvlist;
3464         int rc;
3465
3466         if (devargs == NULL)
3467                 return 0;
3468
3469         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3470         if (kvlist == NULL) {
3471                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3472                         devargs->args);
3473                 return -EINVAL;
3474         }
3475
3476         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3477                 ena_process_bool_devarg, adapter);
3478         if (rc != 0)
3479                 goto exit;
3480         rc = rte_kvargs_process(kvlist, ENA_DEVARG_MISS_TXC_TO,
3481                 ena_process_uint_devarg, adapter);
3482
3483 exit:
3484         rte_kvargs_free(kvlist);
3485
3486         return rc;
3487 }
3488
3489 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3490 {
3491         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3492         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3493         int rc;
3494         uint16_t vectors_nb, i;
3495         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3496
3497         if (!rx_intr_requested)
3498                 return 0;
3499
3500         if (!rte_intr_cap_multiple(intr_handle)) {
3501                 PMD_DRV_LOG(ERR,
3502                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3503                 return -ENOTSUP;
3504         }
3505
3506         /* Disable interrupt mapping before the configuration starts. */
3507         rte_intr_disable(intr_handle);
3508
3509         /* Verify if there are enough vectors available. */
3510         vectors_nb = dev->data->nb_rx_queues;
3511         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3512                 PMD_DRV_LOG(ERR,
3513                         "Too many Rx interrupts requested, maximum number: %d\n",
3514                         RTE_MAX_RXTX_INTR_VEC_ID);
3515                 rc = -ENOTSUP;
3516                 goto enable_intr;
3517         }
3518
3519         /* Allocate the vector list */
3520         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3521                                            dev->data->nb_rx_queues)) {
3522                 PMD_DRV_LOG(ERR,
3523                         "Failed to allocate interrupt vector for %d queues\n",
3524                         dev->data->nb_rx_queues);
3525                 rc = -ENOMEM;
3526                 goto enable_intr;
3527         }
3528
3529         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3530         if (rc != 0)
3531                 goto free_intr_vec;
3532
3533         if (!rte_intr_allow_others(intr_handle)) {
3534                 PMD_DRV_LOG(ERR,
3535                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3536                 goto disable_intr_efd;
3537         }
3538
3539         for (i = 0; i < vectors_nb; ++i)
3540                 if (rte_intr_vec_list_index_set(intr_handle, i,
3541                                            RTE_INTR_VEC_RXTX_OFFSET + i))
3542                         goto disable_intr_efd;
3543
3544         rte_intr_enable(intr_handle);
3545         return 0;
3546
3547 disable_intr_efd:
3548         rte_intr_efd_disable(intr_handle);
3549 free_intr_vec:
3550         rte_intr_vec_list_free(intr_handle);
3551 enable_intr:
3552         rte_intr_enable(intr_handle);
3553         return rc;
3554 }
3555
3556 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3557                                  uint16_t queue_id,
3558                                  bool unmask)
3559 {
3560         struct ena_adapter *adapter = dev->data->dev_private;
3561         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3562         struct ena_eth_io_intr_reg intr_reg;
3563
3564         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3565         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3566 }
3567
3568 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3569                                     uint16_t queue_id)
3570 {
3571         ena_rx_queue_intr_set(dev, queue_id, true);
3572
3573         return 0;
3574 }
3575
3576 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3577                                      uint16_t queue_id)
3578 {
3579         ena_rx_queue_intr_set(dev, queue_id, false);
3580
3581         return 0;
3582 }
3583
3584 static int ena_configure_aenq(struct ena_adapter *adapter)
3585 {
3586         uint32_t aenq_groups = adapter->all_aenq_groups;
3587         int rc;
3588
3589         /* All_aenq_groups holds all AENQ functions supported by the device and
3590          * the HW, so at first we need to be sure the LSC request is valid.
3591          */
3592         if (adapter->edev_data->dev_conf.intr_conf.lsc != 0) {
3593                 if (!(aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) {
3594                         PMD_DRV_LOG(ERR,
3595                                 "LSC requested, but it's not supported by the AENQ\n");
3596                         return -EINVAL;
3597                 }
3598         } else {
3599                 /* If LSC wasn't enabled by the app, let's enable all supported
3600                  * AENQ procedures except the LSC.
3601                  */
3602                 aenq_groups &= ~BIT(ENA_ADMIN_LINK_CHANGE);
3603         }
3604
3605         rc = ena_com_set_aenq_config(&adapter->ena_dev, aenq_groups);
3606         if (rc != 0) {
3607                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc=%d\n", rc);
3608                 return rc;
3609         }
3610
3611         adapter->active_aenq_groups = aenq_groups;
3612
3613         return 0;
3614 }
3615
3616 int ena_mp_indirect_table_set(struct ena_adapter *adapter)
3617 {
3618         return ENA_PROXY(adapter, ena_com_indirect_table_set, &adapter->ena_dev);
3619 }
3620
3621 int ena_mp_indirect_table_get(struct ena_adapter *adapter,
3622                               uint32_t *indirect_table)
3623 {
3624         return ENA_PROXY(adapter, ena_com_indirect_table_get, &adapter->ena_dev,
3625                 indirect_table);
3626 }
3627
3628 /*********************************************************************
3629  *  ena_plat_dpdk.h functions implementations
3630  *********************************************************************/
3631
3632 const struct rte_memzone *
3633 ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size,
3634                        int socket_id, unsigned int alignment, void **virt_addr,
3635                        dma_addr_t *phys_addr)
3636 {
3637         char z_name[RTE_MEMZONE_NAMESIZE];
3638         struct ena_adapter *adapter = data->dev_private;
3639         const struct rte_memzone *memzone;
3640         int rc;
3641
3642         rc = snprintf(z_name, RTE_MEMZONE_NAMESIZE, "ena_p%d_mz%" PRIu64 "",
3643                 data->port_id, adapter->memzone_cnt);
3644         if (rc >= RTE_MEMZONE_NAMESIZE) {
3645                 PMD_DRV_LOG(ERR,
3646                         "Name for the ena_com memzone is too long. Port: %d, mz_num: %" PRIu64 "\n",
3647                         data->port_id, adapter->memzone_cnt);
3648                 goto error;
3649         }
3650         adapter->memzone_cnt++;
3651
3652         memzone = rte_memzone_reserve_aligned(z_name, size, socket_id,
3653                 RTE_MEMZONE_IOVA_CONTIG, alignment);
3654         if (memzone == NULL) {
3655                 PMD_DRV_LOG(ERR, "Failed to allocate ena_com memzone: %s\n",
3656                         z_name);
3657                 goto error;
3658         }
3659
3660         memset(memzone->addr, 0, size);
3661         *virt_addr = memzone->addr;
3662         *phys_addr = memzone->iova;
3663
3664         return memzone;
3665
3666 error:
3667         *virt_addr = NULL;
3668         *phys_addr = 0;
3669
3670         return NULL;
3671 }
3672
3673
3674 /*********************************************************************
3675  *  PMD configuration
3676  *********************************************************************/
3677 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3678         struct rte_pci_device *pci_dev)
3679 {
3680         return rte_eth_dev_pci_generic_probe(pci_dev,
3681                 sizeof(struct ena_adapter), eth_ena_dev_init);
3682 }
3683
3684 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3685 {
3686         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3687 }
3688
3689 static struct rte_pci_driver rte_ena_pmd = {
3690         .id_table = pci_id_ena_map,
3691         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3692                      RTE_PCI_DRV_WC_ACTIVATE,
3693         .probe = eth_ena_pci_probe,
3694         .remove = eth_ena_pci_remove,
3695 };
3696
3697 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3698 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3699 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3700 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3701 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3702 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3703 #ifdef RTE_ETHDEV_DEBUG_RX
3704 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3705 #endif
3706 #ifdef RTE_ETHDEV_DEBUG_TX
3707 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3708 #endif
3709 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3710
3711 /******************************************************************************
3712  ******************************** AENQ Handlers *******************************
3713  *****************************************************************************/
3714 static void ena_update_on_link_change(void *adapter_data,
3715                                       struct ena_admin_aenq_entry *aenq_e)
3716 {
3717         struct rte_eth_dev *eth_dev = adapter_data;
3718         struct ena_adapter *adapter = eth_dev->data->dev_private;
3719         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3720         uint32_t status;
3721
3722         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3723
3724         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3725         adapter->link_status = status;
3726
3727         ena_link_update(eth_dev, 0);
3728         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3729 }
3730
3731 static void ena_notification(void *adapter_data,
3732                              struct ena_admin_aenq_entry *aenq_e)
3733 {
3734         struct rte_eth_dev *eth_dev = adapter_data;
3735         struct ena_adapter *adapter = eth_dev->data->dev_private;
3736         struct ena_admin_ena_hw_hints *hints;
3737
3738         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3739                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3740                         aenq_e->aenq_common_desc.group,
3741                         ENA_ADMIN_NOTIFICATION);
3742
3743         switch (aenq_e->aenq_common_desc.syndrome) {
3744         case ENA_ADMIN_UPDATE_HINTS:
3745                 hints = (struct ena_admin_ena_hw_hints *)
3746                         (&aenq_e->inline_data_w4);
3747                 ena_update_hints(adapter, hints);
3748                 break;
3749         default:
3750                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3751                         aenq_e->aenq_common_desc.syndrome);
3752         }
3753 }
3754
3755 static void ena_keep_alive(void *adapter_data,
3756                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3757 {
3758         struct rte_eth_dev *eth_dev = adapter_data;
3759         struct ena_adapter *adapter = eth_dev->data->dev_private;
3760         struct ena_admin_aenq_keep_alive_desc *desc;
3761         uint64_t rx_drops;
3762         uint64_t tx_drops;
3763
3764         adapter->timestamp_wd = rte_get_timer_cycles();
3765
3766         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3767         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3768         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3769
3770         adapter->drv_stats->rx_drops = rx_drops;
3771         adapter->dev_stats.tx_drops = tx_drops;
3772 }
3773
3774 /**
3775  * This handler will called for unknown event group or unimplemented handlers
3776  **/
3777 static void unimplemented_aenq_handler(__rte_unused void *data,
3778                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3779 {
3780         PMD_DRV_LOG(ERR,
3781                 "Unknown event was received or event with unimplemented handler\n");
3782 }
3783
3784 static struct ena_aenq_handlers aenq_handlers = {
3785         .handlers = {
3786                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3787                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3788                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3789         },
3790         .unimplemented_handler = unimplemented_aenq_handler
3791 };
3792
3793 /*********************************************************************
3794  *  Multi-Process communication request handling (in primary)
3795  *********************************************************************/
3796 static int
3797 ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)
3798 {
3799         const struct ena_mp_body *req =
3800                 (const struct ena_mp_body *)mp_msg->param;
3801         struct ena_adapter *adapter;
3802         struct ena_com_dev *ena_dev;
3803         struct ena_mp_body *rsp;
3804         struct rte_mp_msg mp_rsp;
3805         struct rte_eth_dev *dev;
3806         int res = 0;
3807
3808         rsp = (struct ena_mp_body *)&mp_rsp.param;
3809         mp_msg_init(&mp_rsp, req->type, req->port_id);
3810
3811         if (!rte_eth_dev_is_valid_port(req->port_id)) {
3812                 rte_errno = ENODEV;
3813                 res = -rte_errno;
3814                 PMD_DRV_LOG(ERR, "Unknown port %d in request %d\n",
3815                             req->port_id, req->type);
3816                 goto end;
3817         }
3818         dev = &rte_eth_devices[req->port_id];
3819         adapter = dev->data->dev_private;
3820         ena_dev = &adapter->ena_dev;
3821
3822         switch (req->type) {
3823         case ENA_MP_DEV_STATS_GET:
3824                 res = ena_com_get_dev_basic_stats(ena_dev,
3825                                                   &adapter->basic_stats);
3826                 break;
3827         case ENA_MP_ENI_STATS_GET:
3828                 res = ena_com_get_eni_stats(ena_dev,
3829                         (struct ena_admin_eni_stats *)&adapter->eni_stats);
3830                 break;
3831         case ENA_MP_MTU_SET:
3832                 res = ena_com_set_dev_mtu(ena_dev, req->args.mtu);
3833                 break;
3834         case ENA_MP_IND_TBL_GET:
3835                 res = ena_com_indirect_table_get(ena_dev,
3836                                                  adapter->indirect_table);
3837                 break;
3838         case ENA_MP_IND_TBL_SET:
3839                 res = ena_com_indirect_table_set(ena_dev);
3840                 break;
3841         default:
3842                 PMD_DRV_LOG(ERR, "Unknown request type %d\n", req->type);
3843                 res = -EINVAL;
3844                 break;
3845         }
3846
3847 end:
3848         /* Save processing result in the reply */
3849         rsp->result = res;
3850         /* Return just IPC processing status */
3851         return rte_mp_reply(&mp_rsp, peer);
3852 }