4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 0
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 enum ethtool_stringset {
94 char name[ETH_GSTRING_LEN];
98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
100 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
103 #define ENA_STAT_ENTRY(stat, stat_type) { \
105 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
108 #define ENA_STAT_RX_ENTRY(stat) \
109 ENA_STAT_ENTRY(stat, rx)
111 #define ENA_STAT_TX_ENTRY(stat) \
112 ENA_STAT_ENTRY(stat, tx)
114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
115 ENA_STAT_ENTRY(stat, dev)
118 * Each rte_memzone should have unique name.
119 * To satisfy it, count number of allocation and add it to name.
121 uint32_t ena_alloc_cnt;
123 static const struct ena_stats ena_stats_global_strings[] = {
124 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
125 ENA_STAT_GLOBAL_ENTRY(io_suspend),
126 ENA_STAT_GLOBAL_ENTRY(io_resume),
127 ENA_STAT_GLOBAL_ENTRY(wd_expired),
128 ENA_STAT_GLOBAL_ENTRY(interface_up),
129 ENA_STAT_GLOBAL_ENTRY(interface_down),
130 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
133 static const struct ena_stats ena_stats_tx_strings[] = {
134 ENA_STAT_TX_ENTRY(cnt),
135 ENA_STAT_TX_ENTRY(bytes),
136 ENA_STAT_TX_ENTRY(queue_stop),
137 ENA_STAT_TX_ENTRY(queue_wakeup),
138 ENA_STAT_TX_ENTRY(dma_mapping_err),
139 ENA_STAT_TX_ENTRY(linearize),
140 ENA_STAT_TX_ENTRY(linearize_failed),
141 ENA_STAT_TX_ENTRY(tx_poll),
142 ENA_STAT_TX_ENTRY(doorbells),
143 ENA_STAT_TX_ENTRY(prepare_ctx_err),
144 ENA_STAT_TX_ENTRY(missing_tx_comp),
145 ENA_STAT_TX_ENTRY(bad_req_id),
148 static const struct ena_stats ena_stats_rx_strings[] = {
149 ENA_STAT_RX_ENTRY(cnt),
150 ENA_STAT_RX_ENTRY(bytes),
151 ENA_STAT_RX_ENTRY(refil_partial),
152 ENA_STAT_RX_ENTRY(bad_csum),
153 ENA_STAT_RX_ENTRY(page_alloc_fail),
154 ENA_STAT_RX_ENTRY(skb_alloc_fail),
155 ENA_STAT_RX_ENTRY(dma_mapping_err),
156 ENA_STAT_RX_ENTRY(bad_desc_num),
157 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
160 static const struct ena_stats ena_stats_ena_com_strings[] = {
161 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
162 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
163 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
164 ENA_STAT_ENA_COM_ENTRY(out_of_space),
165 ENA_STAT_ENA_COM_ENTRY(no_completion),
168 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
169 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
170 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
174 DEV_TX_OFFLOAD_UDP_CKSUM |\
175 DEV_TX_OFFLOAD_IPV4_CKSUM |\
176 DEV_TX_OFFLOAD_TCP_TSO)
177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
181 /** Vendor ID used by Amazon devices */
182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
183 /** Amazon devices */
184 #define PCI_DEVICE_ID_ENA_VF 0xEC20
185 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
187 #define ENA_TX_OFFLOAD_MASK (\
192 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
193 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
195 int ena_logtype_init;
196 int ena_logtype_driver;
198 static const struct rte_pci_id pci_id_ena_map[] = {
199 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
200 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
204 static struct ena_aenq_handlers aenq_handlers;
206 static int ena_device_init(struct ena_com_dev *ena_dev,
207 struct ena_com_dev_get_features_ctx *get_feat_ctx,
209 static int ena_dev_configure(struct rte_eth_dev *dev);
210 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
212 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
214 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
215 uint16_t nb_desc, unsigned int socket_id,
216 const struct rte_eth_txconf *tx_conf);
217 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
218 uint16_t nb_desc, unsigned int socket_id,
219 const struct rte_eth_rxconf *rx_conf,
220 struct rte_mempool *mp);
221 static uint16_t eth_ena_recv_pkts(void *rx_queue,
222 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
223 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
224 static void ena_init_rings(struct ena_adapter *adapter);
225 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
226 static int ena_start(struct rte_eth_dev *dev);
227 static void ena_stop(struct rte_eth_dev *dev);
228 static void ena_close(struct rte_eth_dev *dev);
229 static int ena_dev_reset(struct rte_eth_dev *dev);
230 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
231 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
232 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
233 static void ena_rx_queue_release(void *queue);
234 static void ena_tx_queue_release(void *queue);
235 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
236 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
237 static int ena_link_update(struct rte_eth_dev *dev,
238 int wait_to_complete);
239 static int ena_queue_restart(struct ena_ring *ring);
240 static int ena_queue_restart_all(struct rte_eth_dev *dev,
241 enum ena_ring_type ring_type);
242 static void ena_stats_restart(struct rte_eth_dev *dev);
243 static void ena_infos_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int ena_rss_reta_update(struct rte_eth_dev *dev,
246 struct rte_eth_rss_reta_entry64 *reta_conf,
248 static int ena_rss_reta_query(struct rte_eth_dev *dev,
249 struct rte_eth_rss_reta_entry64 *reta_conf,
251 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
252 static void ena_interrupt_handler_rte(void *cb_arg);
253 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
255 static const struct eth_dev_ops ena_dev_ops = {
256 .dev_configure = ena_dev_configure,
257 .dev_infos_get = ena_infos_get,
258 .rx_queue_setup = ena_rx_queue_setup,
259 .tx_queue_setup = ena_tx_queue_setup,
260 .dev_start = ena_start,
261 .dev_stop = ena_stop,
262 .link_update = ena_link_update,
263 .stats_get = ena_stats_get,
264 .mtu_set = ena_mtu_set,
265 .rx_queue_release = ena_rx_queue_release,
266 .tx_queue_release = ena_tx_queue_release,
267 .dev_close = ena_close,
268 .dev_reset = ena_dev_reset,
269 .reta_update = ena_rss_reta_update,
270 .reta_query = ena_rss_reta_query,
273 #define NUMA_NO_NODE SOCKET_ID_ANY
275 static inline int ena_cpu_to_node(int cpu)
277 struct rte_config *config = rte_eal_get_configuration();
278 struct rte_fbarray *arr = &config->mem_config->memzones;
279 const struct rte_memzone *mz;
281 if (unlikely(cpu >= RTE_MAX_MEMZONE))
284 mz = rte_fbarray_get(arr, cpu);
286 return mz->socket_id;
289 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
290 struct ena_com_rx_ctx *ena_rx_ctx)
292 uint64_t ol_flags = 0;
293 uint32_t packet_type = 0;
295 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
296 packet_type |= RTE_PTYPE_L4_TCP;
297 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
298 packet_type |= RTE_PTYPE_L4_UDP;
300 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
301 packet_type |= RTE_PTYPE_L3_IPV4;
302 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
303 packet_type |= RTE_PTYPE_L3_IPV6;
305 if (unlikely(ena_rx_ctx->l4_csum_err))
306 ol_flags |= PKT_RX_L4_CKSUM_BAD;
307 if (unlikely(ena_rx_ctx->l3_csum_err))
308 ol_flags |= PKT_RX_IP_CKSUM_BAD;
310 mbuf->ol_flags = ol_flags;
311 mbuf->packet_type = packet_type;
314 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
315 struct ena_com_tx_ctx *ena_tx_ctx,
316 uint64_t queue_offloads)
318 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
320 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
321 (queue_offloads & QUEUE_OFFLOADS)) {
322 /* check if TSO is required */
323 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
324 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
325 ena_tx_ctx->tso_enable = true;
327 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
330 /* check if L3 checksum is needed */
331 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
332 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
333 ena_tx_ctx->l3_csum_enable = true;
335 if (mbuf->ol_flags & PKT_TX_IPV6) {
336 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
338 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
340 /* set don't fragment (DF) flag */
341 if (mbuf->packet_type &
342 (RTE_PTYPE_L4_NONFRAG
343 | RTE_PTYPE_INNER_L4_NONFRAG))
344 ena_tx_ctx->df = true;
347 /* check if L4 checksum is needed */
348 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
349 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
350 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
351 ena_tx_ctx->l4_csum_enable = true;
352 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
353 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
354 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
355 ena_tx_ctx->l4_csum_enable = true;
357 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
358 ena_tx_ctx->l4_csum_enable = false;
361 ena_meta->mss = mbuf->tso_segsz;
362 ena_meta->l3_hdr_len = mbuf->l3_len;
363 ena_meta->l3_hdr_offset = mbuf->l2_len;
365 ena_tx_ctx->meta_valid = true;
367 ena_tx_ctx->meta_valid = false;
371 static void ena_config_host_info(struct ena_com_dev *ena_dev)
373 struct ena_admin_host_info *host_info;
376 /* Allocate only the host info */
377 rc = ena_com_allocate_host_info(ena_dev);
379 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
383 host_info = ena_dev->host_attr.host_info;
385 host_info->os_type = ENA_ADMIN_OS_DPDK;
386 host_info->kernel_ver = RTE_VERSION;
387 snprintf((char *)host_info->kernel_ver_str,
388 sizeof(host_info->kernel_ver_str),
389 "%s", rte_version());
390 host_info->os_dist = RTE_VERSION;
391 snprintf((char *)host_info->os_dist_str,
392 sizeof(host_info->os_dist_str),
393 "%s", rte_version());
394 host_info->driver_version =
395 (DRV_MODULE_VER_MAJOR) |
396 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
397 (DRV_MODULE_VER_SUBMINOR <<
398 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
400 rc = ena_com_set_host_attributes(ena_dev);
402 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
403 if (rc != -ENA_COM_UNSUPPORTED)
410 ena_com_delete_host_info(ena_dev);
414 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
416 if (sset != ETH_SS_STATS)
419 /* Workaround for clang:
420 * touch internal structures to prevent
423 ENA_TOUCH(ena_stats_global_strings);
424 ENA_TOUCH(ena_stats_tx_strings);
425 ENA_TOUCH(ena_stats_rx_strings);
426 ENA_TOUCH(ena_stats_ena_com_strings);
428 return dev->data->nb_tx_queues *
429 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
430 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
433 static void ena_config_debug_area(struct ena_adapter *adapter)
438 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
440 RTE_LOG(ERR, PMD, "SS count is negative\n");
444 /* allocate 32 bytes for each string and 64bit for the value */
445 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
447 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
449 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
453 rc = ena_com_set_host_attributes(&adapter->ena_dev);
455 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
456 if (rc != -ENA_COM_UNSUPPORTED)
462 ena_com_delete_debug_area(&adapter->ena_dev);
465 static void ena_close(struct rte_eth_dev *dev)
467 struct ena_adapter *adapter =
468 (struct ena_adapter *)(dev->data->dev_private);
471 adapter->state = ENA_ADAPTER_STATE_CLOSED;
473 ena_rx_queue_release_all(dev);
474 ena_tx_queue_release_all(dev);
478 ena_dev_reset(struct rte_eth_dev *dev)
480 struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
481 struct rte_eth_dev *eth_dev;
482 struct rte_pci_device *pci_dev;
483 struct rte_intr_handle *intr_handle;
484 struct ena_com_dev *ena_dev;
485 struct ena_com_dev_get_features_ctx get_feat_ctx;
486 struct ena_adapter *adapter;
491 adapter = (struct ena_adapter *)(dev->data->dev_private);
492 ena_dev = &adapter->ena_dev;
493 eth_dev = adapter->rte_dev;
494 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
495 intr_handle = &pci_dev->intr_handle;
496 nb_queues = eth_dev->data->nb_rx_queues;
498 ena_com_set_admin_running_state(ena_dev, false);
500 ena_com_dev_reset(ena_dev, adapter->reset_reason);
502 for (i = 0; i < nb_queues; i++)
503 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
505 ena_rx_queue_release_all(eth_dev);
506 ena_tx_queue_release_all(eth_dev);
508 rte_intr_disable(intr_handle);
510 ena_com_abort_admin_commands(ena_dev);
511 ena_com_wait_for_abort_completion(ena_dev);
512 ena_com_admin_destroy(ena_dev);
513 ena_com_mmio_reg_read_request_destroy(ena_dev);
515 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
517 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
520 adapter->wd_state = wd_state;
522 rte_intr_enable(intr_handle);
523 ena_com_set_admin_polling_mode(ena_dev, false);
524 ena_com_admin_aenq_enable(ena_dev);
526 for (i = 0; i < nb_queues; ++i)
527 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
530 for (i = 0; i < nb_queues; ++i)
531 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
533 adapter->trigger_reset = false;
538 static int ena_rss_reta_update(struct rte_eth_dev *dev,
539 struct rte_eth_rss_reta_entry64 *reta_conf,
542 struct ena_adapter *adapter =
543 (struct ena_adapter *)(dev->data->dev_private);
544 struct ena_com_dev *ena_dev = &adapter->ena_dev;
550 if ((reta_size == 0) || (reta_conf == NULL))
553 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
554 RTE_LOG(WARNING, PMD,
555 "indirection table %d is bigger than supported (%d)\n",
556 reta_size, ENA_RX_RSS_TABLE_SIZE);
561 for (i = 0 ; i < reta_size ; i++) {
562 /* each reta_conf is for 64 entries.
563 * to support 128 we use 2 conf of 64
565 conf_idx = i / RTE_RETA_GROUP_SIZE;
566 idx = i % RTE_RETA_GROUP_SIZE;
567 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
569 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
570 ret = ena_com_indirect_table_fill_entry(ena_dev,
573 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
575 "Cannot fill indirect table\n");
582 ret = ena_com_indirect_table_set(ena_dev);
583 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
584 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
589 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
590 __func__, reta_size, adapter->rte_dev->data->port_id);
595 /* Query redirection table. */
596 static int ena_rss_reta_query(struct rte_eth_dev *dev,
597 struct rte_eth_rss_reta_entry64 *reta_conf,
600 struct ena_adapter *adapter =
601 (struct ena_adapter *)(dev->data->dev_private);
602 struct ena_com_dev *ena_dev = &adapter->ena_dev;
605 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
609 if (reta_size == 0 || reta_conf == NULL ||
610 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
613 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
614 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
615 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
620 for (i = 0 ; i < reta_size ; i++) {
621 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
622 reta_idx = i % RTE_RETA_GROUP_SIZE;
623 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
624 reta_conf[reta_conf_idx].reta[reta_idx] =
625 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
631 static int ena_rss_init_default(struct ena_adapter *adapter)
633 struct ena_com_dev *ena_dev = &adapter->ena_dev;
634 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
638 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
640 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
644 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
645 val = i % nb_rx_queues;
646 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
647 ENA_IO_RXQ_IDX(val));
648 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
649 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
654 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
655 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
656 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
657 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
661 rc = ena_com_set_default_hash_ctrl(ena_dev);
662 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
663 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
667 rc = ena_com_indirect_table_set(ena_dev);
668 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
669 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
672 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
673 adapter->rte_dev->data->port_id);
678 ena_com_rss_destroy(ena_dev);
684 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
686 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
687 int nb_queues = dev->data->nb_rx_queues;
690 for (i = 0; i < nb_queues; i++)
691 ena_rx_queue_release(queues[i]);
694 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
696 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
697 int nb_queues = dev->data->nb_tx_queues;
700 for (i = 0; i < nb_queues; i++)
701 ena_tx_queue_release(queues[i]);
704 static void ena_rx_queue_release(void *queue)
706 struct ena_ring *ring = (struct ena_ring *)queue;
707 struct ena_adapter *adapter = ring->adapter;
710 ena_assert_msg(ring->configured,
711 "API violation - releasing not configured queue");
712 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
715 /* Destroy HW queue */
716 ena_qid = ENA_IO_RXQ_IDX(ring->id);
717 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
720 ena_rx_queue_release_bufs(ring);
722 /* Free ring resources */
723 if (ring->rx_buffer_info)
724 rte_free(ring->rx_buffer_info);
725 ring->rx_buffer_info = NULL;
727 ring->configured = 0;
729 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
730 ring->port_id, ring->id);
733 static void ena_tx_queue_release(void *queue)
735 struct ena_ring *ring = (struct ena_ring *)queue;
736 struct ena_adapter *adapter = ring->adapter;
739 ena_assert_msg(ring->configured,
740 "API violation. Releasing not configured queue");
741 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
744 /* Destroy HW queue */
745 ena_qid = ENA_IO_TXQ_IDX(ring->id);
746 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
749 ena_tx_queue_release_bufs(ring);
751 /* Free ring resources */
752 if (ring->tx_buffer_info)
753 rte_free(ring->tx_buffer_info);
755 if (ring->empty_tx_reqs)
756 rte_free(ring->empty_tx_reqs);
758 ring->empty_tx_reqs = NULL;
759 ring->tx_buffer_info = NULL;
761 ring->configured = 0;
763 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
764 ring->port_id, ring->id);
767 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
769 unsigned int ring_mask = ring->ring_size - 1;
771 while (ring->next_to_clean != ring->next_to_use) {
773 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
776 rte_mbuf_raw_free(m);
778 ring->next_to_clean++;
782 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
786 for (i = 0; i < ring->ring_size; ++i) {
787 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
790 rte_pktmbuf_free(tx_buf->mbuf);
792 ring->next_to_clean++;
796 static int ena_link_update(struct rte_eth_dev *dev,
797 __rte_unused int wait_to_complete)
799 struct rte_eth_link *link = &dev->data->dev_link;
800 struct ena_adapter *adapter;
802 adapter = (struct ena_adapter *)(dev->data->dev_private);
804 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
805 link->link_speed = ETH_SPEED_NUM_10G;
806 link->link_duplex = ETH_LINK_FULL_DUPLEX;
811 static int ena_queue_restart_all(struct rte_eth_dev *dev,
812 enum ena_ring_type ring_type)
814 struct ena_adapter *adapter =
815 (struct ena_adapter *)(dev->data->dev_private);
816 struct ena_ring *queues = NULL;
821 if (ring_type == ENA_RING_TYPE_RX) {
822 queues = adapter->rx_ring;
823 nb_queues = dev->data->nb_rx_queues;
825 queues = adapter->tx_ring;
826 nb_queues = dev->data->nb_tx_queues;
828 for (i = 0; i < nb_queues; i++) {
829 if (queues[i].configured) {
830 if (ring_type == ENA_RING_TYPE_RX) {
832 dev->data->rx_queues[i] == &queues[i],
833 "Inconsistent state of rx queues\n");
836 dev->data->tx_queues[i] == &queues[i],
837 "Inconsistent state of tx queues\n");
840 rc = ena_queue_restart(&queues[i]);
844 "failed to restart queue %d type(%d)",
854 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
856 uint32_t max_frame_len = adapter->max_mtu;
858 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
859 DEV_RX_OFFLOAD_JUMBO_FRAME)
861 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
863 return max_frame_len;
866 static int ena_check_valid_conf(struct ena_adapter *adapter)
868 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
870 if (max_frame_len > adapter->max_mtu) {
871 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
879 ena_calc_queue_size(struct ena_com_dev *ena_dev,
880 struct ena_com_dev_get_features_ctx *get_feat_ctx)
882 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
884 queue_size = RTE_MIN(queue_size,
885 get_feat_ctx->max_queues.max_cq_depth);
886 queue_size = RTE_MIN(queue_size,
887 get_feat_ctx->max_queues.max_sq_depth);
889 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
890 queue_size = RTE_MIN(queue_size,
891 get_feat_ctx->max_queues.max_llq_depth);
893 /* Round down to power of 2 */
894 if (!rte_is_power_of_2(queue_size))
895 queue_size = rte_align32pow2(queue_size >> 1);
897 if (queue_size == 0) {
898 PMD_INIT_LOG(ERR, "Invalid queue size");
905 static void ena_stats_restart(struct rte_eth_dev *dev)
907 struct ena_adapter *adapter =
908 (struct ena_adapter *)(dev->data->dev_private);
910 rte_atomic64_init(&adapter->drv_stats->ierrors);
911 rte_atomic64_init(&adapter->drv_stats->oerrors);
912 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
915 static int ena_stats_get(struct rte_eth_dev *dev,
916 struct rte_eth_stats *stats)
918 struct ena_admin_basic_stats ena_stats;
919 struct ena_adapter *adapter =
920 (struct ena_adapter *)(dev->data->dev_private);
921 struct ena_com_dev *ena_dev = &adapter->ena_dev;
924 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
927 memset(&ena_stats, 0, sizeof(ena_stats));
928 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
930 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
934 /* Set of basic statistics from ENA */
935 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
936 ena_stats.rx_pkts_low);
937 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
938 ena_stats.tx_pkts_low);
939 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
940 ena_stats.rx_bytes_low);
941 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
942 ena_stats.tx_bytes_low);
943 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
944 ena_stats.rx_drops_low);
946 /* Driver related stats */
947 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
948 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
949 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
953 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
955 struct ena_adapter *adapter;
956 struct ena_com_dev *ena_dev;
959 ena_assert_msg(dev->data != NULL, "Uninitialized device");
960 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
961 adapter = (struct ena_adapter *)(dev->data->dev_private);
963 ena_dev = &adapter->ena_dev;
964 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
966 if (mtu > ena_get_mtu_conf(adapter)) {
968 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
969 mtu, ena_get_mtu_conf(adapter));
974 rc = ena_com_set_dev_mtu(ena_dev, mtu);
976 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
978 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
984 static int ena_start(struct rte_eth_dev *dev)
986 struct ena_adapter *adapter =
987 (struct ena_adapter *)(dev->data->dev_private);
991 rc = ena_check_valid_conf(adapter);
995 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
999 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1003 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1004 ETH_MQ_RX_RSS_FLAG) {
1005 rc = ena_rss_init_default(adapter);
1010 ena_stats_restart(dev);
1012 adapter->timestamp_wd = rte_get_timer_cycles();
1013 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1015 ticks = rte_get_timer_hz();
1016 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1017 ena_timer_wd_callback, adapter);
1019 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1024 static void ena_stop(struct rte_eth_dev *dev)
1026 struct ena_adapter *adapter =
1027 (struct ena_adapter *)(dev->data->dev_private);
1029 rte_timer_stop_sync(&adapter->timer_wd);
1031 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1034 static int ena_queue_restart(struct ena_ring *ring)
1038 ena_assert_msg(ring->configured == 1,
1039 "Trying to restart unconfigured queue\n");
1041 ring->next_to_clean = 0;
1042 ring->next_to_use = 0;
1044 if (ring->type == ENA_RING_TYPE_TX)
1047 bufs_num = ring->ring_size - 1;
1048 rc = ena_populate_rx_queue(ring, bufs_num);
1049 if (rc != bufs_num) {
1050 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1057 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1060 __rte_unused unsigned int socket_id,
1061 const struct rte_eth_txconf *tx_conf)
1063 struct ena_com_create_io_ctx ctx =
1064 /* policy set to _HOST just to satisfy icc compiler */
1065 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1066 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1067 struct ena_ring *txq = NULL;
1068 struct ena_adapter *adapter =
1069 (struct ena_adapter *)(dev->data->dev_private);
1073 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1075 txq = &adapter->tx_ring[queue_idx];
1077 if (txq->configured) {
1079 "API violation. Queue %d is already configured\n",
1084 if (!rte_is_power_of_2(nb_desc)) {
1086 "Unsupported size of RX queue: %d is not a power of 2.",
1091 if (nb_desc > adapter->tx_ring_size) {
1093 "Unsupported size of TX queue (max size: %d)\n",
1094 adapter->tx_ring_size);
1098 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1100 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1102 ctx.msix_vector = -1; /* admin interrupts not used */
1103 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1104 ctx.queue_size = adapter->tx_ring_size;
1105 ctx.numa_node = ena_cpu_to_node(queue_idx);
1107 rc = ena_com_create_io_queue(ena_dev, &ctx);
1110 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1111 queue_idx, ena_qid, rc);
1113 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1114 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1116 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1117 &txq->ena_com_io_sq,
1118 &txq->ena_com_io_cq);
1121 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1123 ena_com_destroy_io_queue(ena_dev, ena_qid);
1127 txq->port_id = dev->data->port_id;
1128 txq->next_to_clean = 0;
1129 txq->next_to_use = 0;
1130 txq->ring_size = nb_desc;
1132 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1133 sizeof(struct ena_tx_buffer) *
1135 RTE_CACHE_LINE_SIZE);
1136 if (!txq->tx_buffer_info) {
1137 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1141 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1142 sizeof(u16) * txq->ring_size,
1143 RTE_CACHE_LINE_SIZE);
1144 if (!txq->empty_tx_reqs) {
1145 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1146 rte_free(txq->tx_buffer_info);
1149 for (i = 0; i < txq->ring_size; i++)
1150 txq->empty_tx_reqs[i] = i;
1152 if (tx_conf != NULL) {
1154 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1157 /* Store pointer to this queue in upper layer */
1158 txq->configured = 1;
1159 dev->data->tx_queues[queue_idx] = txq;
1164 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1167 __rte_unused unsigned int socket_id,
1168 __rte_unused const struct rte_eth_rxconf *rx_conf,
1169 struct rte_mempool *mp)
1171 struct ena_com_create_io_ctx ctx =
1172 /* policy set to _HOST just to satisfy icc compiler */
1173 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1174 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1175 struct ena_adapter *adapter =
1176 (struct ena_adapter *)(dev->data->dev_private);
1177 struct ena_ring *rxq = NULL;
1178 uint16_t ena_qid = 0;
1180 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1182 rxq = &adapter->rx_ring[queue_idx];
1183 if (rxq->configured) {
1185 "API violation. Queue %d is already configured\n",
1190 if (!rte_is_power_of_2(nb_desc)) {
1192 "Unsupported size of TX queue: %d is not a power of 2.",
1197 if (nb_desc > adapter->rx_ring_size) {
1199 "Unsupported size of RX queue (max size: %d)\n",
1200 adapter->rx_ring_size);
1204 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1207 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1208 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1209 ctx.msix_vector = -1; /* admin interrupts not used */
1210 ctx.queue_size = adapter->rx_ring_size;
1211 ctx.numa_node = ena_cpu_to_node(queue_idx);
1213 rc = ena_com_create_io_queue(ena_dev, &ctx);
1215 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1218 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1219 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1221 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1222 &rxq->ena_com_io_sq,
1223 &rxq->ena_com_io_cq);
1226 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1228 ena_com_destroy_io_queue(ena_dev, ena_qid);
1231 rxq->port_id = dev->data->port_id;
1232 rxq->next_to_clean = 0;
1233 rxq->next_to_use = 0;
1234 rxq->ring_size = nb_desc;
1237 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1238 sizeof(struct rte_mbuf *) * nb_desc,
1239 RTE_CACHE_LINE_SIZE);
1240 if (!rxq->rx_buffer_info) {
1241 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1245 /* Store pointer to this queue in upper layer */
1246 rxq->configured = 1;
1247 dev->data->rx_queues[queue_idx] = rxq;
1252 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1256 uint16_t ring_size = rxq->ring_size;
1257 uint16_t ring_mask = ring_size - 1;
1258 uint16_t next_to_use = rxq->next_to_use;
1260 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1262 if (unlikely(!count))
1265 in_use = rxq->next_to_use - rxq->next_to_clean;
1266 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1268 count = RTE_MIN(count,
1269 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1271 /* get resources for incoming packets */
1272 rc = rte_mempool_get_bulk(rxq->mb_pool,
1273 (void **)(&mbufs[next_to_use & ring_mask]),
1275 if (unlikely(rc < 0)) {
1276 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1277 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1281 for (i = 0; i < count; i++) {
1282 uint16_t next_to_use_masked = next_to_use & ring_mask;
1283 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1284 struct ena_com_buf ebuf;
1286 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1287 /* prepare physical address for DMA transaction */
1288 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1289 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1290 /* pass resource to device */
1291 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1292 &ebuf, next_to_use_masked);
1294 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1296 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1302 /* When we submitted free recources to device... */
1304 /* ...let HW know that it can fill buffers with data */
1306 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1308 rxq->next_to_use = next_to_use;
1314 static int ena_device_init(struct ena_com_dev *ena_dev,
1315 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1318 uint32_t aenq_groups;
1320 bool readless_supported;
1322 /* Initialize mmio registers */
1323 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1325 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1329 /* The PCIe configuration space revision id indicate if mmio reg
1332 readless_supported =
1333 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1334 & ENA_MMIO_DISABLE_REG_READ);
1335 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1338 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1340 RTE_LOG(ERR, PMD, "cannot reset device\n");
1341 goto err_mmio_read_less;
1344 /* check FW version */
1345 rc = ena_com_validate_version(ena_dev);
1347 RTE_LOG(ERR, PMD, "device version is too low\n");
1348 goto err_mmio_read_less;
1351 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1353 /* ENA device administration layer init */
1354 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1357 "cannot initialize ena admin queue with device\n");
1358 goto err_mmio_read_less;
1361 /* To enable the msix interrupts the driver needs to know the number
1362 * of queues. So the driver uses polling mode to retrieve this
1365 ena_com_set_admin_polling_mode(ena_dev, true);
1367 ena_config_host_info(ena_dev);
1369 /* Get Device Attributes and features */
1370 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1373 "cannot get attribute for ena device rc= %d\n", rc);
1374 goto err_admin_init;
1377 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1378 BIT(ENA_ADMIN_NOTIFICATION) |
1379 BIT(ENA_ADMIN_KEEP_ALIVE);
1381 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1382 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1384 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1385 goto err_admin_init;
1388 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1393 ena_com_admin_destroy(ena_dev);
1396 ena_com_mmio_reg_read_request_destroy(ena_dev);
1401 static void ena_interrupt_handler_rte(void *cb_arg)
1403 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1404 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1406 ena_com_admin_q_comp_intr_handler(ena_dev);
1407 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1408 ena_com_aenq_intr_handler(ena_dev, adapter);
1411 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1413 if (!adapter->wd_state)
1416 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1419 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1420 adapter->keep_alive_timeout)) {
1421 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1422 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1423 adapter->trigger_reset = true;
1427 /* Check if admin queue is enabled */
1428 static void check_for_admin_com_state(struct ena_adapter *adapter)
1430 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1431 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1432 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1433 adapter->trigger_reset = true;
1437 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1440 struct ena_adapter *adapter = (struct ena_adapter *)arg;
1441 struct rte_eth_dev *dev = adapter->rte_dev;
1443 check_for_missing_keep_alive(adapter);
1444 check_for_admin_com_state(adapter);
1446 if (unlikely(adapter->trigger_reset)) {
1447 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1448 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1453 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1455 struct rte_pci_device *pci_dev;
1456 struct rte_intr_handle *intr_handle;
1457 struct ena_adapter *adapter =
1458 (struct ena_adapter *)(eth_dev->data->dev_private);
1459 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1460 struct ena_com_dev_get_features_ctx get_feat_ctx;
1463 static int adapters_found;
1466 memset(adapter, 0, sizeof(struct ena_adapter));
1467 ena_dev = &adapter->ena_dev;
1469 eth_dev->dev_ops = &ena_dev_ops;
1470 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1471 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1472 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1473 adapter->rte_eth_dev_data = eth_dev->data;
1474 adapter->rte_dev = eth_dev;
1476 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1479 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1480 adapter->pdev = pci_dev;
1482 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1483 pci_dev->addr.domain,
1485 pci_dev->addr.devid,
1486 pci_dev->addr.function);
1488 intr_handle = &pci_dev->intr_handle;
1490 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1491 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1493 if (!adapter->regs) {
1494 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1499 ena_dev->reg_bar = adapter->regs;
1500 ena_dev->dmadev = adapter->pdev;
1502 adapter->id_number = adapters_found;
1504 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1505 adapter->id_number);
1507 /* device specific initialization routine */
1508 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1510 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1513 adapter->wd_state = wd_state;
1515 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1516 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1518 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1519 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1522 adapter->tx_ring_size = queue_size;
1523 adapter->rx_ring_size = queue_size;
1525 /* prepare ring structures */
1526 ena_init_rings(adapter);
1528 ena_config_debug_area(adapter);
1530 /* Set max MTU for this device */
1531 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1533 /* set device support for TSO */
1534 adapter->tso4_supported = get_feat_ctx.offload.tx &
1535 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1537 /* Copy MAC address and point DPDK to it */
1538 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1539 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1540 (struct ether_addr *)adapter->mac_addr);
1542 adapter->drv_stats = rte_zmalloc("adapter stats",
1543 sizeof(*adapter->drv_stats),
1544 RTE_CACHE_LINE_SIZE);
1545 if (!adapter->drv_stats) {
1546 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1550 rte_intr_callback_register(intr_handle,
1551 ena_interrupt_handler_rte,
1553 rte_intr_enable(intr_handle);
1554 ena_com_set_admin_polling_mode(ena_dev, false);
1555 ena_com_admin_aenq_enable(ena_dev);
1557 if (adapters_found == 0)
1558 rte_timer_subsystem_init();
1559 rte_timer_init(&adapter->timer_wd);
1562 adapter->state = ENA_ADAPTER_STATE_INIT;
1567 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1569 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1570 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1571 struct ena_adapter *adapter =
1572 (struct ena_adapter *)(eth_dev->data->dev_private);
1574 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1577 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1580 eth_dev->dev_ops = NULL;
1581 eth_dev->rx_pkt_burst = NULL;
1582 eth_dev->tx_pkt_burst = NULL;
1583 eth_dev->tx_pkt_prepare = NULL;
1585 rte_free(adapter->drv_stats);
1586 adapter->drv_stats = NULL;
1588 rte_intr_disable(intr_handle);
1589 rte_intr_callback_unregister(intr_handle,
1590 ena_interrupt_handler_rte,
1593 adapter->state = ENA_ADAPTER_STATE_FREE;
1598 static int ena_dev_configure(struct rte_eth_dev *dev)
1600 struct ena_adapter *adapter =
1601 (struct ena_adapter *)(dev->data->dev_private);
1603 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1605 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1606 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1610 static void ena_init_rings(struct ena_adapter *adapter)
1614 for (i = 0; i < adapter->num_queues; i++) {
1615 struct ena_ring *ring = &adapter->tx_ring[i];
1617 ring->configured = 0;
1618 ring->type = ENA_RING_TYPE_TX;
1619 ring->adapter = adapter;
1621 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1622 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1625 for (i = 0; i < adapter->num_queues; i++) {
1626 struct ena_ring *ring = &adapter->rx_ring[i];
1628 ring->configured = 0;
1629 ring->type = ENA_RING_TYPE_RX;
1630 ring->adapter = adapter;
1635 static void ena_infos_get(struct rte_eth_dev *dev,
1636 struct rte_eth_dev_info *dev_info)
1638 struct ena_adapter *adapter;
1639 struct ena_com_dev *ena_dev;
1640 struct ena_com_dev_get_features_ctx feat;
1641 uint64_t rx_feat = 0, tx_feat = 0;
1644 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1645 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1646 adapter = (struct ena_adapter *)(dev->data->dev_private);
1648 ena_dev = &adapter->ena_dev;
1649 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1651 dev_info->speed_capa =
1653 ETH_LINK_SPEED_2_5G |
1655 ETH_LINK_SPEED_10G |
1656 ETH_LINK_SPEED_25G |
1657 ETH_LINK_SPEED_40G |
1658 ETH_LINK_SPEED_50G |
1659 ETH_LINK_SPEED_100G;
1661 /* Get supported features from HW */
1662 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1665 "Cannot get attribute for ena device rc= %d\n", rc);
1669 /* Set Tx & Rx features available for device */
1670 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1671 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1673 if (feat.offload.tx &
1674 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1675 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1676 DEV_TX_OFFLOAD_UDP_CKSUM |
1677 DEV_TX_OFFLOAD_TCP_CKSUM;
1679 if (feat.offload.rx_supported &
1680 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1681 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1682 DEV_RX_OFFLOAD_UDP_CKSUM |
1683 DEV_RX_OFFLOAD_TCP_CKSUM;
1685 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1687 /* Inform framework about available features */
1688 dev_info->rx_offload_capa = rx_feat;
1689 dev_info->rx_queue_offload_capa = rx_feat;
1690 dev_info->tx_offload_capa = tx_feat;
1691 dev_info->tx_queue_offload_capa = tx_feat;
1693 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1694 dev_info->max_rx_pktlen = adapter->max_mtu;
1695 dev_info->max_mac_addrs = 1;
1697 dev_info->max_rx_queues = adapter->num_queues;
1698 dev_info->max_tx_queues = adapter->num_queues;
1699 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1701 adapter->tx_supported_offloads = tx_feat;
1702 adapter->rx_supported_offloads = rx_feat;
1705 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1708 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1709 unsigned int ring_size = rx_ring->ring_size;
1710 unsigned int ring_mask = ring_size - 1;
1711 uint16_t next_to_clean = rx_ring->next_to_clean;
1712 uint16_t desc_in_use = 0;
1713 unsigned int recv_idx = 0;
1714 struct rte_mbuf *mbuf = NULL;
1715 struct rte_mbuf *mbuf_head = NULL;
1716 struct rte_mbuf *mbuf_prev = NULL;
1717 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1718 unsigned int completed;
1720 struct ena_com_rx_ctx ena_rx_ctx;
1723 /* Check adapter state */
1724 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1726 "Trying to receive pkts while device is NOT running\n");
1730 desc_in_use = rx_ring->next_to_use - next_to_clean;
1731 if (unlikely(nb_pkts > desc_in_use))
1732 nb_pkts = desc_in_use;
1734 for (completed = 0; completed < nb_pkts; completed++) {
1737 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1738 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1739 ena_rx_ctx.descs = 0;
1740 /* receive packet context */
1741 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1742 rx_ring->ena_com_io_sq,
1745 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1749 if (unlikely(ena_rx_ctx.descs == 0))
1752 while (segments < ena_rx_ctx.descs) {
1753 mbuf = rx_buff_info[next_to_clean & ring_mask];
1754 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1755 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1758 if (segments == 0) {
1759 mbuf->nb_segs = ena_rx_ctx.descs;
1760 mbuf->port = rx_ring->port_id;
1764 /* for multi-segment pkts create mbuf chain */
1765 mbuf_prev->next = mbuf;
1767 mbuf_head->pkt_len += mbuf->data_len;
1774 /* fill mbuf attributes if any */
1775 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1776 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1778 /* pass to DPDK application head mbuf */
1779 rx_pkts[recv_idx] = mbuf_head;
1783 rx_ring->next_to_clean = next_to_clean;
1785 desc_in_use = desc_in_use - completed + 1;
1786 /* Burst refill to save doorbells, memory barriers, const interval */
1787 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1788 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1794 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1800 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1801 struct ipv4_hdr *ip_hdr;
1803 uint16_t frag_field;
1805 for (i = 0; i != nb_pkts; i++) {
1807 ol_flags = m->ol_flags;
1809 if (!(ol_flags & PKT_TX_IPV4))
1812 /* If there was not L2 header length specified, assume it is
1813 * length of the ethernet header.
1815 if (unlikely(m->l2_len == 0))
1816 m->l2_len = sizeof(struct ether_hdr);
1818 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1820 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1822 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1823 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1825 /* If IPv4 header has DF flag enabled and TSO support is
1826 * disabled, partial chcecksum should not be calculated.
1828 if (!tx_ring->adapter->tso4_supported)
1832 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1833 (ol_flags & PKT_TX_L4_MASK) ==
1834 PKT_TX_SCTP_CKSUM) {
1835 rte_errno = -ENOTSUP;
1839 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1840 ret = rte_validate_tx_offload(m);
1847 /* In case we are supposed to TSO and have DF not set (DF=0)
1848 * hardware must be provided with partial checksum, otherwise
1849 * it will take care of necessary calculations.
1852 ret = rte_net_intel_cksum_flags_prepare(m,
1853 ol_flags & ~PKT_TX_TCP_SEG);
1863 static void ena_update_hints(struct ena_adapter *adapter,
1864 struct ena_admin_ena_hw_hints *hints)
1866 if (hints->admin_completion_tx_timeout)
1867 adapter->ena_dev.admin_queue.completion_timeout =
1868 hints->admin_completion_tx_timeout * 1000;
1870 if (hints->mmio_read_timeout)
1871 /* convert to usec */
1872 adapter->ena_dev.mmio_read.reg_read_to =
1873 hints->mmio_read_timeout * 1000;
1875 if (hints->driver_watchdog_timeout) {
1876 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1877 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1879 // Convert msecs to ticks
1880 adapter->keep_alive_timeout =
1881 (hints->driver_watchdog_timeout *
1882 rte_get_timer_hz()) / 1000;
1886 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1889 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1890 uint16_t next_to_use = tx_ring->next_to_use;
1891 uint16_t next_to_clean = tx_ring->next_to_clean;
1892 struct rte_mbuf *mbuf;
1893 unsigned int ring_size = tx_ring->ring_size;
1894 unsigned int ring_mask = ring_size - 1;
1895 struct ena_com_tx_ctx ena_tx_ctx;
1896 struct ena_tx_buffer *tx_info;
1897 struct ena_com_buf *ebuf;
1898 uint16_t rc, req_id, total_tx_descs = 0;
1899 uint16_t sent_idx = 0, empty_tx_reqs;
1902 /* Check adapter state */
1903 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1905 "Trying to xmit pkts while device is NOT running\n");
1909 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1910 if (nb_pkts > empty_tx_reqs)
1911 nb_pkts = empty_tx_reqs;
1913 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1914 mbuf = tx_pkts[sent_idx];
1916 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1917 tx_info = &tx_ring->tx_buffer_info[req_id];
1918 tx_info->mbuf = mbuf;
1919 tx_info->num_of_bufs = 0;
1920 ebuf = tx_info->bufs;
1922 /* Prepare TX context */
1923 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1924 memset(&ena_tx_ctx.ena_meta, 0x0,
1925 sizeof(struct ena_com_tx_meta));
1926 ena_tx_ctx.ena_bufs = ebuf;
1927 ena_tx_ctx.req_id = req_id;
1928 if (tx_ring->tx_mem_queue_type ==
1929 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1930 /* prepare the push buffer with
1931 * virtual address of the data
1933 ena_tx_ctx.header_len =
1934 RTE_MIN(mbuf->data_len,
1935 tx_ring->tx_max_header_size);
1936 ena_tx_ctx.push_header =
1937 (void *)((char *)mbuf->buf_addr +
1939 } /* there's no else as we take advantage of memset zeroing */
1941 /* Set TX offloads flags, if applicable */
1942 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1944 if (unlikely(mbuf->ol_flags &
1945 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1946 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1948 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1950 /* Process first segment taking into
1951 * consideration pushed header
1953 if (mbuf->data_len > ena_tx_ctx.header_len) {
1954 ebuf->paddr = mbuf->buf_iova +
1956 ena_tx_ctx.header_len;
1957 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1959 tx_info->num_of_bufs++;
1962 while ((mbuf = mbuf->next) != NULL) {
1963 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1964 ebuf->len = mbuf->data_len;
1966 tx_info->num_of_bufs++;
1969 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1971 /* Write data to device */
1972 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1973 &ena_tx_ctx, &nb_hw_desc);
1977 tx_info->tx_descs = nb_hw_desc;
1982 /* If there are ready packets to be xmitted... */
1984 /* ...let HW do its best :-) */
1986 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1988 tx_ring->next_to_use = next_to_use;
1991 /* Clear complete packets */
1992 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1993 /* Get Tx info & store how many descs were processed */
1994 tx_info = &tx_ring->tx_buffer_info[req_id];
1995 total_tx_descs += tx_info->tx_descs;
1997 /* Free whole mbuf chain */
1998 mbuf = tx_info->mbuf;
1999 rte_pktmbuf_free(mbuf);
2000 tx_info->mbuf = NULL;
2002 /* Put back descriptor to the ring for reuse */
2003 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2006 /* If too many descs to clean, leave it for another run */
2007 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2011 if (total_tx_descs > 0) {
2012 /* acknowledge completion of sent packets */
2013 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2014 tx_ring->next_to_clean = next_to_clean;
2020 /*********************************************************************
2022 *********************************************************************/
2023 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2024 struct rte_pci_device *pci_dev)
2026 return rte_eth_dev_pci_generic_probe(pci_dev,
2027 sizeof(struct ena_adapter), eth_ena_dev_init);
2030 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2032 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2035 static struct rte_pci_driver rte_ena_pmd = {
2036 .id_table = pci_id_ena_map,
2037 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2038 .probe = eth_ena_pci_probe,
2039 .remove = eth_ena_pci_remove,
2042 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2043 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2044 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2046 RTE_INIT(ena_init_log);
2050 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2051 if (ena_logtype_init >= 0)
2052 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2053 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2054 if (ena_logtype_driver >= 0)
2055 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2058 /******************************************************************************
2059 ******************************** AENQ Handlers *******************************
2060 *****************************************************************************/
2061 static void ena_update_on_link_change(void *adapter_data,
2062 struct ena_admin_aenq_entry *aenq_e)
2064 struct rte_eth_dev *eth_dev;
2065 struct ena_adapter *adapter;
2066 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2069 adapter = (struct ena_adapter *)adapter_data;
2070 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2071 eth_dev = adapter->rte_dev;
2073 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2074 adapter->link_status = status;
2076 ena_link_update(eth_dev, 0);
2077 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2080 static void ena_notification(void *data,
2081 struct ena_admin_aenq_entry *aenq_e)
2083 struct ena_adapter *adapter = (struct ena_adapter *)data;
2084 struct ena_admin_ena_hw_hints *hints;
2086 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2087 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2088 aenq_e->aenq_common_desc.group,
2089 ENA_ADMIN_NOTIFICATION);
2091 switch (aenq_e->aenq_common_desc.syndrom) {
2092 case ENA_ADMIN_UPDATE_HINTS:
2093 hints = (struct ena_admin_ena_hw_hints *)
2094 (&aenq_e->inline_data_w4);
2095 ena_update_hints(adapter, hints);
2098 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2099 aenq_e->aenq_common_desc.syndrom);
2103 static void ena_keep_alive(void *adapter_data,
2104 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2106 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2108 adapter->timestamp_wd = rte_get_timer_cycles();
2112 * This handler will called for unknown event group or unimplemented handlers
2114 static void unimplemented_aenq_handler(__rte_unused void *data,
2115 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2117 // Unimplemented handler
2120 static struct ena_aenq_handlers aenq_handlers = {
2122 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2123 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2124 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2126 .unimplemented_handler = unimplemented_aenq_handler