4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 1
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 #define ENA_MIN_RING_DESC 128
90 enum ethtool_stringset {
96 char name[ETH_GSTRING_LEN];
100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
102 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
105 #define ENA_STAT_ENTRY(stat, stat_type) { \
107 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
110 #define ENA_STAT_RX_ENTRY(stat) \
111 ENA_STAT_ENTRY(stat, rx)
113 #define ENA_STAT_TX_ENTRY(stat) \
114 ENA_STAT_ENTRY(stat, tx)
116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
117 ENA_STAT_ENTRY(stat, dev)
120 * Each rte_memzone should have unique name.
121 * To satisfy it, count number of allocation and add it to name.
123 uint32_t ena_alloc_cnt;
125 static const struct ena_stats ena_stats_global_strings[] = {
126 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
127 ENA_STAT_GLOBAL_ENTRY(io_suspend),
128 ENA_STAT_GLOBAL_ENTRY(io_resume),
129 ENA_STAT_GLOBAL_ENTRY(wd_expired),
130 ENA_STAT_GLOBAL_ENTRY(interface_up),
131 ENA_STAT_GLOBAL_ENTRY(interface_down),
132 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
135 static const struct ena_stats ena_stats_tx_strings[] = {
136 ENA_STAT_TX_ENTRY(cnt),
137 ENA_STAT_TX_ENTRY(bytes),
138 ENA_STAT_TX_ENTRY(queue_stop),
139 ENA_STAT_TX_ENTRY(queue_wakeup),
140 ENA_STAT_TX_ENTRY(dma_mapping_err),
141 ENA_STAT_TX_ENTRY(linearize),
142 ENA_STAT_TX_ENTRY(linearize_failed),
143 ENA_STAT_TX_ENTRY(tx_poll),
144 ENA_STAT_TX_ENTRY(doorbells),
145 ENA_STAT_TX_ENTRY(prepare_ctx_err),
146 ENA_STAT_TX_ENTRY(missing_tx_comp),
147 ENA_STAT_TX_ENTRY(bad_req_id),
150 static const struct ena_stats ena_stats_rx_strings[] = {
151 ENA_STAT_RX_ENTRY(cnt),
152 ENA_STAT_RX_ENTRY(bytes),
153 ENA_STAT_RX_ENTRY(refil_partial),
154 ENA_STAT_RX_ENTRY(bad_csum),
155 ENA_STAT_RX_ENTRY(page_alloc_fail),
156 ENA_STAT_RX_ENTRY(skb_alloc_fail),
157 ENA_STAT_RX_ENTRY(dma_mapping_err),
158 ENA_STAT_RX_ENTRY(bad_desc_num),
159 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
162 static const struct ena_stats ena_stats_ena_com_strings[] = {
163 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
164 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
165 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
166 ENA_STAT_ENA_COM_ENTRY(out_of_space),
167 ENA_STAT_ENA_COM_ENTRY(no_completion),
170 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
171 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
172 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
173 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
175 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
176 DEV_TX_OFFLOAD_UDP_CKSUM |\
177 DEV_TX_OFFLOAD_IPV4_CKSUM |\
178 DEV_TX_OFFLOAD_TCP_TSO)
179 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
183 /** Vendor ID used by Amazon devices */
184 #define PCI_VENDOR_ID_AMAZON 0x1D0F
185 /** Amazon devices */
186 #define PCI_DEVICE_ID_ENA_VF 0xEC20
187 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
189 #define ENA_TX_OFFLOAD_MASK (\
196 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
197 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
199 int ena_logtype_init;
200 int ena_logtype_driver;
202 static const struct rte_pci_id pci_id_ena_map[] = {
203 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
204 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
208 static struct ena_aenq_handlers aenq_handlers;
210 static int ena_device_init(struct ena_com_dev *ena_dev,
211 struct ena_com_dev_get_features_ctx *get_feat_ctx,
213 static int ena_dev_configure(struct rte_eth_dev *dev);
214 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
216 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
218 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
219 uint16_t nb_desc, unsigned int socket_id,
220 const struct rte_eth_txconf *tx_conf);
221 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
222 uint16_t nb_desc, unsigned int socket_id,
223 const struct rte_eth_rxconf *rx_conf,
224 struct rte_mempool *mp);
225 static uint16_t eth_ena_recv_pkts(void *rx_queue,
226 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
227 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
228 static void ena_init_rings(struct ena_adapter *adapter);
229 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
230 static int ena_start(struct rte_eth_dev *dev);
231 static void ena_stop(struct rte_eth_dev *dev);
232 static void ena_close(struct rte_eth_dev *dev);
233 static int ena_dev_reset(struct rte_eth_dev *dev);
234 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
235 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
236 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
237 static void ena_rx_queue_release(void *queue);
238 static void ena_tx_queue_release(void *queue);
239 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
240 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
241 static int ena_link_update(struct rte_eth_dev *dev,
242 int wait_to_complete);
243 static int ena_create_io_queue(struct ena_ring *ring);
244 static void ena_free_io_queues_all(struct ena_adapter *adapter);
245 static int ena_queue_restart(struct ena_ring *ring);
246 static int ena_queue_restart_all(struct rte_eth_dev *dev,
247 enum ena_ring_type ring_type);
248 static void ena_stats_restart(struct rte_eth_dev *dev);
249 static void ena_infos_get(struct rte_eth_dev *dev,
250 struct rte_eth_dev_info *dev_info);
251 static int ena_rss_reta_update(struct rte_eth_dev *dev,
252 struct rte_eth_rss_reta_entry64 *reta_conf,
254 static int ena_rss_reta_query(struct rte_eth_dev *dev,
255 struct rte_eth_rss_reta_entry64 *reta_conf,
257 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
258 static void ena_interrupt_handler_rte(void *cb_arg);
259 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
261 static const struct eth_dev_ops ena_dev_ops = {
262 .dev_configure = ena_dev_configure,
263 .dev_infos_get = ena_infos_get,
264 .rx_queue_setup = ena_rx_queue_setup,
265 .tx_queue_setup = ena_tx_queue_setup,
266 .dev_start = ena_start,
267 .dev_stop = ena_stop,
268 .link_update = ena_link_update,
269 .stats_get = ena_stats_get,
270 .mtu_set = ena_mtu_set,
271 .rx_queue_release = ena_rx_queue_release,
272 .tx_queue_release = ena_tx_queue_release,
273 .dev_close = ena_close,
274 .dev_reset = ena_dev_reset,
275 .reta_update = ena_rss_reta_update,
276 .reta_query = ena_rss_reta_query,
279 #define NUMA_NO_NODE SOCKET_ID_ANY
281 static inline int ena_cpu_to_node(int cpu)
283 struct rte_config *config = rte_eal_get_configuration();
284 struct rte_fbarray *arr = &config->mem_config->memzones;
285 const struct rte_memzone *mz;
287 if (unlikely(cpu >= RTE_MAX_MEMZONE))
290 mz = rte_fbarray_get(arr, cpu);
292 return mz->socket_id;
295 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
296 struct ena_com_rx_ctx *ena_rx_ctx)
298 uint64_t ol_flags = 0;
299 uint32_t packet_type = 0;
301 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
302 packet_type |= RTE_PTYPE_L4_TCP;
303 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
304 packet_type |= RTE_PTYPE_L4_UDP;
306 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
307 packet_type |= RTE_PTYPE_L3_IPV4;
308 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
309 packet_type |= RTE_PTYPE_L3_IPV6;
311 if (unlikely(ena_rx_ctx->l4_csum_err))
312 ol_flags |= PKT_RX_L4_CKSUM_BAD;
313 if (unlikely(ena_rx_ctx->l3_csum_err))
314 ol_flags |= PKT_RX_IP_CKSUM_BAD;
316 mbuf->ol_flags = ol_flags;
317 mbuf->packet_type = packet_type;
320 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
321 struct ena_com_tx_ctx *ena_tx_ctx,
322 uint64_t queue_offloads)
324 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
326 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
327 (queue_offloads & QUEUE_OFFLOADS)) {
328 /* check if TSO is required */
329 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
330 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
331 ena_tx_ctx->tso_enable = true;
333 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
336 /* check if L3 checksum is needed */
337 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
338 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
339 ena_tx_ctx->l3_csum_enable = true;
341 if (mbuf->ol_flags & PKT_TX_IPV6) {
342 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
346 /* set don't fragment (DF) flag */
347 if (mbuf->packet_type &
348 (RTE_PTYPE_L4_NONFRAG
349 | RTE_PTYPE_INNER_L4_NONFRAG))
350 ena_tx_ctx->df = true;
353 /* check if L4 checksum is needed */
354 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
355 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
357 ena_tx_ctx->l4_csum_enable = true;
358 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
359 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
360 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
361 ena_tx_ctx->l4_csum_enable = true;
363 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
364 ena_tx_ctx->l4_csum_enable = false;
367 ena_meta->mss = mbuf->tso_segsz;
368 ena_meta->l3_hdr_len = mbuf->l3_len;
369 ena_meta->l3_hdr_offset = mbuf->l2_len;
371 ena_tx_ctx->meta_valid = true;
373 ena_tx_ctx->meta_valid = false;
377 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
379 if (likely(req_id < rx_ring->ring_size))
382 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
384 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
385 rx_ring->adapter->trigger_reset = true;
390 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
392 struct ena_tx_buffer *tx_info = NULL;
394 if (likely(req_id < tx_ring->ring_size)) {
395 tx_info = &tx_ring->tx_buffer_info[req_id];
396 if (likely(tx_info->mbuf))
401 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
403 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
405 /* Trigger device reset */
406 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
407 tx_ring->adapter->trigger_reset = true;
411 static void ena_config_host_info(struct ena_com_dev *ena_dev)
413 struct ena_admin_host_info *host_info;
416 /* Allocate only the host info */
417 rc = ena_com_allocate_host_info(ena_dev);
419 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
423 host_info = ena_dev->host_attr.host_info;
425 host_info->os_type = ENA_ADMIN_OS_DPDK;
426 host_info->kernel_ver = RTE_VERSION;
427 snprintf((char *)host_info->kernel_ver_str,
428 sizeof(host_info->kernel_ver_str),
429 "%s", rte_version());
430 host_info->os_dist = RTE_VERSION;
431 snprintf((char *)host_info->os_dist_str,
432 sizeof(host_info->os_dist_str),
433 "%s", rte_version());
434 host_info->driver_version =
435 (DRV_MODULE_VER_MAJOR) |
436 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
437 (DRV_MODULE_VER_SUBMINOR <<
438 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
439 host_info->num_cpus = rte_lcore_count();
441 rc = ena_com_set_host_attributes(ena_dev);
443 if (rc == -ENA_COM_UNSUPPORTED)
444 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
446 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
454 ena_com_delete_host_info(ena_dev);
458 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
460 if (sset != ETH_SS_STATS)
463 /* Workaround for clang:
464 * touch internal structures to prevent
467 ENA_TOUCH(ena_stats_global_strings);
468 ENA_TOUCH(ena_stats_tx_strings);
469 ENA_TOUCH(ena_stats_rx_strings);
470 ENA_TOUCH(ena_stats_ena_com_strings);
472 return dev->data->nb_tx_queues *
473 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
474 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
477 static void ena_config_debug_area(struct ena_adapter *adapter)
482 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
484 RTE_LOG(ERR, PMD, "SS count is negative\n");
488 /* allocate 32 bytes for each string and 64bit for the value */
489 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
491 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
493 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
497 rc = ena_com_set_host_attributes(&adapter->ena_dev);
499 if (rc == -ENA_COM_UNSUPPORTED)
500 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
502 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
509 ena_com_delete_debug_area(&adapter->ena_dev);
512 static void ena_close(struct rte_eth_dev *dev)
514 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
515 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
516 struct ena_adapter *adapter =
517 (struct ena_adapter *)(dev->data->dev_private);
519 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
521 adapter->state = ENA_ADAPTER_STATE_CLOSED;
523 ena_rx_queue_release_all(dev);
524 ena_tx_queue_release_all(dev);
526 rte_free(adapter->drv_stats);
527 adapter->drv_stats = NULL;
529 rte_intr_disable(intr_handle);
530 rte_intr_callback_unregister(intr_handle,
531 ena_interrupt_handler_rte,
535 * MAC is not allocated dynamically. Setting NULL should prevent from
536 * release of the resource in the rte_eth_dev_release_port().
538 dev->data->mac_addrs = NULL;
542 ena_dev_reset(struct rte_eth_dev *dev)
544 struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
545 struct rte_eth_dev *eth_dev;
546 struct rte_pci_device *pci_dev;
547 struct rte_intr_handle *intr_handle;
548 struct ena_com_dev *ena_dev;
549 struct ena_com_dev_get_features_ctx get_feat_ctx;
550 struct ena_adapter *adapter;
555 adapter = (struct ena_adapter *)(dev->data->dev_private);
556 ena_dev = &adapter->ena_dev;
557 eth_dev = adapter->rte_dev;
558 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
559 intr_handle = &pci_dev->intr_handle;
560 nb_queues = eth_dev->data->nb_rx_queues;
562 ena_com_set_admin_running_state(ena_dev, false);
564 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
566 RTE_LOG(ERR, PMD, "Device reset failed\n");
568 for (i = 0; i < nb_queues; i++)
569 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
571 ena_rx_queue_release_all(eth_dev);
572 ena_tx_queue_release_all(eth_dev);
574 rte_intr_disable(intr_handle);
576 ena_com_abort_admin_commands(ena_dev);
577 ena_com_wait_for_abort_completion(ena_dev);
578 ena_com_admin_destroy(ena_dev);
579 ena_com_mmio_reg_read_request_destroy(ena_dev);
581 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
583 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
586 adapter->wd_state = wd_state;
588 rte_intr_enable(intr_handle);
589 ena_com_set_admin_polling_mode(ena_dev, false);
590 ena_com_admin_aenq_enable(ena_dev);
592 for (i = 0; i < nb_queues; ++i)
593 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring[i].ring_size, 0,
594 NULL, mb_pool_rx[i]);
596 for (i = 0; i < nb_queues; ++i)
597 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring[i].ring_size, 0,
600 adapter->trigger_reset = false;
605 static int ena_rss_reta_update(struct rte_eth_dev *dev,
606 struct rte_eth_rss_reta_entry64 *reta_conf,
609 struct ena_adapter *adapter =
610 (struct ena_adapter *)(dev->data->dev_private);
611 struct ena_com_dev *ena_dev = &adapter->ena_dev;
617 if ((reta_size == 0) || (reta_conf == NULL))
620 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
621 RTE_LOG(WARNING, PMD,
622 "indirection table %d is bigger than supported (%d)\n",
623 reta_size, ENA_RX_RSS_TABLE_SIZE);
627 for (i = 0 ; i < reta_size ; i++) {
628 /* each reta_conf is for 64 entries.
629 * to support 128 we use 2 conf of 64
631 conf_idx = i / RTE_RETA_GROUP_SIZE;
632 idx = i % RTE_RETA_GROUP_SIZE;
633 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
635 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
637 rc = ena_com_indirect_table_fill_entry(ena_dev,
640 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
642 "Cannot fill indirect table\n");
648 rc = ena_com_indirect_table_set(ena_dev);
649 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
650 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
654 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
655 __func__, reta_size, adapter->rte_dev->data->port_id);
660 /* Query redirection table. */
661 static int ena_rss_reta_query(struct rte_eth_dev *dev,
662 struct rte_eth_rss_reta_entry64 *reta_conf,
665 struct ena_adapter *adapter =
666 (struct ena_adapter *)(dev->data->dev_private);
667 struct ena_com_dev *ena_dev = &adapter->ena_dev;
670 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
674 if (reta_size == 0 || reta_conf == NULL ||
675 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
678 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
679 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
680 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
684 for (i = 0 ; i < reta_size ; i++) {
685 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
686 reta_idx = i % RTE_RETA_GROUP_SIZE;
687 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
688 reta_conf[reta_conf_idx].reta[reta_idx] =
689 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
695 static int ena_rss_init_default(struct ena_adapter *adapter)
697 struct ena_com_dev *ena_dev = &adapter->ena_dev;
698 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
702 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
704 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
708 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
709 val = i % nb_rx_queues;
710 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
711 ENA_IO_RXQ_IDX(val));
712 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
713 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
718 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
719 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
720 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
721 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
725 rc = ena_com_set_default_hash_ctrl(ena_dev);
726 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
727 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
731 rc = ena_com_indirect_table_set(ena_dev);
732 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
733 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
736 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
737 adapter->rte_dev->data->port_id);
742 ena_com_rss_destroy(ena_dev);
748 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
750 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
751 int nb_queues = dev->data->nb_rx_queues;
754 for (i = 0; i < nb_queues; i++)
755 ena_rx_queue_release(queues[i]);
758 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
760 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
761 int nb_queues = dev->data->nb_tx_queues;
764 for (i = 0; i < nb_queues; i++)
765 ena_tx_queue_release(queues[i]);
768 static void ena_rx_queue_release(void *queue)
770 struct ena_ring *ring = (struct ena_ring *)queue;
772 ena_assert_msg(ring->configured,
773 "API violation - releasing not configured queue");
774 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
777 /* Free ring resources */
778 if (ring->rx_buffer_info)
779 rte_free(ring->rx_buffer_info);
780 ring->rx_buffer_info = NULL;
782 if (ring->rx_refill_buffer)
783 rte_free(ring->rx_refill_buffer);
784 ring->rx_refill_buffer = NULL;
786 if (ring->empty_rx_reqs)
787 rte_free(ring->empty_rx_reqs);
788 ring->empty_rx_reqs = NULL;
790 ring->configured = 0;
792 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
793 ring->port_id, ring->id);
796 static void ena_tx_queue_release(void *queue)
798 struct ena_ring *ring = (struct ena_ring *)queue;
800 ena_assert_msg(ring->configured,
801 "API violation. Releasing not configured queue");
802 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
806 ena_tx_queue_release_bufs(ring);
808 /* Free ring resources */
809 if (ring->tx_buffer_info)
810 rte_free(ring->tx_buffer_info);
812 if (ring->empty_tx_reqs)
813 rte_free(ring->empty_tx_reqs);
815 ring->empty_tx_reqs = NULL;
816 ring->tx_buffer_info = NULL;
818 ring->configured = 0;
820 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
821 ring->port_id, ring->id);
824 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
826 unsigned int ring_mask = ring->ring_size - 1;
828 while (ring->next_to_clean != ring->next_to_use) {
830 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
833 rte_mbuf_raw_free(m);
835 ring->next_to_clean++;
839 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
843 for (i = 0; i < ring->ring_size; ++i) {
844 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
847 rte_pktmbuf_free(tx_buf->mbuf);
849 ring->next_to_clean++;
853 static int ena_link_update(struct rte_eth_dev *dev,
854 __rte_unused int wait_to_complete)
856 struct rte_eth_link *link = &dev->data->dev_link;
857 struct ena_adapter *adapter;
859 adapter = (struct ena_adapter *)(dev->data->dev_private);
861 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
862 link->link_speed = ETH_SPEED_NUM_NONE;
863 link->link_duplex = ETH_LINK_FULL_DUPLEX;
868 static int ena_queue_restart_all(struct rte_eth_dev *dev,
869 enum ena_ring_type ring_type)
871 struct ena_adapter *adapter =
872 (struct ena_adapter *)(dev->data->dev_private);
873 struct ena_ring *queues = NULL;
878 if (ring_type == ENA_RING_TYPE_RX) {
879 queues = adapter->rx_ring;
880 nb_queues = dev->data->nb_rx_queues;
882 queues = adapter->tx_ring;
883 nb_queues = dev->data->nb_tx_queues;
885 for (i = 0; i < nb_queues; i++) {
886 if (queues[i].configured) {
887 if (ring_type == ENA_RING_TYPE_RX) {
889 dev->data->rx_queues[i] == &queues[i],
890 "Inconsistent state of rx queues\n");
893 dev->data->tx_queues[i] == &queues[i],
894 "Inconsistent state of tx queues\n");
897 rc = ena_queue_restart(&queues[i]);
901 "failed to restart queue %d type(%d)",
911 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
913 uint32_t max_frame_len = adapter->max_mtu;
915 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
916 DEV_RX_OFFLOAD_JUMBO_FRAME)
918 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
920 return max_frame_len;
923 static int ena_check_valid_conf(struct ena_adapter *adapter)
925 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
927 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
928 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
929 "max mtu: %d, min mtu: %d\n",
930 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
931 return ENA_COM_UNSUPPORTED;
938 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
940 uint32_t tx_queue_size, rx_queue_size;
942 if (ctx->ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
943 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
944 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
945 rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
946 max_queue_ext->max_rx_sq_depth);
947 tx_queue_size = RTE_MIN(max_queue_ext->max_tx_cq_depth,
948 max_queue_ext->max_tx_sq_depth);
949 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
950 max_queue_ext->max_per_packet_rx_descs);
951 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
952 max_queue_ext->max_per_packet_tx_descs);
954 struct ena_admin_queue_feature_desc *max_queues =
955 &ctx->get_feat_ctx->max_queues;
956 rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
957 max_queues->max_sq_depth);
958 tx_queue_size = rx_queue_size;
959 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
960 max_queues->max_packet_tx_descs);
961 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
962 max_queues->max_packet_rx_descs);
965 /* Round down to the nearest power of 2 */
966 rx_queue_size = rte_align32prevpow2(rx_queue_size);
967 tx_queue_size = rte_align32prevpow2(tx_queue_size);
969 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
970 PMD_INIT_LOG(ERR, "Invalid queue size");
974 ctx->rx_queue_size = rx_queue_size;
975 ctx->tx_queue_size = tx_queue_size;
980 static void ena_stats_restart(struct rte_eth_dev *dev)
982 struct ena_adapter *adapter =
983 (struct ena_adapter *)(dev->data->dev_private);
985 rte_atomic64_init(&adapter->drv_stats->ierrors);
986 rte_atomic64_init(&adapter->drv_stats->oerrors);
987 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
990 static int ena_stats_get(struct rte_eth_dev *dev,
991 struct rte_eth_stats *stats)
993 struct ena_admin_basic_stats ena_stats;
994 struct ena_adapter *adapter =
995 (struct ena_adapter *)(dev->data->dev_private);
996 struct ena_com_dev *ena_dev = &adapter->ena_dev;
999 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1002 memset(&ena_stats, 0, sizeof(ena_stats));
1003 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
1005 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
1009 /* Set of basic statistics from ENA */
1010 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1011 ena_stats.rx_pkts_low);
1012 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1013 ena_stats.tx_pkts_low);
1014 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1015 ena_stats.rx_bytes_low);
1016 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1017 ena_stats.tx_bytes_low);
1018 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1019 ena_stats.rx_drops_low);
1021 /* Driver related stats */
1022 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1023 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1024 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1028 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1030 struct ena_adapter *adapter;
1031 struct ena_com_dev *ena_dev;
1034 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1035 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1036 adapter = (struct ena_adapter *)(dev->data->dev_private);
1038 ena_dev = &adapter->ena_dev;
1039 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1041 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1043 "Invalid MTU setting. new_mtu: %d "
1044 "max mtu: %d min mtu: %d\n",
1045 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1049 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1051 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1053 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1058 static int ena_start(struct rte_eth_dev *dev)
1060 struct ena_adapter *adapter =
1061 (struct ena_adapter *)(dev->data->dev_private);
1065 rc = ena_check_valid_conf(adapter);
1069 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1073 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1077 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1078 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1079 rc = ena_rss_init_default(adapter);
1084 ena_stats_restart(dev);
1086 adapter->timestamp_wd = rte_get_timer_cycles();
1087 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1089 ticks = rte_get_timer_hz();
1090 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1091 ena_timer_wd_callback, adapter);
1093 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1098 static void ena_stop(struct rte_eth_dev *dev)
1100 struct ena_adapter *adapter =
1101 (struct ena_adapter *)(dev->data->dev_private);
1103 rte_timer_stop_sync(&adapter->timer_wd);
1104 ena_free_io_queues_all(adapter);
1106 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1109 static int ena_create_io_queue(struct ena_ring *ring)
1111 struct ena_adapter *adapter;
1112 struct ena_com_dev *ena_dev;
1113 struct ena_com_create_io_ctx ctx =
1114 /* policy set to _HOST just to satisfy icc compiler */
1115 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1121 adapter = ring->adapter;
1122 ena_dev = &adapter->ena_dev;
1124 if (ring->type == ENA_RING_TYPE_TX) {
1125 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1126 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1127 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1128 ctx.queue_size = adapter->tx_ring_size;
1129 for (i = 0; i < ring->ring_size; i++)
1130 ring->empty_tx_reqs[i] = i;
1132 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1133 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1134 ctx.queue_size = adapter->rx_ring_size;
1135 for (i = 0; i < ring->ring_size; i++)
1136 ring->empty_rx_reqs[i] = i;
1139 ctx.msix_vector = -1; /* interrupts not used */
1140 ctx.numa_node = ena_cpu_to_node(ring->id);
1142 rc = ena_com_create_io_queue(ena_dev, &ctx);
1145 "failed to create io queue #%d (qid:%d) rc: %d\n",
1146 ring->id, ena_qid, rc);
1150 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1151 &ring->ena_com_io_sq,
1152 &ring->ena_com_io_cq);
1155 "Failed to get io queue handlers. queue num %d rc: %d\n",
1157 ena_com_destroy_io_queue(ena_dev, ena_qid);
1161 if (ring->type == ENA_RING_TYPE_TX)
1162 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1167 static void ena_free_io_queues_all(struct ena_adapter *adapter)
1169 struct rte_eth_dev *eth_dev = adapter->rte_dev;
1170 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1173 uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
1174 uint16_t nb_txq = eth_dev->data->nb_tx_queues;
1176 for (i = 0; i < nb_txq; ++i) {
1177 ena_qid = ENA_IO_TXQ_IDX(i);
1178 ena_com_destroy_io_queue(ena_dev, ena_qid);
1180 ena_tx_queue_release_bufs(&adapter->tx_ring[i]);
1183 for (i = 0; i < nb_rxq; ++i) {
1184 ena_qid = ENA_IO_RXQ_IDX(i);
1185 ena_com_destroy_io_queue(ena_dev, ena_qid);
1187 ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
1191 static int ena_queue_restart(struct ena_ring *ring)
1195 ena_assert_msg(ring->configured == 1,
1196 "Trying to restart unconfigured queue\n");
1198 rc = ena_create_io_queue(ring);
1200 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1204 ring->next_to_clean = 0;
1205 ring->next_to_use = 0;
1207 if (ring->type == ENA_RING_TYPE_TX)
1210 bufs_num = ring->ring_size - 1;
1211 rc = ena_populate_rx_queue(ring, bufs_num);
1212 if (rc != bufs_num) {
1213 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1214 return ENA_COM_FAULT;
1220 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1223 __rte_unused unsigned int socket_id,
1224 const struct rte_eth_txconf *tx_conf)
1226 struct ena_ring *txq = NULL;
1227 struct ena_adapter *adapter =
1228 (struct ena_adapter *)(dev->data->dev_private);
1231 txq = &adapter->tx_ring[queue_idx];
1233 if (txq->configured) {
1235 "API violation. Queue %d is already configured\n",
1237 return ENA_COM_FAULT;
1240 if (!rte_is_power_of_2(nb_desc)) {
1242 "Unsupported size of TX queue: %d is not a power of 2.",
1247 if (nb_desc > adapter->tx_ring_size) {
1249 "Unsupported size of TX queue (max size: %d)\n",
1250 adapter->tx_ring_size);
1254 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1255 nb_desc = adapter->tx_ring_size;
1257 txq->port_id = dev->data->port_id;
1258 txq->next_to_clean = 0;
1259 txq->next_to_use = 0;
1260 txq->ring_size = nb_desc;
1262 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1263 sizeof(struct ena_tx_buffer) *
1265 RTE_CACHE_LINE_SIZE);
1266 if (!txq->tx_buffer_info) {
1267 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1271 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1272 sizeof(u16) * txq->ring_size,
1273 RTE_CACHE_LINE_SIZE);
1274 if (!txq->empty_tx_reqs) {
1275 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1276 rte_free(txq->tx_buffer_info);
1280 for (i = 0; i < txq->ring_size; i++)
1281 txq->empty_tx_reqs[i] = i;
1283 if (tx_conf != NULL) {
1285 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1288 /* Store pointer to this queue in upper layer */
1289 txq->configured = 1;
1290 dev->data->tx_queues[queue_idx] = txq;
1295 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1298 __rte_unused unsigned int socket_id,
1299 __rte_unused const struct rte_eth_rxconf *rx_conf,
1300 struct rte_mempool *mp)
1302 struct ena_adapter *adapter =
1303 (struct ena_adapter *)(dev->data->dev_private);
1304 struct ena_ring *rxq = NULL;
1307 rxq = &adapter->rx_ring[queue_idx];
1308 if (rxq->configured) {
1310 "API violation. Queue %d is already configured\n",
1312 return ENA_COM_FAULT;
1315 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1316 nb_desc = adapter->rx_ring_size;
1318 if (!rte_is_power_of_2(nb_desc)) {
1320 "Unsupported size of RX queue: %d is not a power of 2.",
1325 if (nb_desc > adapter->rx_ring_size) {
1327 "Unsupported size of RX queue (max size: %d)\n",
1328 adapter->rx_ring_size);
1332 rxq->port_id = dev->data->port_id;
1333 rxq->next_to_clean = 0;
1334 rxq->next_to_use = 0;
1335 rxq->ring_size = nb_desc;
1338 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1339 sizeof(struct rte_mbuf *) * nb_desc,
1340 RTE_CACHE_LINE_SIZE);
1341 if (!rxq->rx_buffer_info) {
1342 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1346 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1347 sizeof(struct rte_mbuf *) * nb_desc,
1348 RTE_CACHE_LINE_SIZE);
1350 if (!rxq->rx_refill_buffer) {
1351 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1352 rte_free(rxq->rx_buffer_info);
1353 rxq->rx_buffer_info = NULL;
1357 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1358 sizeof(uint16_t) * nb_desc,
1359 RTE_CACHE_LINE_SIZE);
1360 if (!rxq->empty_rx_reqs) {
1361 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1362 rte_free(rxq->rx_buffer_info);
1363 rxq->rx_buffer_info = NULL;
1364 rte_free(rxq->rx_refill_buffer);
1365 rxq->rx_refill_buffer = NULL;
1369 for (i = 0; i < nb_desc; i++)
1370 rxq->empty_tx_reqs[i] = i;
1372 /* Store pointer to this queue in upper layer */
1373 rxq->configured = 1;
1374 dev->data->rx_queues[queue_idx] = rxq;
1379 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1383 uint16_t ring_size = rxq->ring_size;
1384 uint16_t ring_mask = ring_size - 1;
1385 uint16_t next_to_use = rxq->next_to_use;
1386 uint16_t in_use, req_id;
1387 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1389 if (unlikely(!count))
1392 in_use = rxq->next_to_use - rxq->next_to_clean;
1393 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1395 /* get resources for incoming packets */
1396 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1397 if (unlikely(rc < 0)) {
1398 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1399 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1403 for (i = 0; i < count; i++) {
1404 uint16_t next_to_use_masked = next_to_use & ring_mask;
1405 struct rte_mbuf *mbuf = mbufs[i];
1406 struct ena_com_buf ebuf;
1408 if (likely((i + 4) < count))
1409 rte_prefetch0(mbufs[i + 4]);
1411 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1412 rc = validate_rx_req_id(rxq, req_id);
1413 if (unlikely(rc < 0))
1415 rxq->rx_buffer_info[req_id] = mbuf;
1417 /* prepare physical address for DMA transaction */
1418 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1419 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1420 /* pass resource to device */
1421 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1424 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1425 rxq->rx_buffer_info[req_id] = NULL;
1431 if (unlikely(i < count)) {
1432 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1433 "buffers (from %d)\n", rxq->id, i, count);
1434 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1438 /* When we submitted free recources to device... */
1439 if (likely(i > 0)) {
1440 /* ...let HW know that it can fill buffers with data
1442 * Add memory barrier to make sure the desc were written before
1446 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1448 rxq->next_to_use = next_to_use;
1454 static int ena_device_init(struct ena_com_dev *ena_dev,
1455 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1458 uint32_t aenq_groups;
1460 bool readless_supported;
1462 /* Initialize mmio registers */
1463 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1465 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1469 /* The PCIe configuration space revision id indicate if mmio reg
1472 readless_supported =
1473 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1474 & ENA_MMIO_DISABLE_REG_READ);
1475 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1478 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1480 RTE_LOG(ERR, PMD, "cannot reset device\n");
1481 goto err_mmio_read_less;
1484 /* check FW version */
1485 rc = ena_com_validate_version(ena_dev);
1487 RTE_LOG(ERR, PMD, "device version is too low\n");
1488 goto err_mmio_read_less;
1491 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1493 /* ENA device administration layer init */
1494 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1497 "cannot initialize ena admin queue with device\n");
1498 goto err_mmio_read_less;
1501 /* To enable the msix interrupts the driver needs to know the number
1502 * of queues. So the driver uses polling mode to retrieve this
1505 ena_com_set_admin_polling_mode(ena_dev, true);
1507 ena_config_host_info(ena_dev);
1509 /* Get Device Attributes and features */
1510 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1513 "cannot get attribute for ena device rc= %d\n", rc);
1514 goto err_admin_init;
1517 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1518 BIT(ENA_ADMIN_NOTIFICATION) |
1519 BIT(ENA_ADMIN_KEEP_ALIVE) |
1520 BIT(ENA_ADMIN_FATAL_ERROR) |
1521 BIT(ENA_ADMIN_WARNING);
1523 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1524 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1526 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1527 goto err_admin_init;
1530 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1535 ena_com_admin_destroy(ena_dev);
1538 ena_com_mmio_reg_read_request_destroy(ena_dev);
1543 static void ena_interrupt_handler_rte(void *cb_arg)
1545 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1546 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1548 ena_com_admin_q_comp_intr_handler(ena_dev);
1549 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1550 ena_com_aenq_intr_handler(ena_dev, adapter);
1553 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1555 if (!adapter->wd_state)
1558 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1561 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1562 adapter->keep_alive_timeout)) {
1563 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1564 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1565 adapter->trigger_reset = true;
1569 /* Check if admin queue is enabled */
1570 static void check_for_admin_com_state(struct ena_adapter *adapter)
1572 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1573 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1574 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1575 adapter->trigger_reset = true;
1579 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1582 struct ena_adapter *adapter = (struct ena_adapter *)arg;
1583 struct rte_eth_dev *dev = adapter->rte_dev;
1585 check_for_missing_keep_alive(adapter);
1586 check_for_admin_com_state(adapter);
1588 if (unlikely(adapter->trigger_reset)) {
1589 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1590 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1595 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1596 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1598 uint32_t io_sq_num, io_cq_num, io_queue_num;
1600 /* Regular queues capabilities */
1601 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1602 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1603 &get_feat_ctx->max_queue_ext.max_queue_ext;
1604 io_sq_num = max_queue_ext->max_rx_sq_num;
1605 io_sq_num = RTE_MIN(io_sq_num, max_queue_ext->max_tx_sq_num);
1607 io_cq_num = max_queue_ext->max_rx_cq_num;
1608 io_cq_num = RTE_MIN(io_cq_num, max_queue_ext->max_tx_cq_num);
1610 struct ena_admin_queue_feature_desc *max_queues =
1611 &get_feat_ctx->max_queues;
1612 io_sq_num = max_queues->max_sq_num;
1613 io_cq_num = max_queues->max_cq_num;
1616 io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1618 if (unlikely(io_queue_num == 0)) {
1619 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1623 return io_queue_num;
1626 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1628 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1629 struct rte_pci_device *pci_dev;
1630 struct rte_intr_handle *intr_handle;
1631 struct ena_adapter *adapter =
1632 (struct ena_adapter *)(eth_dev->data->dev_private);
1633 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1634 struct ena_com_dev_get_features_ctx get_feat_ctx;
1637 static int adapters_found;
1640 memset(adapter, 0, sizeof(struct ena_adapter));
1641 ena_dev = &adapter->ena_dev;
1643 eth_dev->dev_ops = &ena_dev_ops;
1644 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1645 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1646 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1647 adapter->rte_eth_dev_data = eth_dev->data;
1648 adapter->rte_dev = eth_dev;
1650 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1653 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1654 adapter->pdev = pci_dev;
1656 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1657 pci_dev->addr.domain,
1659 pci_dev->addr.devid,
1660 pci_dev->addr.function);
1662 intr_handle = &pci_dev->intr_handle;
1664 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1665 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1667 if (!adapter->regs) {
1668 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1673 ena_dev->reg_bar = adapter->regs;
1674 ena_dev->dmadev = adapter->pdev;
1676 adapter->id_number = adapters_found;
1678 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1679 adapter->id_number);
1681 /* device specific initialization routine */
1682 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1684 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1687 adapter->wd_state = wd_state;
1689 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1691 calc_queue_ctx.ena_dev = ena_dev;
1692 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1694 adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1697 rc = ena_calc_queue_size(&calc_queue_ctx);
1698 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1700 goto err_device_destroy;
1703 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1704 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1706 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1707 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1709 /* prepare ring structures */
1710 ena_init_rings(adapter);
1712 ena_config_debug_area(adapter);
1714 /* Set max MTU for this device */
1715 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1717 /* set device support for TSO */
1718 adapter->tso4_supported = get_feat_ctx.offload.tx &
1719 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1721 /* Copy MAC address and point DPDK to it */
1722 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1723 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1724 (struct ether_addr *)adapter->mac_addr);
1727 * Pass the information to the rte_eth_dev_close() that it should also
1728 * release the private port resources.
1730 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1732 adapter->drv_stats = rte_zmalloc("adapter stats",
1733 sizeof(*adapter->drv_stats),
1734 RTE_CACHE_LINE_SIZE);
1735 if (!adapter->drv_stats) {
1736 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1738 goto err_delete_debug_area;
1741 rte_intr_callback_register(intr_handle,
1742 ena_interrupt_handler_rte,
1744 rte_intr_enable(intr_handle);
1745 ena_com_set_admin_polling_mode(ena_dev, false);
1746 ena_com_admin_aenq_enable(ena_dev);
1748 if (adapters_found == 0)
1749 rte_timer_subsystem_init();
1750 rte_timer_init(&adapter->timer_wd);
1753 adapter->state = ENA_ADAPTER_STATE_INIT;
1757 err_delete_debug_area:
1758 ena_com_delete_debug_area(ena_dev);
1761 ena_com_delete_host_info(ena_dev);
1762 ena_com_admin_destroy(ena_dev);
1768 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1770 struct ena_adapter *adapter =
1771 (struct ena_adapter *)(eth_dev->data->dev_private);
1773 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1776 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1779 eth_dev->dev_ops = NULL;
1780 eth_dev->rx_pkt_burst = NULL;
1781 eth_dev->tx_pkt_burst = NULL;
1782 eth_dev->tx_pkt_prepare = NULL;
1784 adapter->state = ENA_ADAPTER_STATE_FREE;
1789 static int ena_dev_configure(struct rte_eth_dev *dev)
1791 struct ena_adapter *adapter =
1792 (struct ena_adapter *)(dev->data->dev_private);
1794 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1796 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1797 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1801 static void ena_init_rings(struct ena_adapter *adapter)
1805 for (i = 0; i < adapter->num_queues; i++) {
1806 struct ena_ring *ring = &adapter->tx_ring[i];
1808 ring->configured = 0;
1809 ring->type = ENA_RING_TYPE_TX;
1810 ring->adapter = adapter;
1812 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1813 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1814 ring->sgl_size = adapter->max_tx_sgl_size;
1817 for (i = 0; i < adapter->num_queues; i++) {
1818 struct ena_ring *ring = &adapter->rx_ring[i];
1820 ring->configured = 0;
1821 ring->type = ENA_RING_TYPE_RX;
1822 ring->adapter = adapter;
1824 ring->sgl_size = adapter->max_rx_sgl_size;
1828 static void ena_infos_get(struct rte_eth_dev *dev,
1829 struct rte_eth_dev_info *dev_info)
1831 struct ena_adapter *adapter;
1832 struct ena_com_dev *ena_dev;
1833 struct ena_com_dev_get_features_ctx feat;
1834 uint64_t rx_feat = 0, tx_feat = 0;
1837 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1838 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1839 adapter = (struct ena_adapter *)(dev->data->dev_private);
1841 ena_dev = &adapter->ena_dev;
1842 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1844 dev_info->speed_capa =
1846 ETH_LINK_SPEED_2_5G |
1848 ETH_LINK_SPEED_10G |
1849 ETH_LINK_SPEED_25G |
1850 ETH_LINK_SPEED_40G |
1851 ETH_LINK_SPEED_50G |
1852 ETH_LINK_SPEED_100G;
1854 /* Get supported features from HW */
1855 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1858 "Cannot get attribute for ena device rc= %d\n", rc);
1862 /* Set Tx & Rx features available for device */
1863 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1864 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1866 if (feat.offload.tx &
1867 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1868 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1869 DEV_TX_OFFLOAD_UDP_CKSUM |
1870 DEV_TX_OFFLOAD_TCP_CKSUM;
1872 if (feat.offload.rx_supported &
1873 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1874 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1875 DEV_RX_OFFLOAD_UDP_CKSUM |
1876 DEV_RX_OFFLOAD_TCP_CKSUM;
1878 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1880 /* Inform framework about available features */
1881 dev_info->rx_offload_capa = rx_feat;
1882 dev_info->rx_queue_offload_capa = rx_feat;
1883 dev_info->tx_offload_capa = tx_feat;
1884 dev_info->tx_queue_offload_capa = tx_feat;
1886 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1887 dev_info->max_rx_pktlen = adapter->max_mtu;
1888 dev_info->max_mac_addrs = 1;
1890 dev_info->max_rx_queues = adapter->num_queues;
1891 dev_info->max_tx_queues = adapter->num_queues;
1892 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1894 adapter->tx_supported_offloads = tx_feat;
1895 adapter->rx_supported_offloads = rx_feat;
1897 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1898 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1899 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1900 adapter->max_rx_sgl_size);
1901 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1902 adapter->max_rx_sgl_size);
1904 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
1905 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1906 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1907 adapter->max_tx_sgl_size);
1908 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1909 adapter->max_tx_sgl_size);
1912 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1915 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1916 unsigned int ring_size = rx_ring->ring_size;
1917 unsigned int ring_mask = ring_size - 1;
1918 uint16_t next_to_clean = rx_ring->next_to_clean;
1919 uint16_t desc_in_use = 0;
1921 unsigned int recv_idx = 0;
1922 struct rte_mbuf *mbuf = NULL;
1923 struct rte_mbuf *mbuf_head = NULL;
1924 struct rte_mbuf *mbuf_prev = NULL;
1925 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1926 unsigned int completed;
1928 struct ena_com_rx_ctx ena_rx_ctx;
1931 /* Check adapter state */
1932 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1934 "Trying to receive pkts while device is NOT running\n");
1938 desc_in_use = rx_ring->next_to_use - next_to_clean;
1939 if (unlikely(nb_pkts > desc_in_use))
1940 nb_pkts = desc_in_use;
1942 for (completed = 0; completed < nb_pkts; completed++) {
1945 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
1946 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1947 ena_rx_ctx.descs = 0;
1948 /* receive packet context */
1949 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1950 rx_ring->ena_com_io_sq,
1953 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1954 rx_ring->adapter->reset_reason =
1955 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1956 rx_ring->adapter->trigger_reset = true;
1960 if (unlikely(ena_rx_ctx.descs == 0))
1963 while (segments < ena_rx_ctx.descs) {
1964 req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1965 rc = validate_rx_req_id(rx_ring, req_id);
1969 mbuf = rx_buff_info[req_id];
1970 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1971 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1974 if (unlikely(segments == 0)) {
1975 mbuf->nb_segs = ena_rx_ctx.descs;
1976 mbuf->port = rx_ring->port_id;
1980 /* for multi-segment pkts create mbuf chain */
1981 mbuf_prev->next = mbuf;
1983 mbuf_head->pkt_len += mbuf->data_len;
1986 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1992 /* fill mbuf attributes if any */
1993 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1994 mbuf_head->hash.rss = ena_rx_ctx.hash;
1996 /* pass to DPDK application head mbuf */
1997 rx_pkts[recv_idx] = mbuf_head;
2001 rx_ring->next_to_clean = next_to_clean;
2003 desc_in_use = desc_in_use - completed + 1;
2004 /* Burst refill to save doorbells, memory barriers, const interval */
2005 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2006 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2012 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2018 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2019 struct ipv4_hdr *ip_hdr;
2021 uint16_t frag_field;
2023 for (i = 0; i != nb_pkts; i++) {
2025 ol_flags = m->ol_flags;
2027 if (!(ol_flags & PKT_TX_IPV4))
2030 /* If there was not L2 header length specified, assume it is
2031 * length of the ethernet header.
2033 if (unlikely(m->l2_len == 0))
2034 m->l2_len = sizeof(struct ether_hdr);
2036 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2038 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2040 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2041 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2043 /* If IPv4 header has DF flag enabled and TSO support is
2044 * disabled, partial chcecksum should not be calculated.
2046 if (!tx_ring->adapter->tso4_supported)
2050 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2051 (ol_flags & PKT_TX_L4_MASK) ==
2052 PKT_TX_SCTP_CKSUM) {
2053 rte_errno = -ENOTSUP;
2057 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2058 ret = rte_validate_tx_offload(m);
2065 /* In case we are supposed to TSO and have DF not set (DF=0)
2066 * hardware must be provided with partial checksum, otherwise
2067 * it will take care of necessary calculations.
2070 ret = rte_net_intel_cksum_flags_prepare(m,
2071 ol_flags & ~PKT_TX_TCP_SEG);
2081 static void ena_update_hints(struct ena_adapter *adapter,
2082 struct ena_admin_ena_hw_hints *hints)
2084 if (hints->admin_completion_tx_timeout)
2085 adapter->ena_dev.admin_queue.completion_timeout =
2086 hints->admin_completion_tx_timeout * 1000;
2088 if (hints->mmio_read_timeout)
2089 /* convert to usec */
2090 adapter->ena_dev.mmio_read.reg_read_to =
2091 hints->mmio_read_timeout * 1000;
2093 if (hints->driver_watchdog_timeout) {
2094 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2095 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2097 // Convert msecs to ticks
2098 adapter->keep_alive_timeout =
2099 (hints->driver_watchdog_timeout *
2100 rte_get_timer_hz()) / 1000;
2104 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2105 struct rte_mbuf *mbuf)
2107 int num_segments, rc;
2109 num_segments = mbuf->nb_segs;
2111 if (likely(num_segments < tx_ring->sgl_size))
2114 rc = rte_pktmbuf_linearize(mbuf);
2116 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2121 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2124 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2125 uint16_t next_to_use = tx_ring->next_to_use;
2126 uint16_t next_to_clean = tx_ring->next_to_clean;
2127 struct rte_mbuf *mbuf;
2128 unsigned int ring_size = tx_ring->ring_size;
2129 unsigned int ring_mask = ring_size - 1;
2130 struct ena_com_tx_ctx ena_tx_ctx;
2131 struct ena_tx_buffer *tx_info;
2132 struct ena_com_buf *ebuf;
2133 uint16_t rc, req_id, total_tx_descs = 0;
2134 uint16_t sent_idx = 0, empty_tx_reqs;
2137 /* Check adapter state */
2138 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2140 "Trying to xmit pkts while device is NOT running\n");
2144 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2145 if (nb_pkts > empty_tx_reqs)
2146 nb_pkts = empty_tx_reqs;
2148 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2149 mbuf = tx_pkts[sent_idx];
2151 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2155 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2156 tx_info = &tx_ring->tx_buffer_info[req_id];
2157 tx_info->mbuf = mbuf;
2158 tx_info->num_of_bufs = 0;
2159 ebuf = tx_info->bufs;
2161 /* Prepare TX context */
2162 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2163 memset(&ena_tx_ctx.ena_meta, 0x0,
2164 sizeof(struct ena_com_tx_meta));
2165 ena_tx_ctx.ena_bufs = ebuf;
2166 ena_tx_ctx.req_id = req_id;
2167 if (tx_ring->tx_mem_queue_type ==
2168 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2169 /* prepare the push buffer with
2170 * virtual address of the data
2172 ena_tx_ctx.header_len =
2173 RTE_MIN(mbuf->data_len,
2174 tx_ring->tx_max_header_size);
2175 ena_tx_ctx.push_header =
2176 (void *)((char *)mbuf->buf_addr +
2178 } /* there's no else as we take advantage of memset zeroing */
2180 /* Set TX offloads flags, if applicable */
2181 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2183 if (unlikely(mbuf->ol_flags &
2184 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2185 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2187 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2189 /* Process first segment taking into
2190 * consideration pushed header
2192 if (mbuf->data_len > ena_tx_ctx.header_len) {
2193 ebuf->paddr = mbuf->buf_iova +
2195 ena_tx_ctx.header_len;
2196 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2198 tx_info->num_of_bufs++;
2201 while ((mbuf = mbuf->next) != NULL) {
2202 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2203 ebuf->len = mbuf->data_len;
2205 tx_info->num_of_bufs++;
2208 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2210 /* Write data to device */
2211 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2212 &ena_tx_ctx, &nb_hw_desc);
2216 tx_info->tx_descs = nb_hw_desc;
2221 /* If there are ready packets to be xmitted... */
2223 /* ...let HW do its best :-) */
2225 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2227 tx_ring->next_to_use = next_to_use;
2230 /* Clear complete packets */
2231 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2232 rc = validate_tx_req_id(tx_ring, req_id);
2236 /* Get Tx info & store how many descs were processed */
2237 tx_info = &tx_ring->tx_buffer_info[req_id];
2238 total_tx_descs += tx_info->tx_descs;
2240 /* Free whole mbuf chain */
2241 mbuf = tx_info->mbuf;
2242 rte_pktmbuf_free(mbuf);
2243 tx_info->mbuf = NULL;
2245 /* Put back descriptor to the ring for reuse */
2246 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2249 /* If too many descs to clean, leave it for another run */
2250 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2254 if (total_tx_descs > 0) {
2255 /* acknowledge completion of sent packets */
2256 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2257 tx_ring->next_to_clean = next_to_clean;
2263 /*********************************************************************
2265 *********************************************************************/
2266 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2267 struct rte_pci_device *pci_dev)
2269 return rte_eth_dev_pci_generic_probe(pci_dev,
2270 sizeof(struct ena_adapter), eth_ena_dev_init);
2273 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2275 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2278 static struct rte_pci_driver rte_ena_pmd = {
2279 .id_table = pci_id_ena_map,
2280 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2281 RTE_PCI_DRV_WC_ACTIVATE,
2282 .probe = eth_ena_pci_probe,
2283 .remove = eth_ena_pci_remove,
2286 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2287 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2288 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2290 RTE_INIT(ena_init_log)
2292 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2293 if (ena_logtype_init >= 0)
2294 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2295 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2296 if (ena_logtype_driver >= 0)
2297 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2300 /******************************************************************************
2301 ******************************** AENQ Handlers *******************************
2302 *****************************************************************************/
2303 static void ena_update_on_link_change(void *adapter_data,
2304 struct ena_admin_aenq_entry *aenq_e)
2306 struct rte_eth_dev *eth_dev;
2307 struct ena_adapter *adapter;
2308 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2311 adapter = (struct ena_adapter *)adapter_data;
2312 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2313 eth_dev = adapter->rte_dev;
2315 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2316 adapter->link_status = status;
2318 ena_link_update(eth_dev, 0);
2319 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2322 static void ena_notification(void *data,
2323 struct ena_admin_aenq_entry *aenq_e)
2325 struct ena_adapter *adapter = (struct ena_adapter *)data;
2326 struct ena_admin_ena_hw_hints *hints;
2328 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2329 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2330 aenq_e->aenq_common_desc.group,
2331 ENA_ADMIN_NOTIFICATION);
2333 switch (aenq_e->aenq_common_desc.syndrom) {
2334 case ENA_ADMIN_UPDATE_HINTS:
2335 hints = (struct ena_admin_ena_hw_hints *)
2336 (&aenq_e->inline_data_w4);
2337 ena_update_hints(adapter, hints);
2340 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2341 aenq_e->aenq_common_desc.syndrom);
2345 static void ena_keep_alive(void *adapter_data,
2346 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2348 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2350 adapter->timestamp_wd = rte_get_timer_cycles();
2354 * This handler will called for unknown event group or unimplemented handlers
2356 static void unimplemented_aenq_handler(__rte_unused void *data,
2357 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2359 RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2360 "unimplemented handler\n");
2363 static struct ena_aenq_handlers aenq_handlers = {
2365 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2366 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2367 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2369 .unimplemented_handler = unimplemented_aenq_handler