drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    5
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 struct ena_stats {
  42         char name[ETH_GSTRING_LEN];
  43         int stat_offset;
  44 };
  45
  46 #define ENA_STAT_ENTRY(stat, stat_type) { \
  47         .name = #stat, \
  48         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  49 }
  50
  51 #define ENA_STAT_RX_ENTRY(stat) \
  52         ENA_STAT_ENTRY(stat, rx)
  53
  54 #define ENA_STAT_TX_ENTRY(stat) \
  55         ENA_STAT_ENTRY(stat, tx)
  56
  57 #define ENA_STAT_ENI_ENTRY(stat) \
  58         ENA_STAT_ENTRY(stat, eni)
  59
  60 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  61         ENA_STAT_ENTRY(stat, dev)
  62
  63 /* Device arguments */
  64 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  65
  66 /*
  67  * Each rte_memzone should have unique name.
  68  * To satisfy it, count number of allocation and add it to name.
  69  */
  70 rte_atomic64_t ena_alloc_cnt;
  71
  72 static const struct ena_stats ena_stats_global_strings[] = {
  73         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  74         ENA_STAT_GLOBAL_ENTRY(dev_start),
  75         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  76         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  77 };
  78
  79 static const struct ena_stats ena_stats_eni_strings[] = {
  80         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  81         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  82         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  83         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  84         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  85 };
  86
  87 static const struct ena_stats ena_stats_tx_strings[] = {
  88         ENA_STAT_TX_ENTRY(cnt),
  89         ENA_STAT_TX_ENTRY(bytes),
  90         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  91         ENA_STAT_TX_ENTRY(tx_poll),
  92         ENA_STAT_TX_ENTRY(doorbells),
  93         ENA_STAT_TX_ENTRY(bad_req_id),
  94         ENA_STAT_TX_ENTRY(available_desc),
  95         ENA_STAT_TX_ENTRY(missed_tx),
  96 };
  97
  98 static const struct ena_stats ena_stats_rx_strings[] = {
  99         ENA_STAT_RX_ENTRY(cnt),
 100         ENA_STAT_RX_ENTRY(bytes),
 101         ENA_STAT_RX_ENTRY(refill_partial),
 102         ENA_STAT_RX_ENTRY(bad_csum),
 103         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 104         ENA_STAT_RX_ENTRY(bad_desc_num),
 105         ENA_STAT_RX_ENTRY(bad_req_id),
 106 };
 107
 108 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 109 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 110 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 111 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 112
 113 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
 114                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
 115                         RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
 116                         RTE_ETH_TX_OFFLOAD_TCP_TSO)
 117 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
 118                        RTE_MBUF_F_TX_IP_CKSUM |\
 119                        RTE_MBUF_F_TX_TCP_SEG)
 120
 121 /** Vendor ID used by Amazon devices */
 122 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 123 /** Amazon devices */
 124 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 125 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 126
 127 #define ENA_TX_OFFLOAD_MASK     (RTE_MBUF_F_TX_L4_MASK |         \
 128         RTE_MBUF_F_TX_IPV6 |            \
 129         RTE_MBUF_F_TX_IPV4 |            \
 130         RTE_MBUF_F_TX_IP_CKSUM |        \
 131         RTE_MBUF_F_TX_TCP_SEG)
 132
 133 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 134         (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 135
 136 /** HW specific offloads capabilities. */
 137 /* IPv4 checksum offload. */
 138 #define ENA_L3_IPV4_CSUM                0x0001
 139 /* TCP/UDP checksum offload for IPv4 packets. */
 140 #define ENA_L4_IPV4_CSUM                0x0002
 141 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 142 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 143 /* TCP/UDP checksum offload for IPv6 packets. */
 144 #define ENA_L4_IPV6_CSUM                0x0008
 145 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 146 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 147 /* TSO support for IPv4 packets. */
 148 #define ENA_IPV4_TSO                    0x0020
 149
 150 /* Device supports setting RSS hash. */
 151 #define ENA_RX_RSS_HASH                 0x0040
 152
 153 static const struct rte_pci_id pci_id_ena_map[] = {
 154         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 155         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 156         { .device_id = 0 },
 157 };
 158
 159 static struct ena_aenq_handlers aenq_handlers;
 160
 161 static int ena_device_init(struct ena_com_dev *ena_dev,
 162                            struct rte_pci_device *pdev,
 163                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 164                            bool *wd_state);
 165 static int ena_dev_configure(struct rte_eth_dev *dev);
 166 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 167         struct ena_tx_buffer *tx_info,
 168         struct rte_mbuf *mbuf,
 169         void **push_header,
 170         uint16_t *header_len);
 171 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 172 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 173 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 174                                   uint16_t nb_pkts);
 175 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 176                 uint16_t nb_pkts);
 177 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 178                               uint16_t nb_desc, unsigned int socket_id,
 179                               const struct rte_eth_txconf *tx_conf);
 180 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 181                               uint16_t nb_desc, unsigned int socket_id,
 182                               const struct rte_eth_rxconf *rx_conf,
 183                               struct rte_mempool *mp);
 184 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 185 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 186                                     struct ena_com_rx_buf_info *ena_bufs,
 187                                     uint32_t descs,
 188                                     uint16_t *next_to_clean,
 189                                     uint8_t offset);
 190 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 191                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 192 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 193                                   struct rte_mbuf *mbuf, uint16_t id);
 194 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 195 static void ena_init_rings(struct ena_adapter *adapter,
 196                            bool disable_meta_caching);
 197 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 198 static int ena_start(struct rte_eth_dev *dev);
 199 static int ena_stop(struct rte_eth_dev *dev);
 200 static int ena_close(struct rte_eth_dev *dev);
 201 static int ena_dev_reset(struct rte_eth_dev *dev);
 202 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 203 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 204 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 205 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 206 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 207 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 208 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 209 static int ena_link_update(struct rte_eth_dev *dev,
 210                            int wait_to_complete);
 211 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 212 static void ena_queue_stop(struct ena_ring *ring);
 213 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 214                               enum ena_ring_type ring_type);
 215 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 216 static int ena_queue_start_all(struct rte_eth_dev *dev,
 217                                enum ena_ring_type ring_type);
 218 static void ena_stats_restart(struct rte_eth_dev *dev);
 219 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
 220 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
 221 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
 222 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
 223 static int ena_infos_get(struct rte_eth_dev *dev,
 224                          struct rte_eth_dev_info *dev_info);
 225 static void ena_interrupt_handler_rte(void *cb_arg);
 226 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 227 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 228 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 229 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 230                                 struct rte_eth_xstat_name *xstats_names,
 231                                 unsigned int n);
 232 static int ena_xstats_get(struct rte_eth_dev *dev,
 233                           struct rte_eth_xstat *stats,
 234                           unsigned int n);
 235 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 236                                 const uint64_t *ids,
 237                                 uint64_t *values,
 238                                 unsigned int n);
 239 static int ena_process_bool_devarg(const char *key,
 240                                    const char *value,
 241                                    void *opaque);
 242 static int ena_parse_devargs(struct ena_adapter *adapter,
 243                              struct rte_devargs *devargs);
 244 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 245 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 246 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 247                                     uint16_t queue_id);
 248 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 249                                      uint16_t queue_id);
 250
 251 static const struct eth_dev_ops ena_dev_ops = {
 252         .dev_configure        = ena_dev_configure,
 253         .dev_infos_get        = ena_infos_get,
 254         .rx_queue_setup       = ena_rx_queue_setup,
 255         .tx_queue_setup       = ena_tx_queue_setup,
 256         .dev_start            = ena_start,
 257         .dev_stop             = ena_stop,
 258         .link_update          = ena_link_update,
 259         .stats_get            = ena_stats_get,
 260         .xstats_get_names     = ena_xstats_get_names,
 261         .xstats_get           = ena_xstats_get,
 262         .xstats_get_by_id     = ena_xstats_get_by_id,
 263         .mtu_set              = ena_mtu_set,
 264         .rx_queue_release     = ena_rx_queue_release,
 265         .tx_queue_release     = ena_tx_queue_release,
 266         .dev_close            = ena_close,
 267         .dev_reset            = ena_dev_reset,
 268         .reta_update          = ena_rss_reta_update,
 269         .reta_query           = ena_rss_reta_query,
 270         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 271         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 272         .rss_hash_update      = ena_rss_hash_update,
 273         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 274 };
 275
 276 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 277                                        struct ena_com_rx_ctx *ena_rx_ctx,
 278                                        bool fill_hash)
 279 {
 280         uint64_t ol_flags = 0;
 281         uint32_t packet_type = 0;
 282
 283         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 284                 packet_type |= RTE_PTYPE_L4_TCP;
 285         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 286                 packet_type |= RTE_PTYPE_L4_UDP;
 287
 288         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 289                 packet_type |= RTE_PTYPE_L3_IPV4;
 290                 if (unlikely(ena_rx_ctx->l3_csum_err))
 291                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 292                 else
 293                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 294         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 295                 packet_type |= RTE_PTYPE_L3_IPV6;
 296         }
 297
 298         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 299                 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
 300         else
 301                 if (unlikely(ena_rx_ctx->l4_csum_err))
 302                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 303                 else
 304                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 305
 306         if (fill_hash &&
 307             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 308                 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 309                 mbuf->hash.rss = ena_rx_ctx->hash;
 310         }
 311
 312         mbuf->ol_flags = ol_flags;
 313         mbuf->packet_type = packet_type;
 314 }
 315
 316 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 317                                        struct ena_com_tx_ctx *ena_tx_ctx,
 318                                        uint64_t queue_offloads,
 319                                        bool disable_meta_caching)
 320 {
 321         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 322
 323         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 324             (queue_offloads & QUEUE_OFFLOADS)) {
 325                 /* check if TSO is required */
 326                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
 327                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
 328                         ena_tx_ctx->tso_enable = true;
 329
 330                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 331                 }
 332
 333                 /* check if L3 checksum is needed */
 334                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
 335                     (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
 336                         ena_tx_ctx->l3_csum_enable = true;
 337
 338                 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
 339                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 340                 } else {
 341                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 342
 343                         /* set don't fragment (DF) flag */
 344                         if (mbuf->packet_type &
 345                                 (RTE_PTYPE_L4_NONFRAG
 346                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 347                                 ena_tx_ctx->df = true;
 348                 }
 349
 350                 /* check if L4 checksum is needed */
 351                 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
 352                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 354                         ena_tx_ctx->l4_csum_enable = true;
 355                 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
 356                                 RTE_MBUF_F_TX_UDP_CKSUM) &&
 357                                 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
 358                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 359                         ena_tx_ctx->l4_csum_enable = true;
 360                 } else {
 361                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 362                         ena_tx_ctx->l4_csum_enable = false;
 363                 }
 364
 365                 ena_meta->mss = mbuf->tso_segsz;
 366                 ena_meta->l3_hdr_len = mbuf->l3_len;
 367                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 368
 369                 ena_tx_ctx->meta_valid = true;
 370         } else if (disable_meta_caching) {
 371                 memset(ena_meta, 0, sizeof(*ena_meta));
 372                 ena_tx_ctx->meta_valid = true;
 373         } else {
 374                 ena_tx_ctx->meta_valid = false;
 375         }
 376 }
 377
 378 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 379 {
 380         struct ena_tx_buffer *tx_info = NULL;
 381
 382         if (likely(req_id < tx_ring->ring_size)) {
 383                 tx_info = &tx_ring->tx_buffer_info[req_id];
 384                 if (likely(tx_info->mbuf))
 385                         return 0;
 386         }
 387
 388         if (tx_info)
 389                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 390         else
 391                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 392
 393         /* Trigger device reset */
 394         ++tx_ring->tx_stats.bad_req_id;
 395         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 396         tx_ring->adapter->trigger_reset = true;
 397         return -EFAULT;
 398 }
 399
 400 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 401 {
 402         struct ena_admin_host_info *host_info;
 403         int rc;
 404
 405         /* Allocate only the host info */
 406         rc = ena_com_allocate_host_info(ena_dev);
 407         if (rc) {
 408                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 409                 return;
 410         }
 411
 412         host_info = ena_dev->host_attr.host_info;
 413
 414         host_info->os_type = ENA_ADMIN_OS_DPDK;
 415         host_info->kernel_ver = RTE_VERSION;
 416         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 417                 sizeof(host_info->kernel_ver_str));
 418         host_info->os_dist = RTE_VERSION;
 419         strlcpy((char *)host_info->os_dist_str, rte_version(),
 420                 sizeof(host_info->os_dist_str));
 421         host_info->driver_version =
 422                 (DRV_MODULE_VER_MAJOR) |
 423                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 424                 (DRV_MODULE_VER_SUBMINOR <<
 425                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 426         host_info->num_cpus = rte_lcore_count();
 427
 428         host_info->driver_supported_features =
 429                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 430                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 431
 432         rc = ena_com_set_host_attributes(ena_dev);
 433         if (rc) {
 434                 if (rc == -ENA_COM_UNSUPPORTED)
 435                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 436                 else
 437                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 438
 439                 goto err;
 440         }
 441
 442         return;
 443
 444 err:
 445         ena_com_delete_host_info(ena_dev);
 446 }
 447
 448 /* This function calculates the number of xstats based on the current config */
 449 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 450 {
 451         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 452                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 453                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 454 }
 455
 456 static void ena_config_debug_area(struct ena_adapter *adapter)
 457 {
 458         u32 debug_area_size;
 459         int rc, ss_count;
 460
 461         ss_count = ena_xstats_calc_num(adapter->edev_data);
 462
 463         /* allocate 32 bytes for each string and 64bit for the value */
 464         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 465
 466         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 467         if (rc) {
 468                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 469                 return;
 470         }
 471
 472         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 473         if (rc) {
 474                 if (rc == -ENA_COM_UNSUPPORTED)
 475                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 476                 else
 477                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 478
 479                 goto err;
 480         }
 481
 482         return;
 483 err:
 484         ena_com_delete_debug_area(&adapter->ena_dev);
 485 }
 486
 487 static int ena_close(struct rte_eth_dev *dev)
 488 {
 489         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 490         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 491         struct ena_adapter *adapter = dev->data->dev_private;
 492         int ret = 0;
 493
 494         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 495                 return 0;
 496
 497         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 498                 ret = ena_stop(dev);
 499         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 500
 501         ena_rx_queue_release_all(dev);
 502         ena_tx_queue_release_all(dev);
 503
 504         rte_free(adapter->drv_stats);
 505         adapter->drv_stats = NULL;
 506
 507         rte_intr_disable(intr_handle);
 508         rte_intr_callback_unregister(intr_handle,
 509                                      ena_interrupt_handler_rte,
 510                                      dev);
 511
 512         /*
 513          * MAC is not allocated dynamically. Setting NULL should prevent from
 514          * release of the resource in the rte_eth_dev_release_port().
 515          */
 516         dev->data->mac_addrs = NULL;
 517
 518         return ret;
 519 }
 520
 521 static int
 522 ena_dev_reset(struct rte_eth_dev *dev)
 523 {
 524         int rc = 0;
 525
 526         /* Cannot release memory in secondary process */
 527         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 528                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 529                 return -EPERM;
 530         }
 531
 532         ena_destroy_device(dev);
 533         rc = eth_ena_dev_init(dev);
 534         if (rc)
 535                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 536
 537         return rc;
 538 }
 539
 540 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 541 {
 542         int nb_queues = dev->data->nb_rx_queues;
 543         int i;
 544
 545         for (i = 0; i < nb_queues; i++)
 546                 ena_rx_queue_release(dev, i);
 547 }
 548
 549 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 550 {
 551         int nb_queues = dev->data->nb_tx_queues;
 552         int i;
 553
 554         for (i = 0; i < nb_queues; i++)
 555                 ena_tx_queue_release(dev, i);
 556 }
 557
 558 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 559 {
 560         struct ena_ring *ring = dev->data->rx_queues[qid];
 561
 562         /* Free ring resources */
 563         rte_free(ring->rx_buffer_info);
 564         ring->rx_buffer_info = NULL;
 565
 566         rte_free(ring->rx_refill_buffer);
 567         ring->rx_refill_buffer = NULL;
 568
 569         rte_free(ring->empty_rx_reqs);
 570         ring->empty_rx_reqs = NULL;
 571
 572         ring->configured = 0;
 573
 574         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 575                 ring->port_id, ring->id);
 576 }
 577
 578 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 579 {
 580         struct ena_ring *ring = dev->data->tx_queues[qid];
 581
 582         /* Free ring resources */
 583         rte_free(ring->push_buf_intermediate_buf);
 584
 585         rte_free(ring->tx_buffer_info);
 586
 587         rte_free(ring->empty_tx_reqs);
 588
 589         ring->empty_tx_reqs = NULL;
 590         ring->tx_buffer_info = NULL;
 591         ring->push_buf_intermediate_buf = NULL;
 592
 593         ring->configured = 0;
 594
 595         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 596                 ring->port_id, ring->id);
 597 }
 598
 599 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 600 {
 601         unsigned int i;
 602
 603         for (i = 0; i < ring->ring_size; ++i) {
 604                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 605                 if (rx_info->mbuf) {
 606                         rte_mbuf_raw_free(rx_info->mbuf);
 607                         rx_info->mbuf = NULL;
 608                 }
 609         }
 610 }
 611
 612 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 613 {
 614         unsigned int i;
 615
 616         for (i = 0; i < ring->ring_size; ++i) {
 617                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 618
 619                 if (tx_buf->mbuf) {
 620                         rte_pktmbuf_free(tx_buf->mbuf);
 621                         tx_buf->mbuf = NULL;
 622                 }
 623         }
 624 }
 625
 626 static int ena_link_update(struct rte_eth_dev *dev,
 627                            __rte_unused int wait_to_complete)
 628 {
 629         struct rte_eth_link *link = &dev->data->dev_link;
 630         struct ena_adapter *adapter = dev->data->dev_private;
 631
 632         link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
 633         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
 634         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 635
 636         return 0;
 637 }
 638
 639 static int ena_queue_start_all(struct rte_eth_dev *dev,
 640                                enum ena_ring_type ring_type)
 641 {
 642         struct ena_adapter *adapter = dev->data->dev_private;
 643         struct ena_ring *queues = NULL;
 644         int nb_queues;
 645         int i = 0;
 646         int rc = 0;
 647
 648         if (ring_type == ENA_RING_TYPE_RX) {
 649                 queues = adapter->rx_ring;
 650                 nb_queues = dev->data->nb_rx_queues;
 651         } else {
 652                 queues = adapter->tx_ring;
 653                 nb_queues = dev->data->nb_tx_queues;
 654         }
 655         for (i = 0; i < nb_queues; i++) {
 656                 if (queues[i].configured) {
 657                         if (ring_type == ENA_RING_TYPE_RX) {
 658                                 ena_assert_msg(
 659                                         dev->data->rx_queues[i] == &queues[i],
 660                                         "Inconsistent state of Rx queues\n");
 661                         } else {
 662                                 ena_assert_msg(
 663                                         dev->data->tx_queues[i] == &queues[i],
 664                                         "Inconsistent state of Tx queues\n");
 665                         }
 666
 667                         rc = ena_queue_start(dev, &queues[i]);
 668
 669                         if (rc) {
 670                                 PMD_INIT_LOG(ERR,
 671                                         "Failed to start queue[%d] of type(%d)\n",
 672                                         i, ring_type);
 673                                 goto err;
 674                         }
 675                 }
 676         }
 677
 678         return 0;
 679
 680 err:
 681         while (i--)
 682                 if (queues[i].configured)
 683                         ena_queue_stop(&queues[i]);
 684
 685         return rc;
 686 }
 687
 688 static int ena_check_valid_conf(struct ena_adapter *adapter)
 689 {
 690         uint32_t mtu = adapter->edev_data->mtu;
 691
 692         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 693                 PMD_INIT_LOG(ERR,
 694                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 695                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 696                 return ENA_COM_UNSUPPORTED;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int
 703 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 704                        bool use_large_llq_hdr)
 705 {
 706         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 707         struct ena_com_dev *ena_dev = ctx->ena_dev;
 708         uint32_t max_tx_queue_size;
 709         uint32_t max_rx_queue_size;
 710
 711         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 712                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 713                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 714                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 715                         max_queue_ext->max_rx_sq_depth);
 716                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 717
 718                 if (ena_dev->tx_mem_queue_type ==
 719                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 720                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 721                                 llq->max_llq_depth);
 722                 } else {
 723                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 724                                 max_queue_ext->max_tx_sq_depth);
 725                 }
 726
 727                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 728                         max_queue_ext->max_per_packet_rx_descs);
 729                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 730                         max_queue_ext->max_per_packet_tx_descs);
 731         } else {
 732                 struct ena_admin_queue_feature_desc *max_queues =
 733                         &ctx->get_feat_ctx->max_queues;
 734                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 735                         max_queues->max_sq_depth);
 736                 max_tx_queue_size = max_queues->max_cq_depth;
 737
 738                 if (ena_dev->tx_mem_queue_type ==
 739                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 740                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 741                                 llq->max_llq_depth);
 742                 } else {
 743                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 744                                 max_queues->max_sq_depth);
 745                 }
 746
 747                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 748                         max_queues->max_packet_rx_descs);
 749                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 750                         max_queues->max_packet_tx_descs);
 751         }
 752
 753         /* Round down to the nearest power of 2 */
 754         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 755         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 756
 757         if (use_large_llq_hdr) {
 758                 if ((llq->entry_size_ctrl_supported &
 759                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 760                     (ena_dev->tx_mem_queue_type ==
 761                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 762                         max_tx_queue_size /= 2;
 763                         PMD_INIT_LOG(INFO,
 764                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
 765                                 max_tx_queue_size);
 766                 } else {
 767                         PMD_INIT_LOG(ERR,
 768                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 769                 }
 770         }
 771
 772         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 773                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 774                 return -EFAULT;
 775         }
 776
 777         ctx->max_tx_queue_size = max_tx_queue_size;
 778         ctx->max_rx_queue_size = max_rx_queue_size;
 779
 780         return 0;
 781 }
 782
 783 static void ena_stats_restart(struct rte_eth_dev *dev)
 784 {
 785         struct ena_adapter *adapter = dev->data->dev_private;
 786
 787         rte_atomic64_init(&adapter->drv_stats->ierrors);
 788         rte_atomic64_init(&adapter->drv_stats->oerrors);
 789         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 790         adapter->drv_stats->rx_drops = 0;
 791 }
 792
 793 static int ena_stats_get(struct rte_eth_dev *dev,
 794                           struct rte_eth_stats *stats)
 795 {
 796         struct ena_admin_basic_stats ena_stats;
 797         struct ena_adapter *adapter = dev->data->dev_private;
 798         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 799         int rc;
 800         int i;
 801         int max_rings_stats;
 802
 803         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 804                 return -ENOTSUP;
 805
 806         memset(&ena_stats, 0, sizeof(ena_stats));
 807
 808         rte_spinlock_lock(&adapter->admin_lock);
 809         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 810         rte_spinlock_unlock(&adapter->admin_lock);
 811         if (unlikely(rc)) {
 812                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 813                 return rc;
 814         }
 815
 816         /* Set of basic statistics from ENA */
 817         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 818                                           ena_stats.rx_pkts_low);
 819         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 820                                           ena_stats.tx_pkts_low);
 821         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 822                                         ena_stats.rx_bytes_low);
 823         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 824                                         ena_stats.tx_bytes_low);
 825
 826         /* Driver related stats */
 827         stats->imissed = adapter->drv_stats->rx_drops;
 828         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 829         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 830         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 831
 832         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 833                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 834         for (i = 0; i < max_rings_stats; ++i) {
 835                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 836
 837                 stats->q_ibytes[i] = rx_stats->bytes;
 838                 stats->q_ipackets[i] = rx_stats->cnt;
 839                 stats->q_errors[i] = rx_stats->bad_desc_num +
 840                         rx_stats->bad_req_id;
 841         }
 842
 843         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 844                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 845         for (i = 0; i < max_rings_stats; ++i) {
 846                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 847
 848                 stats->q_obytes[i] = tx_stats->bytes;
 849                 stats->q_opackets[i] = tx_stats->cnt;
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 856 {
 857         struct ena_adapter *adapter;
 858         struct ena_com_dev *ena_dev;
 859         int rc = 0;
 860
 861         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 862         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 863         adapter = dev->data->dev_private;
 864
 865         ena_dev = &adapter->ena_dev;
 866         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 867
 868         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 869                 PMD_DRV_LOG(ERR,
 870                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
 871                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 872                 return -EINVAL;
 873         }
 874
 875         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 876         if (rc)
 877                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 878         else
 879                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
 880
 881         return rc;
 882 }
 883
 884 static int ena_start(struct rte_eth_dev *dev)
 885 {
 886         struct ena_adapter *adapter = dev->data->dev_private;
 887         uint64_t ticks;
 888         int rc = 0;
 889
 890         /* Cannot allocate memory in secondary process */
 891         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 892                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
 893                 return -EPERM;
 894         }
 895
 896         rc = ena_check_valid_conf(adapter);
 897         if (rc)
 898                 return rc;
 899
 900         rc = ena_setup_rx_intr(dev);
 901         if (rc)
 902                 return rc;
 903
 904         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
 905         if (rc)
 906                 return rc;
 907
 908         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
 909         if (rc)
 910                 goto err_start_tx;
 911
 912         if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 913                 rc = ena_rss_configure(adapter);
 914                 if (rc)
 915                         goto err_rss_init;
 916         }
 917
 918         ena_stats_restart(dev);
 919
 920         adapter->timestamp_wd = rte_get_timer_cycles();
 921         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
 922
 923         ticks = rte_get_timer_hz();
 924         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
 925                         ena_timer_wd_callback, dev);
 926
 927         ++adapter->dev_stats.dev_start;
 928         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 929
 930         return 0;
 931
 932 err_rss_init:
 933         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 934 err_start_tx:
 935         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 936         return rc;
 937 }
 938
 939 static int ena_stop(struct rte_eth_dev *dev)
 940 {
 941         struct ena_adapter *adapter = dev->data->dev_private;
 942         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 943         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 944         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 945         int rc;
 946
 947         /* Cannot free memory in secondary process */
 948         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 949                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
 950                 return -EPERM;
 951         }
 952
 953         rte_timer_stop_sync(&adapter->timer_wd);
 954         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 955         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 956
 957         if (adapter->trigger_reset) {
 958                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 959                 if (rc)
 960                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
 961         }
 962
 963         rte_intr_disable(intr_handle);
 964
 965         rte_intr_efd_disable(intr_handle);
 966
 967         /* Cleanup vector list */
 968         rte_intr_vec_list_free(intr_handle);
 969
 970         rte_intr_enable(intr_handle);
 971
 972         ++adapter->dev_stats.dev_stop;
 973         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 974         dev->data->dev_started = 0;
 975
 976         return 0;
 977 }
 978
 979 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
 980 {
 981         struct ena_adapter *adapter = ring->adapter;
 982         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 983         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 984         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 985         struct ena_com_create_io_ctx ctx =
 986                 /* policy set to _HOST just to satisfy icc compiler */
 987                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 988                   0, 0, 0, 0, 0 };
 989         uint16_t ena_qid;
 990         unsigned int i;
 991         int rc;
 992
 993         ctx.msix_vector = -1;
 994         if (ring->type == ENA_RING_TYPE_TX) {
 995                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
 996                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 997                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 998                 for (i = 0; i < ring->ring_size; i++)
 999                         ring->empty_tx_reqs[i] = i;
1000         } else {
1001                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1002                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1003                 if (rte_intr_dp_is_en(intr_handle))
1004                         ctx.msix_vector =
1005                                 rte_intr_vec_list_index_get(intr_handle,
1006                                                                    ring->id);
1007
1008                 for (i = 0; i < ring->ring_size; i++)
1009                         ring->empty_rx_reqs[i] = i;
1010         }
1011         ctx.queue_size = ring->ring_size;
1012         ctx.qid = ena_qid;
1013         ctx.numa_node = ring->numa_socket_id;
1014
1015         rc = ena_com_create_io_queue(ena_dev, &ctx);
1016         if (rc) {
1017                 PMD_DRV_LOG(ERR,
1018                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1019                         ring->id, ena_qid, rc);
1020                 return rc;
1021         }
1022
1023         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1024                                      &ring->ena_com_io_sq,
1025                                      &ring->ena_com_io_cq);
1026         if (rc) {
1027                 PMD_DRV_LOG(ERR,
1028                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1029                         ring->id, rc);
1030                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1031                 return rc;
1032         }
1033
1034         if (ring->type == ENA_RING_TYPE_TX)
1035                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1036
1037         /* Start with Rx interrupts being masked. */
1038         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1039                 ena_rx_queue_intr_disable(dev, ring->id);
1040
1041         return 0;
1042 }
1043
1044 static void ena_queue_stop(struct ena_ring *ring)
1045 {
1046         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1047
1048         if (ring->type == ENA_RING_TYPE_RX) {
1049                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1050                 ena_rx_queue_release_bufs(ring);
1051         } else {
1052                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1053                 ena_tx_queue_release_bufs(ring);
1054         }
1055 }
1056
1057 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1058                               enum ena_ring_type ring_type)
1059 {
1060         struct ena_adapter *adapter = dev->data->dev_private;
1061         struct ena_ring *queues = NULL;
1062         uint16_t nb_queues, i;
1063
1064         if (ring_type == ENA_RING_TYPE_RX) {
1065                 queues = adapter->rx_ring;
1066                 nb_queues = dev->data->nb_rx_queues;
1067         } else {
1068                 queues = adapter->tx_ring;
1069                 nb_queues = dev->data->nb_tx_queues;
1070         }
1071
1072         for (i = 0; i < nb_queues; ++i)
1073                 if (queues[i].configured)
1074                         ena_queue_stop(&queues[i]);
1075 }
1076
1077 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1078 {
1079         int rc, bufs_num;
1080
1081         ena_assert_msg(ring->configured == 1,
1082                        "Trying to start unconfigured queue\n");
1083
1084         rc = ena_create_io_queue(dev, ring);
1085         if (rc) {
1086                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1087                 return rc;
1088         }
1089
1090         ring->next_to_clean = 0;
1091         ring->next_to_use = 0;
1092
1093         if (ring->type == ENA_RING_TYPE_TX) {
1094                 ring->tx_stats.available_desc =
1095                         ena_com_free_q_entries(ring->ena_com_io_sq);
1096                 return 0;
1097         }
1098
1099         bufs_num = ring->ring_size - 1;
1100         rc = ena_populate_rx_queue(ring, bufs_num);
1101         if (rc != bufs_num) {
1102                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1103                                          ENA_IO_RXQ_IDX(ring->id));
1104                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1105                 return ENA_COM_FAULT;
1106         }
1107         /* Flush per-core RX buffers pools cache as they can be used on other
1108          * cores as well.
1109          */
1110         rte_mempool_cache_flush(NULL, ring->mb_pool);
1111
1112         return 0;
1113 }
1114
1115 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1116                               uint16_t queue_idx,
1117                               uint16_t nb_desc,
1118                               unsigned int socket_id,
1119                               const struct rte_eth_txconf *tx_conf)
1120 {
1121         struct ena_ring *txq = NULL;
1122         struct ena_adapter *adapter = dev->data->dev_private;
1123         unsigned int i;
1124         uint16_t dyn_thresh;
1125
1126         txq = &adapter->tx_ring[queue_idx];
1127
1128         if (txq->configured) {
1129                 PMD_DRV_LOG(CRIT,
1130                         "API violation. Queue[%d] is already configured\n",
1131                         queue_idx);
1132                 return ENA_COM_FAULT;
1133         }
1134
1135         if (!rte_is_power_of_2(nb_desc)) {
1136                 PMD_DRV_LOG(ERR,
1137                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1138                         nb_desc);
1139                 return -EINVAL;
1140         }
1141
1142         if (nb_desc > adapter->max_tx_ring_size) {
1143                 PMD_DRV_LOG(ERR,
1144                         "Unsupported size of Tx queue (max size: %d)\n",
1145                         adapter->max_tx_ring_size);
1146                 return -EINVAL;
1147         }
1148
1149         txq->port_id = dev->data->port_id;
1150         txq->next_to_clean = 0;
1151         txq->next_to_use = 0;
1152         txq->ring_size = nb_desc;
1153         txq->size_mask = nb_desc - 1;
1154         txq->numa_socket_id = socket_id;
1155         txq->pkts_without_db = false;
1156         txq->last_cleanup_ticks = 0;
1157
1158         txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1159                 sizeof(struct ena_tx_buffer) * txq->ring_size,
1160                 RTE_CACHE_LINE_SIZE,
1161                 socket_id);
1162         if (!txq->tx_buffer_info) {
1163                 PMD_DRV_LOG(ERR,
1164                         "Failed to allocate memory for Tx buffer info\n");
1165                 return -ENOMEM;
1166         }
1167
1168         txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1169                 sizeof(uint16_t) * txq->ring_size,
1170                 RTE_CACHE_LINE_SIZE,
1171                 socket_id);
1172         if (!txq->empty_tx_reqs) {
1173                 PMD_DRV_LOG(ERR,
1174                         "Failed to allocate memory for empty Tx requests\n");
1175                 rte_free(txq->tx_buffer_info);
1176                 return -ENOMEM;
1177         }
1178
1179         txq->push_buf_intermediate_buf =
1180                 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1181                         txq->tx_max_header_size,
1182                         RTE_CACHE_LINE_SIZE,
1183                         socket_id);
1184         if (!txq->push_buf_intermediate_buf) {
1185                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1186                 rte_free(txq->tx_buffer_info);
1187                 rte_free(txq->empty_tx_reqs);
1188                 return -ENOMEM;
1189         }
1190
1191         for (i = 0; i < txq->ring_size; i++)
1192                 txq->empty_tx_reqs[i] = i;
1193
1194         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1195
1196         /* Check if caller provided the Tx cleanup threshold value. */
1197         if (tx_conf->tx_free_thresh != 0) {
1198                 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1199         } else {
1200                 dyn_thresh = txq->ring_size -
1201                         txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1202                 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1203                         txq->ring_size - ENA_REFILL_THRESH_PACKET);
1204         }
1205
1206         txq->missing_tx_completion_threshold =
1207                 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1208
1209         /* Store pointer to this queue in upper layer */
1210         txq->configured = 1;
1211         dev->data->tx_queues[queue_idx] = txq;
1212
1213         return 0;
1214 }
1215
1216 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1217                               uint16_t queue_idx,
1218                               uint16_t nb_desc,
1219                               unsigned int socket_id,
1220                               const struct rte_eth_rxconf *rx_conf,
1221                               struct rte_mempool *mp)
1222 {
1223         struct ena_adapter *adapter = dev->data->dev_private;
1224         struct ena_ring *rxq = NULL;
1225         size_t buffer_size;
1226         int i;
1227         uint16_t dyn_thresh;
1228
1229         rxq = &adapter->rx_ring[queue_idx];
1230         if (rxq->configured) {
1231                 PMD_DRV_LOG(CRIT,
1232                         "API violation. Queue[%d] is already configured\n",
1233                         queue_idx);
1234                 return ENA_COM_FAULT;
1235         }
1236
1237         if (!rte_is_power_of_2(nb_desc)) {
1238                 PMD_DRV_LOG(ERR,
1239                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1240                         nb_desc);
1241                 return -EINVAL;
1242         }
1243
1244         if (nb_desc > adapter->max_rx_ring_size) {
1245                 PMD_DRV_LOG(ERR,
1246                         "Unsupported size of Rx queue (max size: %d)\n",
1247                         adapter->max_rx_ring_size);
1248                 return -EINVAL;
1249         }
1250
1251         /* ENA isn't supporting buffers smaller than 1400 bytes */
1252         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1253         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1254                 PMD_DRV_LOG(ERR,
1255                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1256                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1257                 return -EINVAL;
1258         }
1259
1260         rxq->port_id = dev->data->port_id;
1261         rxq->next_to_clean = 0;
1262         rxq->next_to_use = 0;
1263         rxq->ring_size = nb_desc;
1264         rxq->size_mask = nb_desc - 1;
1265         rxq->numa_socket_id = socket_id;
1266         rxq->mb_pool = mp;
1267
1268         rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1269                 sizeof(struct ena_rx_buffer) * nb_desc,
1270                 RTE_CACHE_LINE_SIZE,
1271                 socket_id);
1272         if (!rxq->rx_buffer_info) {
1273                 PMD_DRV_LOG(ERR,
1274                         "Failed to allocate memory for Rx buffer info\n");
1275                 return -ENOMEM;
1276         }
1277
1278         rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1279                 sizeof(struct rte_mbuf *) * nb_desc,
1280                 RTE_CACHE_LINE_SIZE,
1281                 socket_id);
1282         if (!rxq->rx_refill_buffer) {
1283                 PMD_DRV_LOG(ERR,
1284                         "Failed to allocate memory for Rx refill buffer\n");
1285                 rte_free(rxq->rx_buffer_info);
1286                 rxq->rx_buffer_info = NULL;
1287                 return -ENOMEM;
1288         }
1289
1290         rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1291                 sizeof(uint16_t) * nb_desc,
1292                 RTE_CACHE_LINE_SIZE,
1293                 socket_id);
1294         if (!rxq->empty_rx_reqs) {
1295                 PMD_DRV_LOG(ERR,
1296                         "Failed to allocate memory for empty Rx requests\n");
1297                 rte_free(rxq->rx_buffer_info);
1298                 rxq->rx_buffer_info = NULL;
1299                 rte_free(rxq->rx_refill_buffer);
1300                 rxq->rx_refill_buffer = NULL;
1301                 return -ENOMEM;
1302         }
1303
1304         for (i = 0; i < nb_desc; i++)
1305                 rxq->empty_rx_reqs[i] = i;
1306
1307         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1308
1309         if (rx_conf->rx_free_thresh != 0) {
1310                 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1311         } else {
1312                 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1313                 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1314                         (uint16_t)(ENA_REFILL_THRESH_PACKET));
1315         }
1316
1317         /* Store pointer to this queue in upper layer */
1318         rxq->configured = 1;
1319         dev->data->rx_queues[queue_idx] = rxq;
1320
1321         return 0;
1322 }
1323
1324 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1325                                   struct rte_mbuf *mbuf, uint16_t id)
1326 {
1327         struct ena_com_buf ebuf;
1328         int rc;
1329
1330         /* prepare physical address for DMA transaction */
1331         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1332         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1333
1334         /* pass resource to device */
1335         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1336         if (unlikely(rc != 0))
1337                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1338
1339         return rc;
1340 }
1341
1342 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1343 {
1344         unsigned int i;
1345         int rc;
1346         uint16_t next_to_use = rxq->next_to_use;
1347         uint16_t req_id;
1348 #ifdef RTE_ETHDEV_DEBUG_RX
1349         uint16_t in_use;
1350 #endif
1351         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1352
1353         if (unlikely(!count))
1354                 return 0;
1355
1356 #ifdef RTE_ETHDEV_DEBUG_RX
1357         in_use = rxq->ring_size - 1 -
1358                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1359         if (unlikely((in_use + count) >= rxq->ring_size))
1360                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1361 #endif
1362
1363         /* get resources for incoming packets */
1364         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1365         if (unlikely(rc < 0)) {
1366                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1367                 ++rxq->rx_stats.mbuf_alloc_fail;
1368                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1369                 return 0;
1370         }
1371
1372         for (i = 0; i < count; i++) {
1373                 struct rte_mbuf *mbuf = mbufs[i];
1374                 struct ena_rx_buffer *rx_info;
1375
1376                 if (likely((i + 4) < count))
1377                         rte_prefetch0(mbufs[i + 4]);
1378
1379                 req_id = rxq->empty_rx_reqs[next_to_use];
1380                 rx_info = &rxq->rx_buffer_info[req_id];
1381
1382                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1383                 if (unlikely(rc != 0))
1384                         break;
1385
1386                 rx_info->mbuf = mbuf;
1387                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1388         }
1389
1390         if (unlikely(i < count)) {
1391                 PMD_RX_LOG(WARNING,
1392                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1393                         rxq->id, i, count);
1394                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1395                 ++rxq->rx_stats.refill_partial;
1396         }
1397
1398         /* When we submitted free resources to device... */
1399         if (likely(i > 0)) {
1400                 /* ...let HW know that it can fill buffers with data. */
1401                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1402
1403                 rxq->next_to_use = next_to_use;
1404         }
1405
1406         return i;
1407 }
1408
1409 static int ena_device_init(struct ena_com_dev *ena_dev,
1410                            struct rte_pci_device *pdev,
1411                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1412                            bool *wd_state)
1413 {
1414         uint32_t aenq_groups;
1415         int rc;
1416         bool readless_supported;
1417
1418         /* Initialize mmio registers */
1419         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1420         if (rc) {
1421                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1422                 return rc;
1423         }
1424
1425         /* The PCIe configuration space revision id indicate if mmio reg
1426          * read is disabled.
1427          */
1428         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1429         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1430
1431         /* reset device */
1432         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1433         if (rc) {
1434                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1435                 goto err_mmio_read_less;
1436         }
1437
1438         /* check FW version */
1439         rc = ena_com_validate_version(ena_dev);
1440         if (rc) {
1441                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1442                 goto err_mmio_read_less;
1443         }
1444
1445         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1446
1447         /* ENA device administration layer init */
1448         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1449         if (rc) {
1450                 PMD_DRV_LOG(ERR,
1451                         "Cannot initialize ENA admin queue\n");
1452                 goto err_mmio_read_less;
1453         }
1454
1455         /* To enable the msix interrupts the driver needs to know the number
1456          * of queues. So the driver uses polling mode to retrieve this
1457          * information.
1458          */
1459         ena_com_set_admin_polling_mode(ena_dev, true);
1460
1461         ena_config_host_info(ena_dev);
1462
1463         /* Get Device Attributes and features */
1464         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1465         if (rc) {
1466                 PMD_DRV_LOG(ERR,
1467                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1468                 goto err_admin_init;
1469         }
1470
1471         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1472                       BIT(ENA_ADMIN_NOTIFICATION) |
1473                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1474                       BIT(ENA_ADMIN_FATAL_ERROR) |
1475                       BIT(ENA_ADMIN_WARNING);
1476
1477         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1478         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1479         if (rc) {
1480                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc);
1481                 goto err_admin_init;
1482         }
1483
1484         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1485
1486         return 0;
1487
1488 err_admin_init:
1489         ena_com_admin_destroy(ena_dev);
1490
1491 err_mmio_read_less:
1492         ena_com_mmio_reg_read_request_destroy(ena_dev);
1493
1494         return rc;
1495 }
1496
1497 static void ena_interrupt_handler_rte(void *cb_arg)
1498 {
1499         struct rte_eth_dev *dev = cb_arg;
1500         struct ena_adapter *adapter = dev->data->dev_private;
1501         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1502
1503         ena_com_admin_q_comp_intr_handler(ena_dev);
1504         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1505                 ena_com_aenq_intr_handler(ena_dev, dev);
1506 }
1507
1508 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1509 {
1510         if (!adapter->wd_state)
1511                 return;
1512
1513         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1514                 return;
1515
1516         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1517             adapter->keep_alive_timeout)) {
1518                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1519                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1520                 adapter->trigger_reset = true;
1521                 ++adapter->dev_stats.wd_expired;
1522         }
1523 }
1524
1525 /* Check if admin queue is enabled */
1526 static void check_for_admin_com_state(struct ena_adapter *adapter)
1527 {
1528         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1529                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1530                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1531                 adapter->trigger_reset = true;
1532         }
1533 }
1534
1535 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1536                                             struct ena_ring *tx_ring)
1537 {
1538         struct ena_tx_buffer *tx_buf;
1539         uint64_t timestamp;
1540         uint64_t completion_delay;
1541         uint32_t missed_tx = 0;
1542         unsigned int i;
1543         int rc = 0;
1544
1545         for (i = 0; i < tx_ring->ring_size; ++i) {
1546                 tx_buf = &tx_ring->tx_buffer_info[i];
1547                 timestamp = tx_buf->timestamp;
1548
1549                 if (timestamp == 0)
1550                         continue;
1551
1552                 completion_delay = rte_get_timer_cycles() - timestamp;
1553                 if (completion_delay > adapter->missing_tx_completion_to) {
1554                         if (unlikely(!tx_buf->print_once)) {
1555                                 PMD_TX_LOG(WARNING,
1556                                         "Found a Tx that wasn't completed on time, qid %d, index %d. "
1557                                         "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1558                                         tx_ring->id, i, completion_delay /
1559                                         rte_get_timer_hz() * 1000);
1560                                 tx_buf->print_once = true;
1561                         }
1562                         ++missed_tx;
1563                 }
1564         }
1565
1566         if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1567                 PMD_DRV_LOG(ERR,
1568                         "The number of lost Tx completions is above the threshold (%d > %d). "
1569                         "Trigger the device reset.\n",
1570                         missed_tx,
1571                         tx_ring->missing_tx_completion_threshold);
1572                 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1573                 adapter->trigger_reset = true;
1574                 rc = -EIO;
1575         }
1576
1577         tx_ring->tx_stats.missed_tx += missed_tx;
1578
1579         return rc;
1580 }
1581
1582 static void check_for_tx_completions(struct ena_adapter *adapter)
1583 {
1584         struct ena_ring *tx_ring;
1585         uint64_t tx_cleanup_delay;
1586         size_t qid;
1587         int budget;
1588         uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1589
1590         if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1591                 return;
1592
1593         nb_tx_queues = adapter->edev_data->nb_tx_queues;
1594         budget = adapter->missing_tx_completion_budget;
1595
1596         qid = adapter->last_tx_comp_qid;
1597         while (budget-- > 0) {
1598                 tx_ring = &adapter->tx_ring[qid];
1599
1600                 /* Tx cleanup is called only by the burst function and can be
1601                  * called dynamically by the application. Also cleanup is
1602                  * limited by the threshold. To avoid false detection of the
1603                  * missing HW Tx completion, get the delay since last cleanup
1604                  * function was called.
1605                  */
1606                 tx_cleanup_delay = rte_get_timer_cycles() -
1607                         tx_ring->last_cleanup_ticks;
1608                 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1609                         check_for_tx_completion_in_queue(adapter, tx_ring);
1610                 qid = (qid + 1) % nb_tx_queues;
1611         }
1612
1613         adapter->last_tx_comp_qid = qid;
1614 }
1615
1616 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1617                                   void *arg)
1618 {
1619         struct rte_eth_dev *dev = arg;
1620         struct ena_adapter *adapter = dev->data->dev_private;
1621
1622         check_for_missing_keep_alive(adapter);
1623         check_for_admin_com_state(adapter);
1624         check_for_tx_completions(adapter);
1625
1626         if (unlikely(adapter->trigger_reset)) {
1627                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1628                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1629                         NULL);
1630         }
1631 }
1632
1633 static inline void
1634 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1635                                struct ena_admin_feature_llq_desc *llq,
1636                                bool use_large_llq_hdr)
1637 {
1638         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1639         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1640         llq_config->llq_num_decs_before_header =
1641                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1642
1643         if (use_large_llq_hdr &&
1644             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1645                 llq_config->llq_ring_entry_size =
1646                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1647                 llq_config->llq_ring_entry_size_value = 256;
1648         } else {
1649                 llq_config->llq_ring_entry_size =
1650                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1651                 llq_config->llq_ring_entry_size_value = 128;
1652         }
1653 }
1654
1655 static int
1656 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1657                                 struct ena_com_dev *ena_dev,
1658                                 struct ena_admin_feature_llq_desc *llq,
1659                                 struct ena_llq_configurations *llq_default_configurations)
1660 {
1661         int rc;
1662         u32 llq_feature_mask;
1663
1664         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1665         if (!(ena_dev->supported_features & llq_feature_mask)) {
1666                 PMD_DRV_LOG(INFO,
1667                         "LLQ is not supported. Fallback to host mode policy.\n");
1668                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1669                 return 0;
1670         }
1671
1672         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1673         if (unlikely(rc)) {
1674                 PMD_INIT_LOG(WARNING,
1675                         "Failed to config dev mode. Fallback to host mode policy.\n");
1676                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1677                 return 0;
1678         }
1679
1680         /* Nothing to config, exit */
1681         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1682                 return 0;
1683
1684         if (!adapter->dev_mem_base) {
1685                 PMD_DRV_LOG(ERR,
1686                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1687                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1688                 return 0;
1689         }
1690
1691         ena_dev->mem_bar = adapter->dev_mem_base;
1692
1693         return 0;
1694 }
1695
1696 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1697         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1698 {
1699         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1700
1701         /* Regular queues capabilities */
1702         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1703                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1704                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1705                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1706                                     max_queue_ext->max_rx_cq_num);
1707                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1708                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1709         } else {
1710                 struct ena_admin_queue_feature_desc *max_queues =
1711                         &get_feat_ctx->max_queues;
1712                 io_tx_sq_num = max_queues->max_sq_num;
1713                 io_tx_cq_num = max_queues->max_cq_num;
1714                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1715         }
1716
1717         /* In case of LLQ use the llq number in the get feature cmd */
1718         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1719                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1720
1721         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1722         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1723         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1724
1725         if (unlikely(max_num_io_queues == 0)) {
1726                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1727                 return -EFAULT;
1728         }
1729
1730         return max_num_io_queues;
1731 }
1732
1733 static void
1734 ena_set_offloads(struct ena_offloads *offloads,
1735                  struct ena_admin_feature_offload_desc *offload_desc)
1736 {
1737         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1738                 offloads->tx_offloads |= ENA_IPV4_TSO;
1739
1740         /* Tx IPv4 checksum offloads */
1741         if (offload_desc->tx &
1742             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
1743                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
1744         if (offload_desc->tx &
1745             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
1746                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
1747         if (offload_desc->tx &
1748             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1749                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
1750
1751         /* Tx IPv6 checksum offloads */
1752         if (offload_desc->tx &
1753             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
1754                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
1755         if (offload_desc->tx &
1756              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
1757                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
1758
1759         /* Rx IPv4 checksum offloads */
1760         if (offload_desc->rx_supported &
1761             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
1762                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
1763         if (offload_desc->rx_supported &
1764             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1765                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
1766
1767         /* Rx IPv6 checksum offloads */
1768         if (offload_desc->rx_supported &
1769             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
1770                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
1771
1772         if (offload_desc->rx_supported &
1773             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
1774                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
1775 }
1776
1777 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1778 {
1779         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1780         struct rte_pci_device *pci_dev;
1781         struct rte_intr_handle *intr_handle;
1782         struct ena_adapter *adapter = eth_dev->data->dev_private;
1783         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1784         struct ena_com_dev_get_features_ctx get_feat_ctx;
1785         struct ena_llq_configurations llq_config;
1786         const char *queue_type_str;
1787         uint32_t max_num_io_queues;
1788         int rc;
1789         static int adapters_found;
1790         bool disable_meta_caching;
1791         bool wd_state = false;
1792
1793         eth_dev->dev_ops = &ena_dev_ops;
1794         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1795         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1796         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1797
1798         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1799                 return 0;
1800
1801         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1802
1803         memset(adapter, 0, sizeof(struct ena_adapter));
1804         ena_dev = &adapter->ena_dev;
1805
1806         adapter->edev_data = eth_dev->data;
1807
1808         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1809
1810         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1811                      pci_dev->addr.domain,
1812                      pci_dev->addr.bus,
1813                      pci_dev->addr.devid,
1814                      pci_dev->addr.function);
1815
1816         intr_handle = pci_dev->intr_handle;
1817
1818         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1819         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1820
1821         if (!adapter->regs) {
1822                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1823                              ENA_REGS_BAR);
1824                 return -ENXIO;
1825         }
1826
1827         ena_dev->reg_bar = adapter->regs;
1828         /* This is a dummy pointer for ena_com functions. */
1829         ena_dev->dmadev = adapter;
1830
1831         adapter->id_number = adapters_found;
1832
1833         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1834                  adapter->id_number);
1835
1836         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1837         if (rc != 0) {
1838                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1839                 goto err;
1840         }
1841
1842         /* device specific initialization routine */
1843         rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state);
1844         if (rc) {
1845                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1846                 goto err;
1847         }
1848         adapter->wd_state = wd_state;
1849
1850         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1851                 adapter->use_large_llq_hdr);
1852         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1853                                              &get_feat_ctx.llq, &llq_config);
1854         if (unlikely(rc)) {
1855                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
1856                 return rc;
1857         }
1858
1859         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1860                 queue_type_str = "Regular";
1861         else
1862                 queue_type_str = "Low latency";
1863         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1864
1865         calc_queue_ctx.ena_dev = ena_dev;
1866         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1867
1868         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1869         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1870                 adapter->use_large_llq_hdr);
1871         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1872                 rc = -EFAULT;
1873                 goto err_device_destroy;
1874         }
1875
1876         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1877         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1878         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1879         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1880         adapter->max_num_io_queues = max_num_io_queues;
1881
1882         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1883                 disable_meta_caching =
1884                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1885                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1886         } else {
1887                 disable_meta_caching = false;
1888         }
1889
1890         /* prepare ring structures */
1891         ena_init_rings(adapter, disable_meta_caching);
1892
1893         ena_config_debug_area(adapter);
1894
1895         /* Set max MTU for this device */
1896         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1897
1898         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
1899
1900         /* Copy MAC address and point DPDK to it */
1901         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1902         rte_ether_addr_copy((struct rte_ether_addr *)
1903                         get_feat_ctx.dev_attr.mac_addr,
1904                         (struct rte_ether_addr *)adapter->mac_addr);
1905
1906         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
1907         if (unlikely(rc != 0)) {
1908                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
1909                 goto err_delete_debug_area;
1910         }
1911
1912         adapter->drv_stats = rte_zmalloc("adapter stats",
1913                                          sizeof(*adapter->drv_stats),
1914                                          RTE_CACHE_LINE_SIZE);
1915         if (!adapter->drv_stats) {
1916                 PMD_DRV_LOG(ERR,
1917                         "Failed to allocate memory for adapter statistics\n");
1918                 rc = -ENOMEM;
1919                 goto err_rss_destroy;
1920         }
1921
1922         rte_spinlock_init(&adapter->admin_lock);
1923
1924         rte_intr_callback_register(intr_handle,
1925                                    ena_interrupt_handler_rte,
1926                                    eth_dev);
1927         rte_intr_enable(intr_handle);
1928         ena_com_set_admin_polling_mode(ena_dev, false);
1929         ena_com_admin_aenq_enable(ena_dev);
1930
1931         if (adapters_found == 0)
1932                 rte_timer_subsystem_init();
1933         rte_timer_init(&adapter->timer_wd);
1934
1935         adapters_found++;
1936         adapter->state = ENA_ADAPTER_STATE_INIT;
1937
1938         return 0;
1939
1940 err_rss_destroy:
1941         ena_com_rss_destroy(ena_dev);
1942 err_delete_debug_area:
1943         ena_com_delete_debug_area(ena_dev);
1944
1945 err_device_destroy:
1946         ena_com_delete_host_info(ena_dev);
1947         ena_com_admin_destroy(ena_dev);
1948
1949 err:
1950         return rc;
1951 }
1952
1953 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1954 {
1955         struct ena_adapter *adapter = eth_dev->data->dev_private;
1956         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1957
1958         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1959                 return;
1960
1961         ena_com_set_admin_running_state(ena_dev, false);
1962
1963         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1964                 ena_close(eth_dev);
1965
1966         ena_com_rss_destroy(ena_dev);
1967
1968         ena_com_delete_debug_area(ena_dev);
1969         ena_com_delete_host_info(ena_dev);
1970
1971         ena_com_abort_admin_commands(ena_dev);
1972         ena_com_wait_for_abort_completion(ena_dev);
1973         ena_com_admin_destroy(ena_dev);
1974         ena_com_mmio_reg_read_request_destroy(ena_dev);
1975
1976         adapter->state = ENA_ADAPTER_STATE_FREE;
1977 }
1978
1979 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1980 {
1981         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1982                 return 0;
1983
1984         ena_destroy_device(eth_dev);
1985
1986         return 0;
1987 }
1988
1989 static int ena_dev_configure(struct rte_eth_dev *dev)
1990 {
1991         struct ena_adapter *adapter = dev->data->dev_private;
1992
1993         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1994
1995         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1996                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1997         dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
1998
1999         /* Scattered Rx cannot be turned off in the HW, so this capability must
2000          * be forced.
2001          */
2002         dev->data->scattered_rx = 1;
2003
2004         adapter->last_tx_comp_qid = 0;
2005
2006         adapter->missing_tx_completion_budget =
2007                 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2008
2009         adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2010         /* To avoid detection of the spurious Tx completion timeout due to
2011          * application not calling the Tx cleanup function, set timeout for the
2012          * Tx queue which should be half of the missing completion timeout for a
2013          * safety. If there will be a lot of missing Tx completions in the
2014          * queue, they will be detected sooner or later.
2015          */
2016         adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2017
2018         return 0;
2019 }
2020
2021 static void ena_init_rings(struct ena_adapter *adapter,
2022                            bool disable_meta_caching)
2023 {
2024         size_t i;
2025
2026         for (i = 0; i < adapter->max_num_io_queues; i++) {
2027                 struct ena_ring *ring = &adapter->tx_ring[i];
2028
2029                 ring->configured = 0;
2030                 ring->type = ENA_RING_TYPE_TX;
2031                 ring->adapter = adapter;
2032                 ring->id = i;
2033                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2034                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2035                 ring->sgl_size = adapter->max_tx_sgl_size;
2036                 ring->disable_meta_caching = disable_meta_caching;
2037         }
2038
2039         for (i = 0; i < adapter->max_num_io_queues; i++) {
2040                 struct ena_ring *ring = &adapter->rx_ring[i];
2041
2042                 ring->configured = 0;
2043                 ring->type = ENA_RING_TYPE_RX;
2044                 ring->adapter = adapter;
2045                 ring->id = i;
2046                 ring->sgl_size = adapter->max_rx_sgl_size;
2047         }
2048 }
2049
2050 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2051 {
2052         uint64_t port_offloads = 0;
2053
2054         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2055                 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2056
2057         if (adapter->offloads.rx_offloads &
2058             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2059                 port_offloads |=
2060                         RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2061
2062         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2063                 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2064
2065         port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2066
2067         return port_offloads;
2068 }
2069
2070 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2071 {
2072         uint64_t port_offloads = 0;
2073
2074         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2075                 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2076
2077         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2078                 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2079         if (adapter->offloads.tx_offloads &
2080             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2081              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2082                 port_offloads |=
2083                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2084
2085         port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2086
2087         return port_offloads;
2088 }
2089
2090 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2091 {
2092         RTE_SET_USED(adapter);
2093
2094         return 0;
2095 }
2096
2097 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2098 {
2099         RTE_SET_USED(adapter);
2100
2101         return 0;
2102 }
2103
2104 static int ena_infos_get(struct rte_eth_dev *dev,
2105                           struct rte_eth_dev_info *dev_info)
2106 {
2107         struct ena_adapter *adapter;
2108         struct ena_com_dev *ena_dev;
2109
2110         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2111         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2112         adapter = dev->data->dev_private;
2113
2114         ena_dev = &adapter->ena_dev;
2115         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2116
2117         dev_info->speed_capa =
2118                         RTE_ETH_LINK_SPEED_1G   |
2119                         RTE_ETH_LINK_SPEED_2_5G |
2120                         RTE_ETH_LINK_SPEED_5G   |
2121                         RTE_ETH_LINK_SPEED_10G  |
2122                         RTE_ETH_LINK_SPEED_25G  |
2123                         RTE_ETH_LINK_SPEED_40G  |
2124                         RTE_ETH_LINK_SPEED_50G  |
2125                         RTE_ETH_LINK_SPEED_100G;
2126
2127         /* Inform framework about available features */
2128         dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2129         dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2130         dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2131         dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2132
2133         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2134         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2135
2136         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2137         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2138                 RTE_ETHER_CRC_LEN;
2139         dev_info->min_mtu = ENA_MIN_MTU;
2140         dev_info->max_mtu = adapter->max_mtu;
2141         dev_info->max_mac_addrs = 1;
2142
2143         dev_info->max_rx_queues = adapter->max_num_io_queues;
2144         dev_info->max_tx_queues = adapter->max_num_io_queues;
2145         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2146
2147         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2148         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2149         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2150                                         adapter->max_rx_sgl_size);
2151         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2152                                         adapter->max_rx_sgl_size);
2153
2154         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2155         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2156         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2157                                         adapter->max_tx_sgl_size);
2158         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2159                                         adapter->max_tx_sgl_size);
2160
2161         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2162         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2163
2164         return 0;
2165 }
2166
2167 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2168 {
2169         mbuf->data_len = len;
2170         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2171         mbuf->refcnt = 1;
2172         mbuf->next = NULL;
2173 }
2174
2175 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2176                                     struct ena_com_rx_buf_info *ena_bufs,
2177                                     uint32_t descs,
2178                                     uint16_t *next_to_clean,
2179                                     uint8_t offset)
2180 {
2181         struct rte_mbuf *mbuf;
2182         struct rte_mbuf *mbuf_head;
2183         struct ena_rx_buffer *rx_info;
2184         int rc;
2185         uint16_t ntc, len, req_id, buf = 0;
2186
2187         if (unlikely(descs == 0))
2188                 return NULL;
2189
2190         ntc = *next_to_clean;
2191
2192         len = ena_bufs[buf].len;
2193         req_id = ena_bufs[buf].req_id;
2194
2195         rx_info = &rx_ring->rx_buffer_info[req_id];
2196
2197         mbuf = rx_info->mbuf;
2198         RTE_ASSERT(mbuf != NULL);
2199
2200         ena_init_rx_mbuf(mbuf, len);
2201
2202         /* Fill the mbuf head with the data specific for 1st segment. */
2203         mbuf_head = mbuf;
2204         mbuf_head->nb_segs = descs;
2205         mbuf_head->port = rx_ring->port_id;
2206         mbuf_head->pkt_len = len;
2207         mbuf_head->data_off += offset;
2208
2209         rx_info->mbuf = NULL;
2210         rx_ring->empty_rx_reqs[ntc] = req_id;
2211         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2212
2213         while (--descs) {
2214                 ++buf;
2215                 len = ena_bufs[buf].len;
2216                 req_id = ena_bufs[buf].req_id;
2217
2218                 rx_info = &rx_ring->rx_buffer_info[req_id];
2219                 RTE_ASSERT(rx_info->mbuf != NULL);
2220
2221                 if (unlikely(len == 0)) {
2222                         /*
2223                          * Some devices can pass descriptor with the length 0.
2224                          * To avoid confusion, the PMD is simply putting the
2225                          * descriptor back, as it was never used. We'll avoid
2226                          * mbuf allocation that way.
2227                          */
2228                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2229                                 rx_info->mbuf, req_id);
2230                         if (unlikely(rc != 0)) {
2231                                 /* Free the mbuf in case of an error. */
2232                                 rte_mbuf_raw_free(rx_info->mbuf);
2233                         } else {
2234                                 /*
2235                                  * If there was no error, just exit the loop as
2236                                  * 0 length descriptor is always the last one.
2237                                  */
2238                                 break;
2239                         }
2240                 } else {
2241                         /* Create an mbuf chain. */
2242                         mbuf->next = rx_info->mbuf;
2243                         mbuf = mbuf->next;
2244
2245                         ena_init_rx_mbuf(mbuf, len);
2246                         mbuf_head->pkt_len += len;
2247                 }
2248
2249                 /*
2250                  * Mark the descriptor as depleted and perform necessary
2251                  * cleanup.
2252                  * This code will execute in two cases:
2253                  *  1. Descriptor len was greater than 0 - normal situation.
2254                  *  2. Descriptor len was 0 and we failed to add the descriptor
2255                  *     to the device. In that situation, we should try to add
2256                  *     the mbuf again in the populate routine and mark the
2257                  *     descriptor as used up by the device.
2258                  */
2259                 rx_info->mbuf = NULL;
2260                 rx_ring->empty_rx_reqs[ntc] = req_id;
2261                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2262         }
2263
2264         *next_to_clean = ntc;
2265
2266         return mbuf_head;
2267 }
2268
2269 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2270                                   uint16_t nb_pkts)
2271 {
2272         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2273         unsigned int free_queue_entries;
2274         uint16_t next_to_clean = rx_ring->next_to_clean;
2275         uint16_t descs_in_use;
2276         struct rte_mbuf *mbuf;
2277         uint16_t completed;
2278         struct ena_com_rx_ctx ena_rx_ctx;
2279         int i, rc = 0;
2280         bool fill_hash;
2281
2282 #ifdef RTE_ETHDEV_DEBUG_RX
2283         /* Check adapter state */
2284         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2285                 PMD_RX_LOG(ALERT,
2286                         "Trying to receive pkts while device is NOT running\n");
2287                 return 0;
2288         }
2289 #endif
2290
2291         fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2292
2293         descs_in_use = rx_ring->ring_size -
2294                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2295         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2296
2297         for (completed = 0; completed < nb_pkts; completed++) {
2298                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2299                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2300                 ena_rx_ctx.descs = 0;
2301                 ena_rx_ctx.pkt_offset = 0;
2302                 /* receive packet context */
2303                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2304                                     rx_ring->ena_com_io_sq,
2305                                     &ena_rx_ctx);
2306                 if (unlikely(rc)) {
2307                         PMD_RX_LOG(ERR,
2308                                 "Failed to get the packet from the device, rc: %d\n",
2309                                 rc);
2310                         if (rc == ENA_COM_NO_SPACE) {
2311                                 ++rx_ring->rx_stats.bad_desc_num;
2312                                 rx_ring->adapter->reset_reason =
2313                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2314                         } else {
2315                                 ++rx_ring->rx_stats.bad_req_id;
2316                                 rx_ring->adapter->reset_reason =
2317                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2318                         }
2319                         rx_ring->adapter->trigger_reset = true;
2320                         return 0;
2321                 }
2322
2323                 mbuf = ena_rx_mbuf(rx_ring,
2324                         ena_rx_ctx.ena_bufs,
2325                         ena_rx_ctx.descs,
2326                         &next_to_clean,
2327                         ena_rx_ctx.pkt_offset);
2328                 if (unlikely(mbuf == NULL)) {
2329                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2330                                 rx_ring->empty_rx_reqs[next_to_clean] =
2331                                         rx_ring->ena_bufs[i].req_id;
2332                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2333                                         next_to_clean, rx_ring->size_mask);
2334                         }
2335                         break;
2336                 }
2337
2338                 /* fill mbuf attributes if any */
2339                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash);
2340
2341                 if (unlikely(mbuf->ol_flags &
2342                                 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD))) {
2343                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2344                         ++rx_ring->rx_stats.bad_csum;
2345                 }
2346
2347                 rx_pkts[completed] = mbuf;
2348                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2349         }
2350
2351         rx_ring->rx_stats.cnt += completed;
2352         rx_ring->next_to_clean = next_to_clean;
2353
2354         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2355
2356         /* Burst refill to save doorbells, memory barriers, const interval */
2357         if (free_queue_entries >= rx_ring->rx_free_thresh) {
2358                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2359                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2360         }
2361
2362         return completed;
2363 }
2364
2365 static uint16_t
2366 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2367                 uint16_t nb_pkts)
2368 {
2369         int32_t ret;
2370         uint32_t i;
2371         struct rte_mbuf *m;
2372         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2373         struct ena_adapter *adapter = tx_ring->adapter;
2374         struct rte_ipv4_hdr *ip_hdr;
2375         uint64_t ol_flags;
2376         uint64_t l4_csum_flag;
2377         uint64_t dev_offload_capa;
2378         uint16_t frag_field;
2379         bool need_pseudo_csum;
2380
2381         dev_offload_capa = adapter->offloads.tx_offloads;
2382         for (i = 0; i != nb_pkts; i++) {
2383                 m = tx_pkts[i];
2384                 ol_flags = m->ol_flags;
2385
2386                 /* Check if any offload flag was set */
2387                 if (ol_flags == 0)
2388                         continue;
2389
2390                 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2391                 /* SCTP checksum offload is not supported by the ENA. */
2392                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2393                     l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2394                         PMD_TX_LOG(DEBUG,
2395                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2396                                 i, ol_flags);
2397                         rte_errno = ENOTSUP;
2398                         return i;
2399                 }
2400
2401                 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2402                     !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2403                       m->nb_segs == tx_ring->sgl_size &&
2404                       m->data_len < tx_ring->tx_max_header_size))) {
2405                         PMD_TX_LOG(DEBUG,
2406                                 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2407                                 i, m->nb_segs);
2408                         rte_errno = EINVAL;
2409                         return i;
2410                 }
2411
2412 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2413                 /* Check if requested offload is also enabled for the queue */
2414                 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2415                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2416                     (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2417                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2418                     (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2419                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2420                         PMD_TX_LOG(DEBUG,
2421                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2422                                 i, m->nb_segs, tx_ring->id);
2423                         rte_errno = EINVAL;
2424                         return i;
2425                 }
2426
2427                 /* The caller is obligated to set l2 and l3 len if any cksum
2428                  * offload is enabled.
2429                  */
2430                 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2431                     (m->l2_len == 0 || m->l3_len == 0))) {
2432                         PMD_TX_LOG(DEBUG,
2433                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2434                                 i);
2435                         rte_errno = EINVAL;
2436                         return i;
2437                 }
2438                 ret = rte_validate_tx_offload(m);
2439                 if (ret != 0) {
2440                         rte_errno = -ret;
2441                         return i;
2442                 }
2443 #endif
2444
2445                 /* Verify HW support for requested offloads and determine if
2446                  * pseudo header checksum is needed.
2447                  */
2448                 need_pseudo_csum = false;
2449                 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2450                         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2451                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2452                                 rte_errno = ENOTSUP;
2453                                 return i;
2454                         }
2455
2456                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2457                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2458                                 rte_errno = ENOTSUP;
2459                                 return i;
2460                         }
2461
2462                         /* Check HW capabilities and if pseudo csum is needed
2463                          * for L4 offloads.
2464                          */
2465                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2466                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2467                                 if (dev_offload_capa &
2468                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2469                                         need_pseudo_csum = true;
2470                                 } else {
2471                                         rte_errno = ENOTSUP;
2472                                         return i;
2473                                 }
2474                         }
2475
2476                         /* Parse the DF flag */
2477                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2478                                 struct rte_ipv4_hdr *, m->l2_len);
2479                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2480                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2481                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2482                         } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2483                                 /* In case we are supposed to TSO and have DF
2484                                  * not set (DF=0) hardware must be provided with
2485                                  * partial checksum.
2486                                  */
2487                                 need_pseudo_csum = true;
2488                         }
2489                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2490                         /* There is no support for IPv6 TSO as for now. */
2491                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2492                                 rte_errno = ENOTSUP;
2493                                 return i;
2494                         }
2495
2496                         /* Check HW capabilities and if pseudo csum is needed */
2497                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2498                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2499                                 if (dev_offload_capa &
2500                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2501                                         need_pseudo_csum = true;
2502                                 } else {
2503                                         rte_errno = ENOTSUP;
2504                                         return i;
2505                                 }
2506                         }
2507                 }
2508
2509                 if (need_pseudo_csum) {
2510                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2511                         if (ret != 0) {
2512                                 rte_errno = -ret;
2513                                 return i;
2514                         }
2515                 }
2516         }
2517
2518         return i;
2519 }
2520
2521 static void ena_update_hints(struct ena_adapter *adapter,
2522                              struct ena_admin_ena_hw_hints *hints)
2523 {
2524         if (hints->admin_completion_tx_timeout)
2525                 adapter->ena_dev.admin_queue.completion_timeout =
2526                         hints->admin_completion_tx_timeout * 1000;
2527
2528         if (hints->mmio_read_timeout)
2529                 /* convert to usec */
2530                 adapter->ena_dev.mmio_read.reg_read_to =
2531                         hints->mmio_read_timeout * 1000;
2532
2533         if (hints->missing_tx_completion_timeout) {
2534                 if (hints->missing_tx_completion_timeout ==
2535                     ENA_HW_HINTS_NO_TIMEOUT) {
2536                         adapter->missing_tx_completion_to =
2537                                 ENA_HW_HINTS_NO_TIMEOUT;
2538                 } else {
2539                         /* Convert from msecs to ticks */
2540                         adapter->missing_tx_completion_to = rte_get_timer_hz() *
2541                                 hints->missing_tx_completion_timeout / 1000;
2542                         adapter->tx_cleanup_stall_delay =
2543                                 adapter->missing_tx_completion_to / 2;
2544                 }
2545         }
2546
2547         if (hints->driver_watchdog_timeout) {
2548                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2549                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2550                 else
2551                         // Convert msecs to ticks
2552                         adapter->keep_alive_timeout =
2553                                 (hints->driver_watchdog_timeout *
2554                                 rte_get_timer_hz()) / 1000;
2555         }
2556 }
2557
2558 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2559         struct ena_tx_buffer *tx_info,
2560         struct rte_mbuf *mbuf,
2561         void **push_header,
2562         uint16_t *header_len)
2563 {
2564         struct ena_com_buf *ena_buf;
2565         uint16_t delta, seg_len, push_len;
2566
2567         delta = 0;
2568         seg_len = mbuf->data_len;
2569
2570         tx_info->mbuf = mbuf;
2571         ena_buf = tx_info->bufs;
2572
2573         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2574                 /*
2575                  * Tx header might be (and will be in most cases) smaller than
2576                  * tx_max_header_size. But it's not an issue to send more data
2577                  * to the device, than actually needed if the mbuf size is
2578                  * greater than tx_max_header_size.
2579                  */
2580                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2581                 *header_len = push_len;
2582
2583                 if (likely(push_len <= seg_len)) {
2584                         /* If the push header is in the single segment, then
2585                          * just point it to the 1st mbuf data.
2586                          */
2587                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2588                 } else {
2589                         /* If the push header lays in the several segments, copy
2590                          * it to the intermediate buffer.
2591                          */
2592                         rte_pktmbuf_read(mbuf, 0, push_len,
2593                                 tx_ring->push_buf_intermediate_buf);
2594                         *push_header = tx_ring->push_buf_intermediate_buf;
2595                         delta = push_len - seg_len;
2596                 }
2597         } else {
2598                 *push_header = NULL;
2599                 *header_len = 0;
2600                 push_len = 0;
2601         }
2602
2603         /* Process first segment taking into consideration pushed header */
2604         if (seg_len > push_len) {
2605                 ena_buf->paddr = mbuf->buf_iova +
2606                                 mbuf->data_off +
2607                                 push_len;
2608                 ena_buf->len = seg_len - push_len;
2609                 ena_buf++;
2610                 tx_info->num_of_bufs++;
2611         }
2612
2613         while ((mbuf = mbuf->next) != NULL) {
2614                 seg_len = mbuf->data_len;
2615
2616                 /* Skip mbufs if whole data is pushed as a header */
2617                 if (unlikely(delta > seg_len)) {
2618                         delta -= seg_len;
2619                         continue;
2620                 }
2621
2622                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2623                 ena_buf->len = seg_len - delta;
2624                 ena_buf++;
2625                 tx_info->num_of_bufs++;
2626
2627                 delta = 0;
2628         }
2629 }
2630
2631 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2632 {
2633         struct ena_tx_buffer *tx_info;
2634         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2635         uint16_t next_to_use;
2636         uint16_t header_len;
2637         uint16_t req_id;
2638         void *push_header;
2639         int nb_hw_desc;
2640         int rc;
2641
2642         /* Checking for space for 2 additional metadata descriptors due to
2643          * possible header split and metadata descriptor
2644          */
2645         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2646                                           mbuf->nb_segs + 2)) {
2647                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2648                 return ENA_COM_NO_MEM;
2649         }
2650
2651         next_to_use = tx_ring->next_to_use;
2652
2653         req_id = tx_ring->empty_tx_reqs[next_to_use];
2654         tx_info = &tx_ring->tx_buffer_info[req_id];
2655         tx_info->num_of_bufs = 0;
2656         RTE_ASSERT(tx_info->mbuf == NULL);
2657
2658         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2659
2660         ena_tx_ctx.ena_bufs = tx_info->bufs;
2661         ena_tx_ctx.push_header = push_header;
2662         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2663         ena_tx_ctx.req_id = req_id;
2664         ena_tx_ctx.header_len = header_len;
2665
2666         /* Set Tx offloads flags, if applicable */
2667         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2668                 tx_ring->disable_meta_caching);
2669
2670         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2671                         &ena_tx_ctx))) {
2672                 PMD_TX_LOG(DEBUG,
2673                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2674                         tx_ring->id);
2675                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2676                 tx_ring->tx_stats.doorbells++;
2677                 tx_ring->pkts_without_db = false;
2678         }
2679
2680         /* prepare the packet's descriptors to dma engine */
2681         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2682                 &nb_hw_desc);
2683         if (unlikely(rc)) {
2684                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2685                 ++tx_ring->tx_stats.prepare_ctx_err;
2686                 tx_ring->adapter->reset_reason =
2687                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2688                 tx_ring->adapter->trigger_reset = true;
2689                 return rc;
2690         }
2691
2692         tx_info->tx_descs = nb_hw_desc;
2693         tx_info->timestamp = rte_get_timer_cycles();
2694
2695         tx_ring->tx_stats.cnt++;
2696         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2697
2698         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2699                 tx_ring->size_mask);
2700
2701         return 0;
2702 }
2703
2704 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2705 {
2706         unsigned int total_tx_descs = 0;
2707         uint16_t cleanup_budget;
2708         uint16_t next_to_clean = tx_ring->next_to_clean;
2709
2710         /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
2711         cleanup_budget = tx_ring->size_mask;
2712
2713         while (likely(total_tx_descs < cleanup_budget)) {
2714                 struct rte_mbuf *mbuf;
2715                 struct ena_tx_buffer *tx_info;
2716                 uint16_t req_id;
2717
2718                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2719                         break;
2720
2721                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2722                         break;
2723
2724                 /* Get Tx info & store how many descs were processed  */
2725                 tx_info = &tx_ring->tx_buffer_info[req_id];
2726                 tx_info->timestamp = 0;
2727
2728                 mbuf = tx_info->mbuf;
2729                 rte_pktmbuf_free(mbuf);
2730
2731                 tx_info->mbuf = NULL;
2732                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2733
2734                 total_tx_descs += tx_info->tx_descs;
2735
2736                 /* Put back descriptor to the ring for reuse */
2737                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2738                         tx_ring->size_mask);
2739         }
2740
2741         if (likely(total_tx_descs > 0)) {
2742                 /* acknowledge completion of sent packets */
2743                 tx_ring->next_to_clean = next_to_clean;
2744                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2745                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2746         }
2747
2748         /* Notify completion handler that the cleanup was just called */
2749         tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
2750 }
2751
2752 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2753                                   uint16_t nb_pkts)
2754 {
2755         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2756         int available_desc;
2757         uint16_t sent_idx = 0;
2758
2759 #ifdef RTE_ETHDEV_DEBUG_TX
2760         /* Check adapter state */
2761         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2762                 PMD_TX_LOG(ALERT,
2763                         "Trying to xmit pkts while device is NOT running\n");
2764                 return 0;
2765         }
2766 #endif
2767
2768         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2769                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2770                         break;
2771                 tx_ring->pkts_without_db = true;
2772                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2773                         tx_ring->size_mask)]);
2774         }
2775
2776         available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2777         tx_ring->tx_stats.available_desc = available_desc;
2778
2779         /* If there are ready packets to be xmitted... */
2780         if (likely(tx_ring->pkts_without_db)) {
2781                 /* ...let HW do its best :-) */
2782                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2783                 tx_ring->tx_stats.doorbells++;
2784                 tx_ring->pkts_without_db = false;
2785         }
2786
2787         if (available_desc < tx_ring->tx_free_thresh)
2788                 ena_tx_cleanup(tx_ring);
2789
2790         tx_ring->tx_stats.available_desc =
2791                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2792         tx_ring->tx_stats.tx_poll++;
2793
2794         return sent_idx;
2795 }
2796
2797 int ena_copy_eni_stats(struct ena_adapter *adapter)
2798 {
2799         struct ena_admin_eni_stats admin_eni_stats;
2800         int rc;
2801
2802         rte_spinlock_lock(&adapter->admin_lock);
2803         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2804         rte_spinlock_unlock(&adapter->admin_lock);
2805         if (rc != 0) {
2806                 if (rc == ENA_COM_UNSUPPORTED) {
2807                         PMD_DRV_LOG(DEBUG,
2808                                 "Retrieving ENI metrics is not supported\n");
2809                 } else {
2810                         PMD_DRV_LOG(WARNING,
2811                                 "Failed to get ENI metrics, rc: %d\n", rc);
2812                 }
2813                 return rc;
2814         }
2815
2816         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2817                 sizeof(struct ena_stats_eni));
2818
2819         return 0;
2820 }
2821
2822 /**
2823  * DPDK callback to retrieve names of extended device statistics
2824  *
2825  * @param dev
2826  *   Pointer to Ethernet device structure.
2827  * @param[out] xstats_names
2828  *   Buffer to insert names into.
2829  * @param n
2830  *   Number of names.
2831  *
2832  * @return
2833  *   Number of xstats names.
2834  */
2835 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2836                                 struct rte_eth_xstat_name *xstats_names,
2837                                 unsigned int n)
2838 {
2839         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2840         unsigned int stat, i, count = 0;
2841
2842         if (n < xstats_count || !xstats_names)
2843                 return xstats_count;
2844
2845         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2846                 strcpy(xstats_names[count].name,
2847                         ena_stats_global_strings[stat].name);
2848
2849         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2850                 strcpy(xstats_names[count].name,
2851                         ena_stats_eni_strings[stat].name);
2852
2853         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2854                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2855                         snprintf(xstats_names[count].name,
2856                                 sizeof(xstats_names[count].name),
2857                                 "rx_q%d_%s", i,
2858                                 ena_stats_rx_strings[stat].name);
2859
2860         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2861                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2862                         snprintf(xstats_names[count].name,
2863                                 sizeof(xstats_names[count].name),
2864                                 "tx_q%d_%s", i,
2865                                 ena_stats_tx_strings[stat].name);
2866
2867         return xstats_count;
2868 }
2869
2870 /**
2871  * DPDK callback to get extended device statistics.
2872  *
2873  * @param dev
2874  *   Pointer to Ethernet device structure.
2875  * @param[out] stats
2876  *   Stats table output buffer.
2877  * @param n
2878  *   The size of the stats table.
2879  *
2880  * @return
2881  *   Number of xstats on success, negative on failure.
2882  */
2883 static int ena_xstats_get(struct rte_eth_dev *dev,
2884                           struct rte_eth_xstat *xstats,
2885                           unsigned int n)
2886 {
2887         struct ena_adapter *adapter = dev->data->dev_private;
2888         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2889         unsigned int stat, i, count = 0;
2890         int stat_offset;
2891         void *stats_begin;
2892
2893         if (n < xstats_count)
2894                 return xstats_count;
2895
2896         if (!xstats)
2897                 return 0;
2898
2899         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2900                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2901                 stats_begin = &adapter->dev_stats;
2902
2903                 xstats[count].id = count;
2904                 xstats[count].value = *((uint64_t *)
2905                         ((char *)stats_begin + stat_offset));
2906         }
2907
2908         /* Even if the function below fails, we should copy previous (or initial
2909          * values) to keep structure of rte_eth_xstat consistent.
2910          */
2911         ena_copy_eni_stats(adapter);
2912         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2913                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2914                 stats_begin = &adapter->eni_stats;
2915
2916                 xstats[count].id = count;
2917                 xstats[count].value = *((uint64_t *)
2918                     ((char *)stats_begin + stat_offset));
2919         }
2920
2921         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2922                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2923                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2924                         stats_begin = &adapter->rx_ring[i].rx_stats;
2925
2926                         xstats[count].id = count;
2927                         xstats[count].value = *((uint64_t *)
2928                                 ((char *)stats_begin + stat_offset));
2929                 }
2930         }
2931
2932         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2933                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2934                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2935                         stats_begin = &adapter->tx_ring[i].rx_stats;
2936
2937                         xstats[count].id = count;
2938                         xstats[count].value = *((uint64_t *)
2939                                 ((char *)stats_begin + stat_offset));
2940                 }
2941         }
2942
2943         return count;
2944 }
2945
2946 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2947                                 const uint64_t *ids,
2948                                 uint64_t *values,
2949                                 unsigned int n)
2950 {
2951         struct ena_adapter *adapter = dev->data->dev_private;
2952         uint64_t id;
2953         uint64_t rx_entries, tx_entries;
2954         unsigned int i;
2955         int qid;
2956         int valid = 0;
2957         bool was_eni_copied = false;
2958
2959         for (i = 0; i < n; ++i) {
2960                 id = ids[i];
2961                 /* Check if id belongs to global statistics */
2962                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2963                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2964                         ++valid;
2965                         continue;
2966                 }
2967
2968                 /* Check if id belongs to ENI statistics */
2969                 id -= ENA_STATS_ARRAY_GLOBAL;
2970                 if (id < ENA_STATS_ARRAY_ENI) {
2971                         /* Avoid reading ENI stats multiple times in a single
2972                          * function call, as it requires communication with the
2973                          * admin queue.
2974                          */
2975                         if (!was_eni_copied) {
2976                                 was_eni_copied = true;
2977                                 ena_copy_eni_stats(adapter);
2978                         }
2979                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2980                         ++valid;
2981                         continue;
2982                 }
2983
2984                 /* Check if id belongs to rx queue statistics */
2985                 id -= ENA_STATS_ARRAY_ENI;
2986                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2987                 if (id < rx_entries) {
2988                         qid = id % dev->data->nb_rx_queues;
2989                         id /= dev->data->nb_rx_queues;
2990                         values[i] = *((uint64_t *)
2991                                 &adapter->rx_ring[qid].rx_stats + id);
2992                         ++valid;
2993                         continue;
2994                 }
2995                                 /* Check if id belongs to rx queue statistics */
2996                 id -= rx_entries;
2997                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2998                 if (id < tx_entries) {
2999                         qid = id % dev->data->nb_tx_queues;
3000                         id /= dev->data->nb_tx_queues;
3001                         values[i] = *((uint64_t *)
3002                                 &adapter->tx_ring[qid].tx_stats + id);
3003                         ++valid;
3004                         continue;
3005                 }
3006         }
3007
3008         return valid;
3009 }
3010
3011 static int ena_process_bool_devarg(const char *key,
3012                                    const char *value,
3013                                    void *opaque)
3014 {
3015         struct ena_adapter *adapter = opaque;
3016         bool bool_value;
3017
3018         /* Parse the value. */
3019         if (strcmp(value, "1") == 0) {
3020                 bool_value = true;
3021         } else if (strcmp(value, "0") == 0) {
3022                 bool_value = false;
3023         } else {
3024                 PMD_INIT_LOG(ERR,
3025                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3026                         value, key);
3027                 return -EINVAL;
3028         }
3029
3030         /* Now, assign it to the proper adapter field. */
3031         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3032                 adapter->use_large_llq_hdr = bool_value;
3033
3034         return 0;
3035 }
3036
3037 static int ena_parse_devargs(struct ena_adapter *adapter,
3038                              struct rte_devargs *devargs)
3039 {
3040         static const char * const allowed_args[] = {
3041                 ENA_DEVARG_LARGE_LLQ_HDR,
3042                 NULL,
3043         };
3044         struct rte_kvargs *kvlist;
3045         int rc;
3046
3047         if (devargs == NULL)
3048                 return 0;
3049
3050         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3051         if (kvlist == NULL) {
3052                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3053                         devargs->args);
3054                 return -EINVAL;
3055         }
3056
3057         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3058                 ena_process_bool_devarg, adapter);
3059
3060         rte_kvargs_free(kvlist);
3061
3062         return rc;
3063 }
3064
3065 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3066 {
3067         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3068         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3069         int rc;
3070         uint16_t vectors_nb, i;
3071         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3072
3073         if (!rx_intr_requested)
3074                 return 0;
3075
3076         if (!rte_intr_cap_multiple(intr_handle)) {
3077                 PMD_DRV_LOG(ERR,
3078                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3079                 return -ENOTSUP;
3080         }
3081
3082         /* Disable interrupt mapping before the configuration starts. */
3083         rte_intr_disable(intr_handle);
3084
3085         /* Verify if there are enough vectors available. */
3086         vectors_nb = dev->data->nb_rx_queues;
3087         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3088                 PMD_DRV_LOG(ERR,
3089                         "Too many Rx interrupts requested, maximum number: %d\n",
3090                         RTE_MAX_RXTX_INTR_VEC_ID);
3091                 rc = -ENOTSUP;
3092                 goto enable_intr;
3093         }
3094
3095         /* Allocate the vector list */
3096         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3097                                            dev->data->nb_rx_queues)) {
3098                 PMD_DRV_LOG(ERR,
3099                         "Failed to allocate interrupt vector for %d queues\n",
3100                         dev->data->nb_rx_queues);
3101                 rc = -ENOMEM;
3102                 goto enable_intr;
3103         }
3104
3105         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3106         if (rc != 0)
3107                 goto free_intr_vec;
3108
3109         if (!rte_intr_allow_others(intr_handle)) {
3110                 PMD_DRV_LOG(ERR,
3111                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3112                 goto disable_intr_efd;
3113         }
3114
3115         for (i = 0; i < vectors_nb; ++i)
3116                 if (rte_intr_vec_list_index_set(intr_handle, i,
3117                                            RTE_INTR_VEC_RXTX_OFFSET + i))
3118                         goto disable_intr_efd;
3119
3120         rte_intr_enable(intr_handle);
3121         return 0;
3122
3123 disable_intr_efd:
3124         rte_intr_efd_disable(intr_handle);
3125 free_intr_vec:
3126         rte_intr_vec_list_free(intr_handle);
3127 enable_intr:
3128         rte_intr_enable(intr_handle);
3129         return rc;
3130 }
3131
3132 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3133                                  uint16_t queue_id,
3134                                  bool unmask)
3135 {
3136         struct ena_adapter *adapter = dev->data->dev_private;
3137         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3138         struct ena_eth_io_intr_reg intr_reg;
3139
3140         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3141         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3142 }
3143
3144 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3145                                     uint16_t queue_id)
3146 {
3147         ena_rx_queue_intr_set(dev, queue_id, true);
3148
3149         return 0;
3150 }
3151
3152 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3153                                      uint16_t queue_id)
3154 {
3155         ena_rx_queue_intr_set(dev, queue_id, false);
3156
3157         return 0;
3158 }
3159
3160 /*********************************************************************
3161  *  PMD configuration
3162  *********************************************************************/
3163 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3164         struct rte_pci_device *pci_dev)
3165 {
3166         return rte_eth_dev_pci_generic_probe(pci_dev,
3167                 sizeof(struct ena_adapter), eth_ena_dev_init);
3168 }
3169
3170 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3171 {
3172         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3173 }
3174
3175 static struct rte_pci_driver rte_ena_pmd = {
3176         .id_table = pci_id_ena_map,
3177         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3178                      RTE_PCI_DRV_WC_ACTIVATE,
3179         .probe = eth_ena_pci_probe,
3180         .remove = eth_ena_pci_remove,
3181 };
3182
3183 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3184 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3185 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3186 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3187 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3188 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3189 #ifdef RTE_ETHDEV_DEBUG_RX
3190 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3191 #endif
3192 #ifdef RTE_ETHDEV_DEBUG_TX
3193 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3194 #endif
3195 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3196
3197 /******************************************************************************
3198  ******************************** AENQ Handlers *******************************
3199  *****************************************************************************/
3200 static void ena_update_on_link_change(void *adapter_data,
3201                                       struct ena_admin_aenq_entry *aenq_e)
3202 {
3203         struct rte_eth_dev *eth_dev = adapter_data;
3204         struct ena_adapter *adapter = eth_dev->data->dev_private;
3205         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3206         uint32_t status;
3207
3208         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3209
3210         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3211         adapter->link_status = status;
3212
3213         ena_link_update(eth_dev, 0);
3214         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3215 }
3216
3217 static void ena_notification(void *adapter_data,
3218                              struct ena_admin_aenq_entry *aenq_e)
3219 {
3220         struct rte_eth_dev *eth_dev = adapter_data;
3221         struct ena_adapter *adapter = eth_dev->data->dev_private;
3222         struct ena_admin_ena_hw_hints *hints;
3223
3224         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3225                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3226                         aenq_e->aenq_common_desc.group,
3227                         ENA_ADMIN_NOTIFICATION);
3228
3229         switch (aenq_e->aenq_common_desc.syndrome) {
3230         case ENA_ADMIN_UPDATE_HINTS:
3231                 hints = (struct ena_admin_ena_hw_hints *)
3232                         (&aenq_e->inline_data_w4);
3233                 ena_update_hints(adapter, hints);
3234                 break;
3235         default:
3236                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3237                         aenq_e->aenq_common_desc.syndrome);
3238         }
3239 }
3240
3241 static void ena_keep_alive(void *adapter_data,
3242                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3243 {
3244         struct rte_eth_dev *eth_dev = adapter_data;
3245         struct ena_adapter *adapter = eth_dev->data->dev_private;
3246         struct ena_admin_aenq_keep_alive_desc *desc;
3247         uint64_t rx_drops;
3248         uint64_t tx_drops;
3249
3250         adapter->timestamp_wd = rte_get_timer_cycles();
3251
3252         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3253         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3254         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3255
3256         adapter->drv_stats->rx_drops = rx_drops;
3257         adapter->dev_stats.tx_drops = tx_drops;
3258 }
3259
3260 /**
3261  * This handler will called for unknown event group or unimplemented handlers
3262  **/
3263 static void unimplemented_aenq_handler(__rte_unused void *data,
3264                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3265 {
3266         PMD_DRV_LOG(ERR,
3267                 "Unknown event was received or event with unimplemented handler\n");
3268 }
3269
3270 static struct ena_aenq_handlers aenq_handlers = {
3271         .handlers = {
3272                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3273                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3274                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3275         },
3276         .unimplemented_handler = unimplemented_aenq_handler
3277 };