1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
9 #include <rte_atomic.h>
10 #include <rte_ether.h>
11 #include <ethdev_driver.h>
12 #include <ethdev_pci.h>
13 #include <rte_cycles.h>
15 #include <rte_bus_pci.h>
16 #include <rte_timer.h>
22 #define ENA_REGS_BAR 0
25 #define ENA_MAX_NUM_QUEUES 128
26 #define ENA_MIN_FRAME_LEN 64
27 #define ENA_NAME_MAX_LEN 20
28 #define ENA_PKT_MAX_BUFS 17
29 #define ENA_RX_BUF_MIN_SIZE 1400
30 #define ENA_DEFAULT_RING_SIZE 1024
32 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
33 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
35 #define ENA_MIN_MTU 128
37 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
39 #define ENA_WD_TIMEOUT_SEC 3
40 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
42 #define ENA_TX_TIMEOUT (5 * rte_get_timer_hz())
43 #define ENA_MONITORED_TX_QUEUES 3
44 #define ENA_DEFAULT_MISSING_COMP 256U
46 /* While processing submitted and completed descriptors (rx and tx path
47 * respectively) in a loop it is desired to:
48 * - perform batch submissions while populating submission queue
49 * - avoid blocking transmission of other packets during cleanup phase
50 * Hence the utilization ratio of 1/8 of a queue size or max value if the size
51 * of the ring is very big - like 8k Rx rings.
53 #define ENA_REFILL_THRESH_DIVIDER 8
54 #define ENA_REFILL_THRESH_PACKET 256
56 #define ENA_IDX_NEXT_MASKED(idx, mask) (((idx) + 1) & (mask))
57 #define ENA_IDX_ADD_MASKED(idx, n, mask) (((idx) + (n)) & (mask))
59 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
60 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
62 #define ENA_HASH_KEY_SIZE 40
64 #define ENA_ALL_RSS_HF (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
65 RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)
67 #define ENA_IO_TXQ_IDX(q) (2 * (q))
68 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
69 /* Reversed version of ENA_IO_RXQ_IDX */
70 #define ENA_IO_RXQ_IDX_REV(q) (((q) - 1) / 2)
72 extern struct ena_shared_data *ena_shared_data;
81 struct ena_tx_buffer {
82 struct rte_mbuf *mbuf;
83 unsigned int tx_descs;
84 unsigned int num_of_bufs;
87 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
90 /* Rx buffer holds only pointer to the mbuf - may be expanded in the future */
91 struct ena_rx_buffer {
92 struct rte_mbuf *mbuf;
93 struct ena_com_buf ena_buf;
96 struct ena_calc_queue_size_ctx {
97 struct ena_com_dev_get_features_ctx *get_feat_ctx;
98 struct ena_com_dev *ena_dev;
99 u32 max_rx_queue_size;
100 u32 max_tx_queue_size;
105 struct ena_stats_tx {
116 struct ena_stats_rx {
131 uint64_t last_cleanup_ticks;
133 enum ena_ring_type type;
134 enum ena_admin_placement_policy_type tx_mem_queue_type;
136 /* Indicate there are Tx packets pushed to the device and wait for db */
137 bool pkts_without_db;
139 /* Holds the empty requests for TX/RX OOO completions */
141 uint16_t *empty_tx_reqs;
142 uint16_t *empty_rx_reqs;
146 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
147 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
149 struct rte_mbuf **rx_refill_buffer;
150 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
151 unsigned int size_mask;
153 struct ena_com_io_cq *ena_com_io_cq;
154 struct ena_com_io_sq *ena_com_io_sq;
157 uint16_t tx_free_thresh;
158 uint16_t rx_free_thresh;
161 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
164 struct rte_mempool *mb_pool;
165 unsigned int port_id;
167 /* Max length PMD can push to device for LLQ */
168 uint8_t tx_max_header_size;
171 uint8_t *push_buf_intermediate_buf;
173 struct ena_adapter *adapter;
177 bool disable_meta_caching;
180 struct ena_stats_rx rx_stats;
181 struct ena_stats_tx tx_stats;
184 unsigned int numa_socket_id;
186 uint32_t missing_tx_completion_threshold;
187 } __rte_cache_aligned;
189 enum ena_adapter_state {
190 ENA_ADAPTER_STATE_FREE = 0,
191 ENA_ADAPTER_STATE_INIT = 1,
192 ENA_ADAPTER_STATE_RUNNING = 2,
193 ENA_ADAPTER_STATE_STOPPED = 3,
194 ENA_ADAPTER_STATE_CONFIG = 4,
195 ENA_ADAPTER_STATE_CLOSED = 5,
198 struct ena_driver_stats {
199 rte_atomic64_t ierrors;
200 rte_atomic64_t oerrors;
201 rte_atomic64_t rx_nombuf;
205 struct ena_stats_dev {
210 * Tx drops cannot be reported as the driver statistic, because DPDK
211 * rte_eth_stats structure isn't providing appropriate field for that.
212 * As a workaround it is being published as an extended statistic.
217 struct ena_stats_eni {
219 * The number of packets shaped due to inbound aggregate BW
220 * allowance being exceeded
222 uint64_t bw_in_allowance_exceeded;
224 * The number of packets shaped due to outbound aggregate BW
225 * allowance being exceeded
227 uint64_t bw_out_allowance_exceeded;
228 /* The number of packets shaped due to PPS allowance being exceeded */
229 uint64_t pps_allowance_exceeded;
231 * The number of packets shaped due to connection tracking
232 * allowance being exceeded and leading to failure in establishment
235 uint64_t conntrack_allowance_exceeded;
237 * The number of packets shaped due to linklocal packet rate
238 * allowance being exceeded
240 uint64_t linklocal_allowance_exceeded;
243 struct ena_offloads {
244 uint32_t tx_offloads;
245 uint32_t rx_offloads;
248 /* board specific private data structure */
250 /* OS defined structs */
251 struct rte_eth_dev_data *edev_data;
253 struct ena_com_dev ena_dev __rte_cache_aligned;
256 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
257 u32 max_tx_ring_size;
261 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
262 u32 max_rx_ring_size;
265 u32 max_num_io_queues;
267 struct ena_offloads offloads;
269 /* The admin queue isn't protected by the lock and is used to
270 * retrieve statistics from the device. As there is no guarantee that
271 * application won't try to get statistics from multiple threads, it is
272 * safer to lock the queue to avoid admin queue failure.
274 rte_spinlock_t admin_lock;
277 char name[ENA_NAME_MAX_LEN];
278 u8 mac_addr[RTE_ETHER_ADDR_LEN];
283 struct ena_driver_stats *drv_stats;
284 enum ena_adapter_state state;
288 enum ena_regs_reset_reason_types reset_reason;
290 struct rte_timer timer_wd;
291 uint64_t timestamp_wd;
292 uint64_t keep_alive_timeout;
294 struct ena_stats_dev dev_stats;
295 struct ena_stats_eni eni_stats;
296 struct ena_admin_basic_stats basic_stats;
298 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE];
300 uint32_t all_aenq_groups;
301 uint32_t active_aenq_groups;
305 bool use_large_llq_hdr;
307 uint32_t last_tx_comp_qid;
308 uint64_t missing_tx_completion_to;
309 uint64_t missing_tx_completion_budget;
310 uint64_t tx_cleanup_stall_delay;
313 int ena_mp_indirect_table_set(struct ena_adapter *adapter);
314 int ena_mp_indirect_table_get(struct ena_adapter *adapter,
315 uint32_t *indirect_table);
316 int ena_rss_reta_update(struct rte_eth_dev *dev,
317 struct rte_eth_rss_reta_entry64 *reta_conf,
319 int ena_rss_reta_query(struct rte_eth_dev *dev,
320 struct rte_eth_rss_reta_entry64 *reta_conf,
322 int ena_rss_hash_update(struct rte_eth_dev *dev,
323 struct rte_eth_rss_conf *rss_conf);
324 int ena_rss_hash_conf_get(struct rte_eth_dev *dev,
325 struct rte_eth_rss_conf *rss_conf);
326 int ena_rss_configure(struct ena_adapter *adapter);
328 #endif /* _ENA_ETHDEV_H_ */