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34 #ifndef _ENA_ETHDEV_H_
35 #define _ENA_ETHDEV_H_
37 #include <rte_cycles.h>
39 #include <rte_bus_pci.h>
40 #include <rte_timer.h>
44 #define ENA_REGS_BAR 0
47 #define ENA_MAX_NUM_QUEUES 128
48 #define ENA_MIN_FRAME_LEN 64
49 #define ENA_NAME_MAX_LEN 20
50 #define ENA_PKT_MAX_BUFS 17
52 #define ENA_MIN_MTU 128
54 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
56 #define ENA_WD_TIMEOUT_SEC 3
57 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
66 struct ena_tx_buffer {
67 struct rte_mbuf *mbuf;
68 unsigned int tx_descs;
69 unsigned int num_of_bufs;
70 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
73 struct ena_calc_queue_size_ctx {
74 struct ena_com_dev_get_features_ctx *get_feat_ctx;
75 struct ena_com_dev *ena_dev;
108 enum ena_ring_type type;
109 enum ena_admin_placement_policy_type tx_mem_queue_type;
110 /* Holds the empty requests for TX/RX OOO completions */
112 uint16_t *empty_tx_reqs;
113 uint16_t *empty_rx_reqs;
117 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
118 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
120 struct rte_mbuf **rx_refill_buffer;
121 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
123 struct ena_com_io_cq *ena_com_io_cq;
124 struct ena_com_io_sq *ena_com_io_sq;
126 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
129 struct rte_mempool *mb_pool;
130 unsigned int port_id;
132 /* Max length PMD can push to device for LLQ */
133 uint8_t tx_max_header_size;
136 uint8_t *push_buf_intermediate_buf;
138 struct ena_adapter *adapter;
143 struct ena_stats_rx rx_stats;
144 struct ena_stats_tx tx_stats;
146 } __rte_cache_aligned;
148 enum ena_adapter_state {
149 ENA_ADAPTER_STATE_FREE = 0,
150 ENA_ADAPTER_STATE_INIT = 1,
151 ENA_ADAPTER_STATE_RUNNING = 2,
152 ENA_ADAPTER_STATE_STOPPED = 3,
153 ENA_ADAPTER_STATE_CONFIG = 4,
154 ENA_ADAPTER_STATE_CLOSED = 5,
157 struct ena_driver_stats {
158 rte_atomic64_t ierrors;
159 rte_atomic64_t oerrors;
160 rte_atomic64_t rx_nombuf;
161 rte_atomic64_t rx_drops;
164 struct ena_stats_dev {
170 struct ena_offloads {
172 bool tx_csum_supported;
173 bool rx_csum_supported;
176 /* board specific private data structure */
178 /* OS defined structs */
179 struct rte_pci_device *pdev;
180 struct rte_eth_dev_data *rte_eth_dev_data;
181 struct rte_eth_dev *rte_dev;
183 struct ena_com_dev ena_dev __rte_cache_aligned;
186 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
191 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
197 struct ena_offloads offloads;
200 char name[ENA_NAME_MAX_LEN];
201 u8 mac_addr[ETHER_ADDR_LEN];
206 struct ena_driver_stats *drv_stats;
207 enum ena_adapter_state state;
209 uint64_t tx_supported_offloads;
210 uint64_t tx_selected_offloads;
211 uint64_t rx_supported_offloads;
212 uint64_t rx_selected_offloads;
216 enum ena_regs_reset_reason_types reset_reason;
218 struct rte_timer timer_wd;
219 uint64_t timestamp_wd;
220 uint64_t keep_alive_timeout;
222 struct ena_stats_dev dev_stats;
229 #endif /* _ENA_ETHDEV_H_ */