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34 #ifndef _ENA_ETHDEV_H_
35 #define _ENA_ETHDEV_H_
37 #include <rte_cycles.h>
39 #include <rte_bus_pci.h>
40 #include <rte_timer.h>
44 #define ENA_REGS_BAR 0
47 #define ENA_MAX_NUM_QUEUES 128
48 #define ENA_DEFAULT_RING_SIZE (1024)
49 #define ENA_MIN_FRAME_LEN 64
50 #define ENA_NAME_MAX_LEN 20
51 #define ENA_PKT_MAX_BUFS 17
53 #define ENA_MIN_MTU 128
55 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
57 #define ENA_WD_TIMEOUT_SEC 3
58 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
67 struct ena_tx_buffer {
68 struct rte_mbuf *mbuf;
69 unsigned int tx_descs;
70 unsigned int num_of_bufs;
71 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
78 enum ena_ring_type type;
79 enum ena_admin_placement_policy_type tx_mem_queue_type;
80 /* Holds the empty requests for TX/RX OOO completions */
82 uint16_t *empty_tx_reqs;
83 uint16_t *empty_rx_reqs;
87 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
88 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
90 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
92 struct ena_com_io_cq *ena_com_io_cq;
93 struct ena_com_io_sq *ena_com_io_sq;
95 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
98 struct rte_mempool *mb_pool;
101 /* Max length PMD can push to device for LLQ */
102 uint8_t tx_max_header_size;
104 struct ena_adapter *adapter;
107 } __rte_cache_aligned;
109 enum ena_adapter_state {
110 ENA_ADAPTER_STATE_FREE = 0,
111 ENA_ADAPTER_STATE_INIT = 1,
112 ENA_ADAPTER_STATE_RUNNING = 2,
113 ENA_ADAPTER_STATE_STOPPED = 3,
114 ENA_ADAPTER_STATE_CONFIG = 4,
115 ENA_ADAPTER_STATE_CLOSED = 5,
118 struct ena_driver_stats {
119 rte_atomic64_t ierrors;
120 rte_atomic64_t oerrors;
121 rte_atomic64_t rx_nombuf;
124 struct ena_stats_dev {
134 struct ena_stats_tx {
142 u64 linearize_failed;
149 struct ena_stats_rx {
158 u64 small_copy_len_pkt;
161 /* board specific private data structure */
163 /* OS defined structs */
164 struct rte_pci_device *pdev;
165 struct rte_eth_dev_data *rte_eth_dev_data;
166 struct rte_eth_dev *rte_dev;
168 struct ena_com_dev ena_dev __rte_cache_aligned;
171 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
176 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
184 char name[ENA_NAME_MAX_LEN];
185 u8 mac_addr[ETHER_ADDR_LEN];
190 struct ena_driver_stats *drv_stats;
191 enum ena_adapter_state state;
193 uint64_t tx_supported_offloads;
194 uint64_t tx_selected_offloads;
195 uint64_t rx_supported_offloads;
196 uint64_t rx_selected_offloads;
200 enum ena_regs_reset_reason_types reset_reason;
202 struct rte_timer timer_wd;
203 uint64_t timestamp_wd;
204 uint64_t keep_alive_timeout;
211 #endif /* _ENA_ETHDEV_H_ */