1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
9 #include <rte_cycles.h>
11 #include <rte_bus_pci.h>
12 #include <rte_timer.h>
16 #define ENA_REGS_BAR 0
19 #define ENA_MAX_NUM_QUEUES 128
20 #define ENA_MIN_FRAME_LEN 64
21 #define ENA_NAME_MAX_LEN 20
22 #define ENA_PKT_MAX_BUFS 17
23 #define ENA_RX_BUF_MIN_SIZE 1400
24 #define ENA_DEFAULT_RING_SIZE 1024
26 #define ENA_MIN_MTU 128
28 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
30 #define ENA_WD_TIMEOUT_SEC 3
31 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
40 struct ena_tx_buffer {
41 struct rte_mbuf *mbuf;
42 unsigned int tx_descs;
43 unsigned int num_of_bufs;
44 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
47 struct ena_calc_queue_size_ctx {
48 struct ena_com_dev_get_features_ctx *get_feat_ctx;
49 struct ena_com_dev *ena_dev;
50 u32 max_rx_queue_size;
51 u32 max_tx_queue_size;
82 enum ena_ring_type type;
83 enum ena_admin_placement_policy_type tx_mem_queue_type;
84 /* Holds the empty requests for TX/RX OOO completions */
86 uint16_t *empty_tx_reqs;
87 uint16_t *empty_rx_reqs;
91 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
92 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
94 struct rte_mbuf **rx_refill_buffer;
95 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
97 struct ena_com_io_cq *ena_com_io_cq;
98 struct ena_com_io_sq *ena_com_io_sq;
100 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
103 struct rte_mempool *mb_pool;
104 unsigned int port_id;
106 /* Max length PMD can push to device for LLQ */
107 uint8_t tx_max_header_size;
110 uint8_t *push_buf_intermediate_buf;
112 struct ena_adapter *adapter;
117 struct ena_stats_rx rx_stats;
118 struct ena_stats_tx tx_stats;
121 unsigned int numa_socket_id;
122 } __rte_cache_aligned;
124 enum ena_adapter_state {
125 ENA_ADAPTER_STATE_FREE = 0,
126 ENA_ADAPTER_STATE_INIT = 1,
127 ENA_ADAPTER_STATE_RUNNING = 2,
128 ENA_ADAPTER_STATE_STOPPED = 3,
129 ENA_ADAPTER_STATE_CONFIG = 4,
130 ENA_ADAPTER_STATE_CLOSED = 5,
133 struct ena_driver_stats {
134 rte_atomic64_t ierrors;
135 rte_atomic64_t oerrors;
136 rte_atomic64_t rx_nombuf;
140 struct ena_stats_dev {
145 * Tx drops cannot be reported as the driver statistic, because DPDK
146 * rte_eth_stats structure isn't providing appropriate field for that.
147 * As a workaround it is being published as an extended statistic.
152 struct ena_offloads {
154 bool tx_csum_supported;
155 bool rx_csum_supported;
158 /* board specific private data structure */
160 /* OS defined structs */
161 struct rte_pci_device *pdev;
162 struct rte_eth_dev_data *rte_eth_dev_data;
163 struct rte_eth_dev *rte_dev;
165 struct ena_com_dev ena_dev __rte_cache_aligned;
168 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
169 u32 max_tx_ring_size;
173 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
174 u32 max_rx_ring_size;
177 u32 max_num_io_queues;
179 struct ena_offloads offloads;
182 char name[ENA_NAME_MAX_LEN];
183 u8 mac_addr[RTE_ETHER_ADDR_LEN];
188 struct ena_driver_stats *drv_stats;
189 enum ena_adapter_state state;
191 uint64_t tx_supported_offloads;
192 uint64_t tx_selected_offloads;
193 uint64_t rx_supported_offloads;
194 uint64_t rx_selected_offloads;
198 enum ena_regs_reset_reason_types reset_reason;
200 struct rte_timer timer_wd;
201 uint64_t timestamp_wd;
202 uint64_t keep_alive_timeout;
204 struct ena_stats_dev dev_stats;
210 bool use_large_llq_hdr;
213 #endif /* _ENA_ETHDEV_H_ */