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34 #ifndef _ENA_ETHDEV_H_
35 #define _ENA_ETHDEV_H_
37 #include <rte_cycles.h>
39 #include <rte_bus_pci.h>
40 #include <rte_timer.h>
44 #define ENA_REGS_BAR 0
47 #define ENA_MAX_NUM_QUEUES 128
48 #define ENA_MIN_FRAME_LEN 64
49 #define ENA_NAME_MAX_LEN 20
50 #define ENA_PKT_MAX_BUFS 17
52 #define ENA_MIN_MTU 128
54 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
56 #define ENA_WD_TIMEOUT_SEC 3
57 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
66 struct ena_tx_buffer {
67 struct rte_mbuf *mbuf;
68 unsigned int tx_descs;
69 unsigned int num_of_bufs;
70 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
73 struct ena_calc_queue_size_ctx {
74 struct ena_com_dev_get_features_ctx *get_feat_ctx;
75 struct ena_com_dev *ena_dev;
86 enum ena_ring_type type;
87 enum ena_admin_placement_policy_type tx_mem_queue_type;
88 /* Holds the empty requests for TX/RX OOO completions */
90 uint16_t *empty_tx_reqs;
91 uint16_t *empty_rx_reqs;
95 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
96 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
98 struct rte_mbuf **rx_refill_buffer;
99 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
101 struct ena_com_io_cq *ena_com_io_cq;
102 struct ena_com_io_sq *ena_com_io_sq;
104 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
107 struct rte_mempool *mb_pool;
108 unsigned int port_id;
110 /* Max length PMD can push to device for LLQ */
111 uint8_t tx_max_header_size;
114 uint8_t *push_buf_intermediate_buf;
116 struct ena_adapter *adapter;
119 } __rte_cache_aligned;
121 enum ena_adapter_state {
122 ENA_ADAPTER_STATE_FREE = 0,
123 ENA_ADAPTER_STATE_INIT = 1,
124 ENA_ADAPTER_STATE_RUNNING = 2,
125 ENA_ADAPTER_STATE_STOPPED = 3,
126 ENA_ADAPTER_STATE_CONFIG = 4,
127 ENA_ADAPTER_STATE_CLOSED = 5,
130 struct ena_driver_stats {
131 rte_atomic64_t ierrors;
132 rte_atomic64_t oerrors;
133 rte_atomic64_t rx_nombuf;
136 struct ena_stats_dev {
146 struct ena_stats_tx {
154 u64 linearize_failed;
161 struct ena_stats_rx {
170 u64 small_copy_len_pkt;
173 /* board specific private data structure */
175 /* OS defined structs */
176 struct rte_pci_device *pdev;
177 struct rte_eth_dev_data *rte_eth_dev_data;
178 struct rte_eth_dev *rte_dev;
180 struct ena_com_dev ena_dev __rte_cache_aligned;
183 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
188 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
197 char name[ENA_NAME_MAX_LEN];
198 u8 mac_addr[ETHER_ADDR_LEN];
203 struct ena_driver_stats *drv_stats;
204 enum ena_adapter_state state;
206 uint64_t tx_supported_offloads;
207 uint64_t tx_selected_offloads;
208 uint64_t rx_supported_offloads;
209 uint64_t rx_selected_offloads;
213 enum ena_regs_reset_reason_types reset_reason;
215 struct rte_timer timer_wd;
216 uint64_t timestamp_wd;
217 uint64_t keep_alive_timeout;
224 #endif /* _ENA_ETHDEV_H_ */