1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
9 #include <rte_cycles.h>
11 #include <rte_bus_pci.h>
12 #include <rte_timer.h>
16 #define ENA_REGS_BAR 0
19 #define ENA_MAX_NUM_QUEUES 128
20 #define ENA_MIN_FRAME_LEN 64
21 #define ENA_NAME_MAX_LEN 20
22 #define ENA_PKT_MAX_BUFS 17
24 #define ENA_MIN_MTU 128
26 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
28 #define ENA_WD_TIMEOUT_SEC 3
29 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
38 struct ena_tx_buffer {
39 struct rte_mbuf *mbuf;
40 unsigned int tx_descs;
41 unsigned int num_of_bufs;
42 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
45 struct ena_calc_queue_size_ctx {
46 struct ena_com_dev_get_features_ctx *get_feat_ctx;
47 struct ena_com_dev *ena_dev;
80 enum ena_ring_type type;
81 enum ena_admin_placement_policy_type tx_mem_queue_type;
82 /* Holds the empty requests for TX/RX OOO completions */
84 uint16_t *empty_tx_reqs;
85 uint16_t *empty_rx_reqs;
89 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
90 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
92 struct rte_mbuf **rx_refill_buffer;
93 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
95 struct ena_com_io_cq *ena_com_io_cq;
96 struct ena_com_io_sq *ena_com_io_sq;
98 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
101 struct rte_mempool *mb_pool;
102 unsigned int port_id;
104 /* Max length PMD can push to device for LLQ */
105 uint8_t tx_max_header_size;
108 uint8_t *push_buf_intermediate_buf;
110 struct ena_adapter *adapter;
115 struct ena_stats_rx rx_stats;
116 struct ena_stats_tx tx_stats;
119 unsigned int numa_socket_id;
120 } __rte_cache_aligned;
122 enum ena_adapter_state {
123 ENA_ADAPTER_STATE_FREE = 0,
124 ENA_ADAPTER_STATE_INIT = 1,
125 ENA_ADAPTER_STATE_RUNNING = 2,
126 ENA_ADAPTER_STATE_STOPPED = 3,
127 ENA_ADAPTER_STATE_CONFIG = 4,
128 ENA_ADAPTER_STATE_CLOSED = 5,
131 struct ena_driver_stats {
132 rte_atomic64_t ierrors;
133 rte_atomic64_t oerrors;
134 rte_atomic64_t rx_nombuf;
135 rte_atomic64_t rx_drops;
138 struct ena_stats_dev {
144 struct ena_offloads {
146 bool tx_csum_supported;
147 bool rx_csum_supported;
150 /* board specific private data structure */
152 /* OS defined structs */
153 struct rte_pci_device *pdev;
154 struct rte_eth_dev_data *rte_eth_dev_data;
155 struct rte_eth_dev *rte_dev;
157 struct ena_com_dev ena_dev __rte_cache_aligned;
160 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
165 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
171 struct ena_offloads offloads;
174 char name[ENA_NAME_MAX_LEN];
175 u8 mac_addr[RTE_ETHER_ADDR_LEN];
180 struct ena_driver_stats *drv_stats;
181 enum ena_adapter_state state;
183 uint64_t tx_supported_offloads;
184 uint64_t tx_selected_offloads;
185 uint64_t rx_supported_offloads;
186 uint64_t rx_selected_offloads;
190 enum ena_regs_reset_reason_types reset_reason;
192 struct rte_timer timer_wd;
193 uint64_t timestamp_wd;
194 uint64_t keep_alive_timeout;
196 struct ena_stats_dev dev_stats;
203 #endif /* _ENA_ETHDEV_H_ */