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34 #ifndef _ENA_ETHDEV_H_
35 #define _ENA_ETHDEV_H_
37 #include <rte_cycles.h>
39 #include <rte_bus_pci.h>
40 #include <rte_timer.h>
44 #define ENA_REGS_BAR 0
47 #define ENA_MAX_NUM_QUEUES 128
48 #define ENA_DEFAULT_RING_SIZE (1024)
49 #define ENA_MIN_FRAME_LEN 64
50 #define ENA_NAME_MAX_LEN 20
51 #define ENA_PKT_MAX_BUFS 17
53 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
55 #define ENA_WD_TIMEOUT_SEC 3
56 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
65 struct ena_tx_buffer {
66 struct rte_mbuf *mbuf;
67 unsigned int tx_descs;
68 unsigned int num_of_bufs;
69 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
76 enum ena_ring_type type;
77 enum ena_admin_placement_policy_type tx_mem_queue_type;
78 /* Holds the empty requests for TX OOO completions */
79 uint16_t *empty_tx_reqs;
81 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
82 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
84 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
86 struct ena_com_io_cq *ena_com_io_cq;
87 struct ena_com_io_sq *ena_com_io_sq;
89 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
92 struct rte_mempool *mb_pool;
95 /* Max length PMD can push to device for LLQ */
96 uint8_t tx_max_header_size;
98 struct ena_adapter *adapter;
100 } __rte_cache_aligned;
102 enum ena_adapter_state {
103 ENA_ADAPTER_STATE_FREE = 0,
104 ENA_ADAPTER_STATE_INIT = 1,
105 ENA_ADAPTER_STATE_RUNNING = 2,
106 ENA_ADAPTER_STATE_STOPPED = 3,
107 ENA_ADAPTER_STATE_CONFIG = 4,
108 ENA_ADAPTER_STATE_CLOSED = 5,
111 struct ena_driver_stats {
112 rte_atomic64_t ierrors;
113 rte_atomic64_t oerrors;
114 rte_atomic64_t rx_nombuf;
117 struct ena_stats_dev {
127 struct ena_stats_tx {
135 u64 linearize_failed;
142 struct ena_stats_rx {
151 u64 small_copy_len_pkt;
154 /* board specific private data structure */
156 /* OS defined structs */
157 struct rte_pci_device *pdev;
158 struct rte_eth_dev_data *rte_eth_dev_data;
159 struct rte_eth_dev *rte_dev;
161 struct ena_com_dev ena_dev __rte_cache_aligned;
164 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
168 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
176 char name[ENA_NAME_MAX_LEN];
177 u8 mac_addr[ETHER_ADDR_LEN];
182 struct ena_driver_stats *drv_stats;
183 enum ena_adapter_state state;
185 uint64_t tx_supported_offloads;
186 uint64_t tx_selected_offloads;
187 uint64_t rx_supported_offloads;
188 uint64_t rx_selected_offloads;
192 enum ena_regs_reset_reason_types reset_reason;
194 struct rte_timer timer_wd;
195 uint64_t timestamp_wd;
196 uint64_t keep_alive_timeout;
199 #endif /* _ENA_ETHDEV_H_ */