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34 #ifndef _ENA_ETHDEV_H_
35 #define _ENA_ETHDEV_H_
37 #include <rte_cycles.h>
39 #include <rte_bus_pci.h>
40 #include <rte_timer.h>
44 #define ENA_REGS_BAR 0
47 #define ENA_MAX_NUM_QUEUES 128
48 #define ENA_DEFAULT_RING_SIZE (1024)
49 #define ENA_MIN_FRAME_LEN 64
50 #define ENA_NAME_MAX_LEN 20
51 #define ENA_PKT_MAX_BUFS 17
53 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
55 #define ENA_WD_TIMEOUT_SEC 3
56 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
65 struct ena_tx_buffer {
66 struct rte_mbuf *mbuf;
67 unsigned int tx_descs;
68 unsigned int num_of_bufs;
69 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
76 enum ena_ring_type type;
77 enum ena_admin_placement_policy_type tx_mem_queue_type;
78 /* Holds the empty requests for TX/RX OOO completions */
80 uint16_t *empty_tx_reqs;
81 uint16_t *empty_rx_reqs;
85 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
86 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
88 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
90 struct ena_com_io_cq *ena_com_io_cq;
91 struct ena_com_io_sq *ena_com_io_sq;
93 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
96 struct rte_mempool *mb_pool;
99 /* Max length PMD can push to device for LLQ */
100 uint8_t tx_max_header_size;
102 struct ena_adapter *adapter;
104 } __rte_cache_aligned;
106 enum ena_adapter_state {
107 ENA_ADAPTER_STATE_FREE = 0,
108 ENA_ADAPTER_STATE_INIT = 1,
109 ENA_ADAPTER_STATE_RUNNING = 2,
110 ENA_ADAPTER_STATE_STOPPED = 3,
111 ENA_ADAPTER_STATE_CONFIG = 4,
112 ENA_ADAPTER_STATE_CLOSED = 5,
115 struct ena_driver_stats {
116 rte_atomic64_t ierrors;
117 rte_atomic64_t oerrors;
118 rte_atomic64_t rx_nombuf;
121 struct ena_stats_dev {
131 struct ena_stats_tx {
139 u64 linearize_failed;
146 struct ena_stats_rx {
155 u64 small_copy_len_pkt;
158 /* board specific private data structure */
160 /* OS defined structs */
161 struct rte_pci_device *pdev;
162 struct rte_eth_dev_data *rte_eth_dev_data;
163 struct rte_eth_dev *rte_dev;
165 struct ena_com_dev ena_dev __rte_cache_aligned;
168 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
172 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
180 char name[ENA_NAME_MAX_LEN];
181 u8 mac_addr[ETHER_ADDR_LEN];
186 struct ena_driver_stats *drv_stats;
187 enum ena_adapter_state state;
189 uint64_t tx_supported_offloads;
190 uint64_t tx_selected_offloads;
191 uint64_t rx_supported_offloads;
192 uint64_t rx_selected_offloads;
196 enum ena_regs_reset_reason_types reset_reason;
198 struct rte_timer timer_wd;
199 uint64_t timestamp_wd;
200 uint64_t keep_alive_timeout;
207 #endif /* _ENA_ETHDEV_H_ */