1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
9 #include <rte_cycles.h>
11 #include <rte_bus_pci.h>
12 #include <rte_timer.h>
16 #define ENA_REGS_BAR 0
19 #define ENA_MAX_NUM_QUEUES 128
20 #define ENA_MIN_FRAME_LEN 64
21 #define ENA_NAME_MAX_LEN 20
22 #define ENA_PKT_MAX_BUFS 17
23 #define ENA_RX_BUF_MIN_SIZE 1400
25 #define ENA_MIN_MTU 128
27 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
29 #define ENA_WD_TIMEOUT_SEC 3
30 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
39 struct ena_tx_buffer {
40 struct rte_mbuf *mbuf;
41 unsigned int tx_descs;
42 unsigned int num_of_bufs;
43 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
46 struct ena_calc_queue_size_ctx {
47 struct ena_com_dev_get_features_ctx *get_feat_ctx;
48 struct ena_com_dev *ena_dev;
81 enum ena_ring_type type;
82 enum ena_admin_placement_policy_type tx_mem_queue_type;
83 /* Holds the empty requests for TX/RX OOO completions */
85 uint16_t *empty_tx_reqs;
86 uint16_t *empty_rx_reqs;
90 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
91 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
93 struct rte_mbuf **rx_refill_buffer;
94 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
96 struct ena_com_io_cq *ena_com_io_cq;
97 struct ena_com_io_sq *ena_com_io_sq;
99 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
102 struct rte_mempool *mb_pool;
103 unsigned int port_id;
105 /* Max length PMD can push to device for LLQ */
106 uint8_t tx_max_header_size;
109 uint8_t *push_buf_intermediate_buf;
111 struct ena_adapter *adapter;
116 struct ena_stats_rx rx_stats;
117 struct ena_stats_tx tx_stats;
120 unsigned int numa_socket_id;
121 } __rte_cache_aligned;
123 enum ena_adapter_state {
124 ENA_ADAPTER_STATE_FREE = 0,
125 ENA_ADAPTER_STATE_INIT = 1,
126 ENA_ADAPTER_STATE_RUNNING = 2,
127 ENA_ADAPTER_STATE_STOPPED = 3,
128 ENA_ADAPTER_STATE_CONFIG = 4,
129 ENA_ADAPTER_STATE_CLOSED = 5,
132 struct ena_driver_stats {
133 rte_atomic64_t ierrors;
134 rte_atomic64_t oerrors;
135 rte_atomic64_t rx_nombuf;
136 rte_atomic64_t rx_drops;
139 struct ena_stats_dev {
145 struct ena_offloads {
147 bool tx_csum_supported;
148 bool rx_csum_supported;
151 /* board specific private data structure */
153 /* OS defined structs */
154 struct rte_pci_device *pdev;
155 struct rte_eth_dev_data *rte_eth_dev_data;
156 struct rte_eth_dev *rte_dev;
158 struct ena_com_dev ena_dev __rte_cache_aligned;
161 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
166 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
172 struct ena_offloads offloads;
175 char name[ENA_NAME_MAX_LEN];
176 u8 mac_addr[RTE_ETHER_ADDR_LEN];
181 struct ena_driver_stats *drv_stats;
182 enum ena_adapter_state state;
184 uint64_t tx_supported_offloads;
185 uint64_t tx_selected_offloads;
186 uint64_t rx_supported_offloads;
187 uint64_t rx_selected_offloads;
191 enum ena_regs_reset_reason_types reset_reason;
193 struct rte_timer timer_wd;
194 uint64_t timestamp_wd;
195 uint64_t keep_alive_timeout;
197 struct ena_stats_dev dev_stats;
204 #endif /* _ENA_ETHDEV_H_ */