1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2019 NXP
9 #define BIT(x) ((uint64_t)1 << ((x)))
11 /* ENETC device IDs */
12 #define ENETC_DEV_ID_VF 0xef00
13 #define ENETC_DEV_ID 0xe100
15 /* BD RING ALIGNMENT */
16 #define ENETC_BD_RING_ALIGN 128
18 /* ENETC register block BAR */
19 #define ENETC_BAR_REGS 0x0
21 /* SI regs, offset: 0h */
22 #define ENETC_SIMR 0x0
23 #define ENETC_SIMR_EN BIT(31)
25 #define ENETC_SIPMAR0 0x80
26 #define ENETC_SIPMAR1 0x84
28 #define ENETC_SICAPR0 0x900
29 #define ENETC_SICAPR1 0x904
31 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
32 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
34 #define ENETC_SICCAPR 0x1200
36 /* enum for BD type */
37 enum enetc_bdr_type {TX, RX};
39 #define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 \
41 /* RX BDR reg offsets */
42 #define ENETC_RBMR 0x0 /* RX BDR mode register*/
43 #define ENETC_RBMR_EN BIT(31)
45 #define ENETC_RBSR 0x4 /* Rx BDR status register*/
46 #define ENETC_RBBSR 0x8 /* Rx BDR buffer size register*/
47 #define ENETC_RBCIR 0xc /* Rx BDR consumer index register*/
48 #define ENETC_RBBAR0 0x10 /* Rx BDR base address register 0 */
49 #define ENETC_RBBAR1 0x14 /* Rx BDR base address register 1*/
50 #define ENETC_RBPIR 0x18 /* Rx BDR producer index register*/
51 #define ENETC_RBLENR 0x20 /* Rx BDR length register*/
52 #define ENETC_RBIER 0xa0 /* Rx BDR interrupt enable register*/
53 #define ENETC_RBIER_RXTIE BIT(0)
54 #define ENETC_RBIDR 0xa4 /* Rx BDR interrupt detect register*/
55 #define ENETC_RBICIR0 0xa8 /* Rx BDR inetrrupt coalescing register 0*/
56 #define ENETC_RBICIR0_ICEN BIT(31)
59 #define ENETC_TBMR 0x0 /* Tx BDR mode register (TBMR) 32 RW */
60 #define ENETC_TBSR 0x4 /* x BDR status register (TBSR) 32 RO */
61 #define ENETC_TBBAR0 0x10 /* Tx BDR base address register 0 (TBBAR0) 32 RW */
62 #define ENETC_TBBAR1 0x14 /* Tx BDR base address register 1 (TBBAR1) 32 RW */
63 #define ENETC_TBCIR 0x18 /* Tx BDR consumer index register (TBCIR) 32 RW */
64 #define ENETC_TBCISR 0x1C /* Tx BDR consumer index shadow register 32 RW */
65 #define ENETC_TBIER 0xA0 /* Tx BDR interrupt enable register 32 RW */
66 #define ENETC_TBIDR 0xA4 /* Tx BDR interrupt detect register 32 RO */
67 #define ENETC_TBICR0 0xA8 /* Tx BDR interrupt coalescing register 0 32 RW */
68 #define ENETC_TBICR1 0xAC /* Tx BDR interrupt coalescing register 1 32 RW */
69 #define ENETC_TBLENR 0x20
71 #define ENETC_TBCISR_IDX_MASK 0xffff
72 #define ENETC_TBIER_TXFIE BIT(1)
74 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
75 #define ENETC_TBMR_EN BIT(31)
77 /* Port regs, offset: 1_0000h */
78 #define ENETC_PORT_BASE 0x10000
79 #define ENETC_PMR 0x00000
80 #define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18))
81 #define ENETC_PSR 0x00004 /* RO */
82 #define ENETC_PSIPMR 0x00018
83 #define ENETC_PSIPMR_SET_UP(n) (0x1 << (n)) /* n = SI index */
84 #define ENETC_PSIPMR_SET_MP(n) (0x1 << ((n) + 16))
85 #define ENETC_PSIPMAR0(n) (0x00100 + (n) * 0x20)
86 #define ENETC_PSIPMAR1(n) (0x00104 + (n) * 0x20)
87 #define ENETC_PCAPR0 0x00900
88 #define ENETC_PCAPR1 0x00904
89 #define ENETC_PM0_IF_MODE 0x8300
90 #define ENETC_PM1_IF_MODE 0x9300
91 #define ENETC_PMO_IFM_RG BIT(2)
92 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
93 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
94 #define ENETC_PM0_IFM_XGMII BIT(12)
96 #define ENETC_PV0CFGR(n) (0x00920 + (n) * 0x10)
97 #define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff)
98 #define ENETC_PVCFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
100 #define ENETC_PM0_CMD_CFG 0x08008
101 #define ENETC_PM0_TX_EN BIT(0)
102 #define ENETC_PM0_RX_EN BIT(1)
103 #define ENETC_PM0_CRC BIT(6)
105 #define ENETC_PAR_PORT_CFG 0x03050
106 #define L3_CKSUM BIT(0)
107 #define L4_CKSUM BIT(1)
109 #define ENETC_PM0_MAXFRM 0x08014
110 #define ENETC_SET_TX_MTU(val) ((val) << 16)
111 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
112 #define ENETC_PTXMBAR 0x0608
113 /* n = TC index [0..7] */
114 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4)
116 #define ENETC_PM0_STATUS 0x08304
117 #define ENETC_LINK_MODE 0x0000000000080000ULL
118 #define ENETC_LINK_STATUS 0x0000000000010000ULL
119 #define ENETC_LINK_SPEED_MASK 0x0000000000060000ULL
120 #define ENETC_LINK_SPEED_10M 0x0ULL
121 #define ENETC_LINK_SPEED_100M 0x0000000000020000ULL
122 #define ENETC_LINK_SPEED_1G 0x0000000000040000ULL
124 /* Global regs, offset: 2_0000h */
125 #define ENETC_GLOBAL_BASE 0x20000
126 #define ENETC_G_EIPBRR0 0x00bf8
127 #define ENETC_G_EIPBRR1 0x00bfc
130 /* Config register to reset counters*/
131 #define ENETC_PM0_STAT_CONFIG 0x080E0
132 /* Receive frames counter without error */
133 #define ENETC_PM0_RFRM 0x08120
134 /* Receive packets counter, good + bad */
135 #define ENETC_PM0_RPKT 0x08160
136 /* Received octets, good + bad */
137 #define ENETC_PM0_REOCT 0x08120
138 /* Transmit octets, good + bad */
139 #define ENETC_PM0_TEOCT 0x08200
140 /* Transmit frames counter without error */
141 #define ENETC_PM0_TFRM 0x08220
142 /* Transmit packets counter, good + bad */
143 #define ENETC_PM0_TPKT 0x08260
144 /* Dropped not Truncated packets counter */
145 #define ENETC_PM0_RDRNTP 0x081C8
146 /* Dropped + trucated packets counter */
147 #define ENETC_PM0_RDRP 0x08158
148 /* Receive packets error counter */
149 #define ENETC_PM0_RERR 0x08138
150 /* Transmit packets error counter */
151 #define ENETC_PM0_TERR 0x08238
154 #define ENETC_CLEAR_STATS BIT(2)
156 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
157 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
159 /* general register accessors */
160 #define enetc_rd_reg(reg) rte_read32((void *)(reg))
161 #define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg))
162 #define enetc_rd(hw, off) enetc_rd_reg((size_t)(hw)->reg + (off))
163 #define enetc_wr(hw, off, val) enetc_wr_reg((size_t)(hw)->reg + (off), val)
164 /* port register accessors - PF only */
165 #define enetc_port_rd(hw, off) enetc_rd_reg((size_t)(hw)->port + (off))
166 #define enetc_port_wr(hw, off, val) \
167 enetc_wr_reg((size_t)(hw)->port + (off), val)
168 /* global register accessors - PF only */
169 #define enetc_global_rd(hw, off) \
170 enetc_rd_reg((size_t)(hw)->global + (off))
171 #define enetc_global_wr(hw, off, val) \
172 enetc_wr_reg((size_t)(hw)->global + (off), val)
173 /* BDR register accessors, see ENETC_BDR() */
174 #define enetc_bdr_rd(hw, t, n, off) \
175 enetc_rd(hw, ENETC_BDR(t, n, off))
176 #define enetc_bdr_wr(hw, t, n, off, val) \
177 enetc_wr(hw, ENETC_BDR(t, n, off), val)
179 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
180 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
181 #define enetc_txbdr_wr(hw, n, off, val) \
182 enetc_bdr_wr(hw, TX, n, off, val)
183 #define enetc_rxbdr_wr(hw, n, off, val) \
184 enetc_bdr_wr(hw, RX, n, off, val)
186 #define ENETC_TX_ADDR(txq, addr) ((void *)((txq)->enetc_txbdr + (addr)))
188 #define ENETC_TXBD_FLAGS_IE BIT(13)
189 #define ENETC_TXBD_FLAGS_F BIT(15)
191 /* ENETC Parsed values (Little Endian) */
192 #define ENETC_PARSE_ERROR 0x8000
193 #define ENETC_PKT_TYPE_ETHER 0x0060
194 #define ENETC_PKT_TYPE_IPV4 0x0000
195 #define ENETC_PKT_TYPE_IPV6 0x0020
196 #define ENETC_PKT_TYPE_IPV4_TCP \
197 (0x0010 | ENETC_PKT_TYPE_IPV4)
198 #define ENETC_PKT_TYPE_IPV6_TCP \
199 (0x0010 | ENETC_PKT_TYPE_IPV6)
200 #define ENETC_PKT_TYPE_IPV4_UDP \
201 (0x0011 | ENETC_PKT_TYPE_IPV4)
202 #define ENETC_PKT_TYPE_IPV6_UDP \
203 (0x0011 | ENETC_PKT_TYPE_IPV6)
204 #define ENETC_PKT_TYPE_IPV4_SCTP \
205 (0x0013 | ENETC_PKT_TYPE_IPV4)
206 #define ENETC_PKT_TYPE_IPV6_SCTP \
207 (0x0013 | ENETC_PKT_TYPE_IPV6)
208 #define ENETC_PKT_TYPE_IPV4_ICMP \
209 (0x0003 | ENETC_PKT_TYPE_IPV4)
210 #define ENETC_PKT_TYPE_IPV6_ICMP \
211 (0x0003 | ENETC_PKT_TYPE_IPV6)
213 /* PCI device info */
215 void *reg; /* SI registers, used by all PCI functions */
216 void *port; /* Port registers, PF only */
217 void *global; /* IP global registers, PF only */
220 struct enetc_eth_mac_info {
221 uint8_t addr[RTE_ETHER_ADDR_LEN];
222 uint8_t perm_addr[RTE_ETHER_ADDR_LEN];
223 uint8_t get_link_status;
226 struct enetc_eth_hw {
227 struct rte_eth_dev *ndev;
232 struct enetc_eth_mac_info mac;
235 /* Transmit Descriptor */
236 struct enetc_tx_desc {
240 uint32_t flags_errors;
243 /* TX Buffer Descriptors (BD) */
252 /* RX buffer descriptor */
260 uint16_t parse_summary;