1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2019 NXP
9 #define BIT(x) ((uint64_t)1 << ((x)))
11 /* ENETC device IDs */
12 #define ENETC_DEV_ID_VF 0xef00
13 #define ENETC_DEV_ID 0xe100
15 /* ENETC register block BAR */
16 #define ENETC_BAR_REGS 0x0
18 /* SI regs, offset: 0h */
19 #define ENETC_SIMR 0x0
20 #define ENETC_SIMR_EN BIT(31)
22 #define ENETC_SIPMAR0 0x80
23 #define ENETC_SIPMAR1 0x84
25 #define ENETC_SICAPR0 0x900
26 #define ENETC_SICAPR1 0x904
28 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
29 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
31 #define ENETC_SICCAPR 0x1200
33 /* enum for BD type */
34 enum enetc_bdr_type {TX, RX};
36 #define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 \
38 /* RX BDR reg offsets */
39 #define ENETC_RBMR 0x0 /* RX BDR mode register*/
40 #define ENETC_RBMR_EN BIT(31)
42 #define ENETC_RBSR 0x4 /* Rx BDR status register*/
43 #define ENETC_RBBSR 0x8 /* Rx BDR buffer size register*/
44 #define ENETC_RBCIR 0xc /* Rx BDR consumer index register*/
45 #define ENETC_RBBAR0 0x10 /* Rx BDR base address register 0 */
46 #define ENETC_RBBAR1 0x14 /* Rx BDR base address register 1*/
47 #define ENETC_RBPIR 0x18 /* Rx BDR producer index register*/
48 #define ENETC_RBLENR 0x20 /* Rx BDR length register*/
49 #define ENETC_RBIER 0xa0 /* Rx BDR interrupt enable register*/
50 #define ENETC_RBIER_RXTIE BIT(0)
51 #define ENETC_RBIDR 0xa4 /* Rx BDR interrupt detect register*/
52 #define ENETC_RBICIR0 0xa8 /* Rx BDR inetrrupt coalescing register 0*/
53 #define ENETC_RBICIR0_ICEN BIT(31)
56 #define ENETC_TBMR 0x0 /* Tx BDR mode register (TBMR) 32 RW */
57 #define ENETC_TBSR 0x4 /* x BDR status register (TBSR) 32 RO */
58 #define ENETC_TBBAR0 0x10 /* Tx BDR base address register 0 (TBBAR0) 32 RW */
59 #define ENETC_TBBAR1 0x14 /* Tx BDR base address register 1 (TBBAR1) 32 RW */
60 #define ENETC_TBCIR 0x18 /* Tx BDR consumer index register (TBCIR) 32 RW */
61 #define ENETC_TBCISR 0x1C /* Tx BDR consumer index shadow register 32 RW */
62 #define ENETC_TBIER 0xA0 /* Tx BDR interrupt enable register 32 RW */
63 #define ENETC_TBIDR 0xA4 /* Tx BDR interrupt detect register 32 RO */
64 #define ENETC_TBICR0 0xA8 /* Tx BDR interrupt coalescing register 0 32 RW */
65 #define ENETC_TBICR1 0xAC /* Tx BDR interrupt coalescing register 1 32 RW */
66 #define ENETC_TBLENR 0x20
68 #define ENETC_TBCISR_IDX_MASK 0xffff
69 #define ENETC_TBIER_TXFIE BIT(1)
71 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
72 #define ENETC_TBMR_EN BIT(31)
74 /* Port regs, offset: 1_0000h */
75 #define ENETC_PORT_BASE 0x10000
76 #define ENETC_PMR 0x00000
77 #define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18))
78 #define ENETC_PSR 0x00004 /* RO */
79 #define ENETC_PSIPMR 0x00018
80 #define ENETC_PSIPMR_SET_UP(n) (0x1 << (n)) /* n = SI index */
81 #define ENETC_PSIPMR_SET_MP(n) (0x1 << ((n) + 16))
82 #define ENETC_PSIPMAR0(n) (0x00100 + (n) * 0x20)
83 #define ENETC_PSIPMAR1(n) (0x00104 + (n) * 0x20)
84 #define ENETC_PCAPR0 0x00900
85 #define ENETC_PCAPR1 0x00904
86 #define ENETC_PM0_IF_MODE 0x8300
87 #define ENETC_PM1_IF_MODE 0x9300
88 #define ENETC_PMO_IFM_RG BIT(2)
89 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
90 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
91 #define ENETC_PM0_IFM_XGMII BIT(12)
93 #define ENETC_PV0CFGR(n) (0x00920 + (n) * 0x10)
94 #define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff)
95 #define ENETC_PVCFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
97 #define ENETC_PM0_CMD_CFG 0x08008
98 #define ENETC_PM0_TX_EN BIT(0)
99 #define ENETC_PM0_RX_EN BIT(1)
101 #define ENETC_PM0_MAXFRM 0x08014
102 #define ENETC_SET_TX_MTU(val) ((val) << 16)
103 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
104 #define ENETC_PTXMBAR 0x0608
105 /* n = TC index [0..7] */
106 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4)
108 #define ENETC_PM0_STATUS 0x08304
109 #define ENETC_LINK_MODE 0x0000000000080000ULL
110 #define ENETC_LINK_STATUS 0x0000000000010000ULL
111 #define ENETC_LINK_SPEED_MASK 0x0000000000060000ULL
112 #define ENETC_LINK_SPEED_10M 0x0ULL
113 #define ENETC_LINK_SPEED_100M 0x0000000000020000ULL
114 #define ENETC_LINK_SPEED_1G 0x0000000000040000ULL
116 /* Global regs, offset: 2_0000h */
117 #define ENETC_GLOBAL_BASE 0x20000
118 #define ENETC_G_EIPBRR0 0x00bf8
119 #define ENETC_G_EIPBRR1 0x00bfc
122 /* Config register to reset counters*/
123 #define ENETC_PM0_STAT_CONFIG 0x080E0
124 /* Receive frames counter without error */
125 #define ENETC_PM0_RFRM 0x08120
126 /* Receive packets counter, good + bad */
127 #define ENETC_PM0_RPKT 0x08160
128 /* Received octets, good + bad */
129 #define ENETC_PM0_REOCT 0x08120
130 /* Transmit octets, good + bad */
131 #define ENETC_PM0_TEOCT 0x08200
132 /* Transmit frames counter without error */
133 #define ENETC_PM0_TFRM 0x08220
134 /* Transmit packets counter, good + bad */
135 #define ENETC_PM0_TPKT 0x08260
136 /* Dropped not Truncated packets counter */
137 #define ENETC_PM0_RDRNTP 0x081C8
138 /* Dropped + trucated packets counter */
139 #define ENETC_PM0_RDRP 0x08158
140 /* Receive packets error counter */
141 #define ENETC_PM0_RERR 0x08138
142 /* Transmit packets error counter */
143 #define ENETC_PM0_TERR 0x08238
146 #define ENETC_CLEAR_STATS BIT(2)
148 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
149 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
151 /* general register accessors */
152 #define enetc_rd_reg(reg) rte_read32((void *)(reg))
153 #define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg))
154 #define enetc_rd(hw, off) enetc_rd_reg((size_t)(hw)->reg + (off))
155 #define enetc_wr(hw, off, val) enetc_wr_reg((size_t)(hw)->reg + (off), val)
156 /* port register accessors - PF only */
157 #define enetc_port_rd(hw, off) enetc_rd_reg((size_t)(hw)->port + (off))
158 #define enetc_port_wr(hw, off, val) \
159 enetc_wr_reg((size_t)(hw)->port + (off), val)
160 /* global register accessors - PF only */
161 #define enetc_global_rd(hw, off) \
162 enetc_rd_reg((size_t)(hw)->global + (off))
163 #define enetc_global_wr(hw, off, val) \
164 enetc_wr_reg((size_t)(hw)->global + (off), val)
165 /* BDR register accessors, see ENETC_BDR() */
166 #define enetc_bdr_rd(hw, t, n, off) \
167 enetc_rd(hw, ENETC_BDR(t, n, off))
168 #define enetc_bdr_wr(hw, t, n, off, val) \
169 enetc_wr(hw, ENETC_BDR(t, n, off), val)
171 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
172 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
173 #define enetc_txbdr_wr(hw, n, off, val) \
174 enetc_bdr_wr(hw, TX, n, off, val)
175 #define enetc_rxbdr_wr(hw, n, off, val) \
176 enetc_bdr_wr(hw, RX, n, off, val)
178 #define ENETC_TX_ADDR(txq, addr) ((void *)((txq)->enetc_txbdr + (addr)))
180 #define ENETC_TXBD_FLAGS_IE BIT(13)
181 #define ENETC_TXBD_FLAGS_F BIT(15)
183 /* ENETC Parsed values (Little Endian) */
184 #define ENETC_PKT_TYPE_ETHER 0x0060
185 #define ENETC_PKT_TYPE_IPV4 0x0000
186 #define ENETC_PKT_TYPE_IPV6 0x0020
187 #define ENETC_PKT_TYPE_IPV4_TCP \
188 (0x0010 | ENETC_PKT_TYPE_IPV4)
189 #define ENETC_PKT_TYPE_IPV6_TCP \
190 (0x0010 | ENETC_PKT_TYPE_IPV6)
191 #define ENETC_PKT_TYPE_IPV4_UDP \
192 (0x0011 | ENETC_PKT_TYPE_IPV4)
193 #define ENETC_PKT_TYPE_IPV6_UDP \
194 (0x0011 | ENETC_PKT_TYPE_IPV6)
195 #define ENETC_PKT_TYPE_IPV4_SCTP \
196 (0x0013 | ENETC_PKT_TYPE_IPV4)
197 #define ENETC_PKT_TYPE_IPV6_SCTP \
198 (0x0013 | ENETC_PKT_TYPE_IPV6)
199 #define ENETC_PKT_TYPE_IPV4_ICMP \
200 (0x0003 | ENETC_PKT_TYPE_IPV4)
201 #define ENETC_PKT_TYPE_IPV6_ICMP \
202 (0x0003 | ENETC_PKT_TYPE_IPV6)
204 /* PCI device info */
206 void *reg; /* SI registers, used by all PCI functions */
207 void *port; /* Port registers, PF only */
208 void *global; /* IP global registers, PF only */
211 struct enetc_eth_mac_info {
212 uint8_t addr[ETHER_ADDR_LEN];
213 uint8_t perm_addr[ETHER_ADDR_LEN];
214 uint8_t get_link_status;
217 struct enetc_eth_hw {
218 struct rte_eth_dev *ndev;
223 struct enetc_eth_mac_info mac;
226 /* Transmit Descriptor */
227 struct enetc_tx_desc {
231 uint32_t flags_errors;
234 /* TX Buffer Descriptors (BD) */
243 /* RX buffer descriptor */
251 uint16_t parse_summary;