1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2020 NXP
6 #include <ethdev_pci.h>
7 #include <rte_random.h>
8 #include <dpaax_iova_table.h>
10 #include "enetc_logs.h"
14 enetc_dev_start(struct rte_eth_dev *dev)
16 struct enetc_eth_hw *hw =
17 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
18 struct enetc_hw *enetc_hw = &hw->hw;
21 PMD_INIT_FUNC_TRACE();
22 if (hw->device_id == ENETC_DEV_ID_VF)
25 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
26 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
27 val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
30 val = enetc_port_rd(enetc_hw, ENETC_PMR);
31 enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN);
33 /* set auto-speed for RGMII */
34 if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) {
35 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
36 ENETC_PM0_IFM_RGAUTO);
37 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
38 ENETC_PM0_IFM_RGAUTO);
40 if (enetc_global_rd(enetc_hw,
41 ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) {
42 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
44 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
52 enetc_dev_stop(struct rte_eth_dev *dev)
54 struct enetc_eth_hw *hw =
55 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
56 struct enetc_hw *enetc_hw = &hw->hw;
59 PMD_INIT_FUNC_TRACE();
60 dev->data->dev_started = 0;
61 if (hw->device_id == ENETC_DEV_ID_VF)
65 val = enetc_port_rd(enetc_hw, ENETC_PMR);
66 enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN));
68 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
69 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
70 val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN)));
75 static const uint32_t *
76 enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
78 static const uint32_t ptypes[] = {
92 /* return 0 means link status changed, -1 means not changed */
94 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
96 struct enetc_eth_hw *hw =
97 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
98 struct enetc_hw *enetc_hw = &hw->hw;
99 struct rte_eth_link link;
102 PMD_INIT_FUNC_TRACE();
104 memset(&link, 0, sizeof(link));
106 status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS);
108 if (status & ENETC_LINK_MODE)
109 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
111 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
113 if (status & ENETC_LINK_STATUS)
114 link.link_status = RTE_ETH_LINK_UP;
116 link.link_status = RTE_ETH_LINK_DOWN;
118 switch (status & ENETC_LINK_SPEED_MASK) {
119 case ENETC_LINK_SPEED_1G:
120 link.link_speed = RTE_ETH_SPEED_NUM_1G;
123 case ENETC_LINK_SPEED_100M:
124 link.link_speed = RTE_ETH_SPEED_NUM_100M;
128 case ENETC_LINK_SPEED_10M:
129 link.link_speed = RTE_ETH_SPEED_NUM_10M;
132 return rte_eth_linkstatus_set(dev, &link);
136 print_ethaddr(const char *name, const struct rte_ether_addr *eth_addr)
138 char buf[RTE_ETHER_ADDR_FMT_SIZE];
140 rte_ether_format_addr(buf, RTE_ETHER_ADDR_FMT_SIZE, eth_addr);
141 ENETC_PMD_NOTICE("%s%s\n", name, buf);
145 enetc_hardware_init(struct enetc_eth_hw *hw)
147 struct enetc_hw *enetc_hw = &hw->hw;
148 uint32_t *mac = (uint32_t *)hw->mac.addr;
149 uint32_t high_mac = 0;
150 uint16_t low_mac = 0;
152 PMD_INIT_FUNC_TRACE();
153 /* Calculating and storing the base HW addresses */
154 hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE);
155 hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE);
157 /* WA for Rx lock-up HW erratum */
158 enetc_port_wr(enetc_hw, ENETC_PM0_RX_FIFO, 1);
160 /* set ENETC transaction flags to coherent, don't allocate.
161 * BD writes merge with surrounding cache line data, frame data writes
162 * overwrite cache line.
164 enetc_wr(enetc_hw, ENETC_SICAR0, ENETC_SICAR0_COHERENT);
166 /* Enabling Station Interface */
167 enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);
170 if (hw->device_id == ENETC_DEV_ID_VF) {
171 *mac = (uint32_t)enetc_rd(enetc_hw, ENETC_SIPMAR0);
172 high_mac = (uint32_t)*mac;
174 *mac = (uint32_t)enetc_rd(enetc_hw, ENETC_SIPMAR1);
175 low_mac = (uint16_t)*mac;
177 *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0));
178 high_mac = (uint32_t)*mac;
180 *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0));
181 low_mac = (uint16_t)*mac;
184 if ((high_mac | low_mac) == 0) {
187 ENETC_PMD_NOTICE("MAC is not available for this SI, "
189 mac = (uint32_t *)hw->mac.addr;
190 *mac = (uint32_t)rte_rand();
191 first_byte = (char *)mac;
192 *first_byte &= 0xfe; /* clear multicast bit */
193 *first_byte |= 0x02; /* set local assignment bit (IEEE802) */
195 enetc_port_wr(enetc_hw, ENETC_PSIPMAR0(0), *mac);
197 *mac = (uint16_t)rte_rand();
198 enetc_port_wr(enetc_hw, ENETC_PSIPMAR1(0), *mac);
199 print_ethaddr("New address: ",
200 (const struct rte_ether_addr *)hw->mac.addr);
207 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
208 struct rte_eth_dev_info *dev_info)
210 PMD_INIT_FUNC_TRACE();
211 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
212 .nb_max = MAX_BD_COUNT,
213 .nb_min = MIN_BD_COUNT,
214 .nb_align = BD_ALIGN,
216 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
217 .nb_max = MAX_BD_COUNT,
218 .nb_min = MIN_BD_COUNT,
219 .nb_align = BD_ALIGN,
221 dev_info->max_rx_queues = MAX_RX_RINGS;
222 dev_info->max_tx_queues = MAX_TX_RINGS;
223 dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE;
224 dev_info->rx_offload_capa =
225 (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
226 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
227 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
228 RTE_ETH_RX_OFFLOAD_KEEP_CRC);
234 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc)
238 size = nb_desc * sizeof(struct enetc_swbd);
239 txr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
240 if (txr->q_swbd == NULL)
243 size = nb_desc * sizeof(struct enetc_tx_bd);
244 txr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
245 if (txr->bd_base == NULL) {
246 rte_free(txr->q_swbd);
251 txr->bd_count = nb_desc;
252 txr->next_to_clean = 0;
253 txr->next_to_use = 0;
259 enetc_free_bdr(struct enetc_bdr *rxr)
261 rte_free(rxr->q_swbd);
262 rte_free(rxr->bd_base);
268 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
270 int idx = tx_ring->index;
271 phys_addr_t bd_address;
273 bd_address = (phys_addr_t)
274 rte_mem_virt2iova((const void *)tx_ring->bd_base);
275 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
276 lower_32_bits((uint64_t)bd_address));
277 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
278 upper_32_bits((uint64_t)bd_address));
279 enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
280 ENETC_RTBLENR_LEN(tx_ring->bd_count));
282 enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
283 enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0);
284 tx_ring->tcir = (void *)((size_t)hw->reg +
285 ENETC_BDR(TX, idx, ENETC_TBCIR));
286 tx_ring->tcisr = (void *)((size_t)hw->reg +
287 ENETC_BDR(TX, idx, ENETC_TBCISR));
291 enetc_tx_queue_setup(struct rte_eth_dev *dev,
294 unsigned int socket_id __rte_unused,
295 const struct rte_eth_txconf *tx_conf)
298 struct enetc_bdr *tx_ring;
299 struct rte_eth_dev_data *data = dev->data;
300 struct enetc_eth_adapter *priv =
301 ENETC_DEV_PRIVATE(data->dev_private);
303 PMD_INIT_FUNC_TRACE();
304 if (nb_desc > MAX_BD_COUNT)
307 tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
308 if (tx_ring == NULL) {
309 ENETC_PMD_ERR("Failed to allocate TX ring memory");
314 err = enetc_alloc_txbdr(tx_ring, nb_desc);
318 tx_ring->index = queue_idx;
320 enetc_setup_txbdr(&priv->hw.hw, tx_ring);
321 data->tx_queues[queue_idx] = tx_ring;
323 if (!tx_conf->tx_deferred_start) {
325 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index,
326 ENETC_TBMR, ENETC_TBMR_EN);
327 dev->data->tx_queue_state[tx_ring->index] =
328 RTE_ETH_QUEUE_STATE_STARTED;
330 dev->data->tx_queue_state[tx_ring->index] =
331 RTE_ETH_QUEUE_STATE_STOPPED;
342 enetc_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
344 void *txq = dev->data->tx_queues[qid];
349 struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq;
350 struct enetc_eth_hw *eth_hw =
351 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private);
353 struct enetc_swbd *tx_swbd;
357 /* Disable the ring */
359 val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR);
360 val &= (~ENETC_TBMR_EN);
361 enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val);
364 i = tx_ring->next_to_clean;
365 tx_swbd = &tx_ring->q_swbd[i];
366 while (tx_swbd->buffer_addr != NULL) {
367 rte_pktmbuf_free(tx_swbd->buffer_addr);
368 tx_swbd->buffer_addr = NULL;
371 if (unlikely(i == tx_ring->bd_count)) {
373 tx_swbd = &tx_ring->q_swbd[i];
377 enetc_free_bdr(tx_ring);
382 enetc_alloc_rxbdr(struct enetc_bdr *rxr,
387 size = nb_rx_desc * sizeof(struct enetc_swbd);
388 rxr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
389 if (rxr->q_swbd == NULL)
392 size = nb_rx_desc * sizeof(union enetc_rx_bd);
393 rxr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
394 if (rxr->bd_base == NULL) {
395 rte_free(rxr->q_swbd);
400 rxr->bd_count = nb_rx_desc;
401 rxr->next_to_clean = 0;
402 rxr->next_to_use = 0;
403 rxr->next_to_alloc = 0;
409 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
410 struct rte_mempool *mb_pool)
412 int idx = rx_ring->index;
414 phys_addr_t bd_address;
416 bd_address = (phys_addr_t)
417 rte_mem_virt2iova((const void *)rx_ring->bd_base);
418 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
419 lower_32_bits((uint64_t)bd_address));
420 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
421 upper_32_bits((uint64_t)bd_address));
422 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
423 ENETC_RTBLENR_LEN(rx_ring->bd_count));
425 rx_ring->mb_pool = mb_pool;
426 rx_ring->rcir = (void *)((size_t)hw->reg +
427 ENETC_BDR(RX, idx, ENETC_RBCIR));
428 enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring)));
429 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) -
430 RTE_PKTMBUF_HEADROOM);
431 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size);
432 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
436 enetc_rx_queue_setup(struct rte_eth_dev *dev,
437 uint16_t rx_queue_id,
439 unsigned int socket_id __rte_unused,
440 const struct rte_eth_rxconf *rx_conf,
441 struct rte_mempool *mb_pool)
444 struct enetc_bdr *rx_ring;
445 struct rte_eth_dev_data *data = dev->data;
446 struct enetc_eth_adapter *adapter =
447 ENETC_DEV_PRIVATE(data->dev_private);
448 uint64_t rx_offloads = data->dev_conf.rxmode.offloads;
450 PMD_INIT_FUNC_TRACE();
451 if (nb_rx_desc > MAX_BD_COUNT)
454 rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
455 if (rx_ring == NULL) {
456 ENETC_PMD_ERR("Failed to allocate RX ring memory");
461 err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc);
465 rx_ring->index = rx_queue_id;
467 enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool);
468 data->rx_queues[rx_queue_id] = rx_ring;
470 if (!rx_conf->rx_deferred_start) {
472 enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR,
474 dev->data->rx_queue_state[rx_ring->index] =
475 RTE_ETH_QUEUE_STATE_STARTED;
477 dev->data->rx_queue_state[rx_ring->index] =
478 RTE_ETH_QUEUE_STATE_STOPPED;
481 rx_ring->crc_len = (uint8_t)((rx_offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) ?
482 RTE_ETHER_CRC_LEN : 0);
492 enetc_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
494 void *rxq = dev->data->rx_queues[qid];
499 struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;
500 struct enetc_eth_hw *eth_hw =
501 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private);
502 struct enetc_swbd *q_swbd;
507 /* Disable the ring */
509 val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR);
510 val &= (~ENETC_RBMR_EN);
511 enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val);
514 i = rx_ring->next_to_clean;
515 q_swbd = &rx_ring->q_swbd[i];
516 while (i != rx_ring->next_to_use) {
517 rte_pktmbuf_free(q_swbd->buffer_addr);
518 q_swbd->buffer_addr = NULL;
521 if (unlikely(i == rx_ring->bd_count)) {
523 q_swbd = &rx_ring->q_swbd[i];
527 enetc_free_bdr(rx_ring);
532 int enetc_stats_get(struct rte_eth_dev *dev,
533 struct rte_eth_stats *stats)
535 struct enetc_eth_hw *hw =
536 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
537 struct enetc_hw *enetc_hw = &hw->hw;
539 /* Total received packets, bad + good, if we want to get counters of
540 * only good received packets then use ENETC_PM0_RFRM,
541 * ENETC_PM0_TFRM registers.
543 stats->ipackets = enetc_port_rd(enetc_hw, ENETC_PM0_RPKT);
544 stats->opackets = enetc_port_rd(enetc_hw, ENETC_PM0_TPKT);
545 stats->ibytes = enetc_port_rd(enetc_hw, ENETC_PM0_REOCT);
546 stats->obytes = enetc_port_rd(enetc_hw, ENETC_PM0_TEOCT);
547 /* Dropped + Truncated packets, use ENETC_PM0_RDRNTP for without
550 stats->imissed = enetc_port_rd(enetc_hw, ENETC_PM0_RDRP);
551 stats->ierrors = enetc_port_rd(enetc_hw, ENETC_PM0_RERR);
552 stats->oerrors = enetc_port_rd(enetc_hw, ENETC_PM0_TERR);
558 enetc_stats_reset(struct rte_eth_dev *dev)
560 struct enetc_eth_hw *hw =
561 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 struct enetc_hw *enetc_hw = &hw->hw;
564 enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS);
570 enetc_dev_close(struct rte_eth_dev *dev)
575 PMD_INIT_FUNC_TRACE();
576 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
579 ret = enetc_dev_stop(dev);
581 for (i = 0; i < dev->data->nb_rx_queues; i++) {
582 enetc_rx_queue_release(dev, i);
583 dev->data->rx_queues[i] = NULL;
585 dev->data->nb_rx_queues = 0;
587 for (i = 0; i < dev->data->nb_tx_queues; i++) {
588 enetc_tx_queue_release(dev, i);
589 dev->data->tx_queues[i] = NULL;
591 dev->data->nb_tx_queues = 0;
593 if (rte_eal_iova_mode() == RTE_IOVA_PA)
594 dpaax_iova_table_depopulate();
600 enetc_promiscuous_enable(struct rte_eth_dev *dev)
602 struct enetc_eth_hw *hw =
603 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
604 struct enetc_hw *enetc_hw = &hw->hw;
607 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
609 /* Setting to enable promiscuous mode*/
610 psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
612 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
618 enetc_promiscuous_disable(struct rte_eth_dev *dev)
620 struct enetc_eth_hw *hw =
621 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
622 struct enetc_hw *enetc_hw = &hw->hw;
625 /* Setting to disable promiscuous mode for SI0*/
626 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
627 psipmr &= (~ENETC_PSIPMR_SET_UP(0));
629 if (dev->data->all_multicast == 0)
630 psipmr &= (~ENETC_PSIPMR_SET_MP(0));
632 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
638 enetc_allmulticast_enable(struct rte_eth_dev *dev)
640 struct enetc_eth_hw *hw =
641 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
642 struct enetc_hw *enetc_hw = &hw->hw;
645 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
647 /* Setting to enable allmulticast mode for SI0*/
648 psipmr |= ENETC_PSIPMR_SET_MP(0);
650 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
656 enetc_allmulticast_disable(struct rte_eth_dev *dev)
658 struct enetc_eth_hw *hw =
659 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
660 struct enetc_hw *enetc_hw = &hw->hw;
663 if (dev->data->promiscuous == 1)
664 return 0; /* must remain in all_multicast mode */
666 /* Setting to disable all multicast mode for SI0*/
667 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) &
668 ~(ENETC_PSIPMR_SET_MP(0));
670 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
676 enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
678 struct enetc_eth_hw *hw =
679 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
680 struct enetc_hw *enetc_hw = &hw->hw;
681 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
684 * Refuse mtu that requires the support of scattered packets
685 * when this feature has not been enabled before.
687 if (dev->data->min_rx_buf_size &&
688 !dev->data->scattered_rx && frame_size >
689 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
690 ENETC_PMD_ERR("SG not enabled, will not fit in one buffer");
694 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
695 enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
698 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) |
699 ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE));
705 enetc_dev_configure(struct rte_eth_dev *dev)
707 struct enetc_eth_hw *hw =
708 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
709 struct enetc_hw *enetc_hw = &hw->hw;
710 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
711 uint64_t rx_offloads = eth_conf->rxmode.offloads;
712 uint32_t checksum = L3_CKSUM | L4_CKSUM;
715 PMD_INIT_FUNC_TRACE();
717 max_len = dev->data->dev_conf.rxmode.mtu + RTE_ETHER_HDR_LEN +
719 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(max_len));
720 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
721 enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
723 if (rx_offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
726 config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
727 config |= ENETC_PM0_CRC;
728 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config);
731 if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
732 checksum &= ~L3_CKSUM;
734 if (rx_offloads & (RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM))
735 checksum &= ~L4_CKSUM;
737 enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum);
744 enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
746 struct enetc_eth_adapter *priv =
747 ENETC_DEV_PRIVATE(dev->data->dev_private);
748 struct enetc_bdr *rx_ring;
751 rx_ring = dev->data->rx_queues[qidx];
752 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
753 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
755 rx_data = rx_data | ENETC_RBMR_EN;
756 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
758 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
765 enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
767 struct enetc_eth_adapter *priv =
768 ENETC_DEV_PRIVATE(dev->data->dev_private);
769 struct enetc_bdr *rx_ring;
772 rx_ring = dev->data->rx_queues[qidx];
773 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
774 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
776 rx_data = rx_data & (~ENETC_RBMR_EN);
777 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
779 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
786 enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
788 struct enetc_eth_adapter *priv =
789 ENETC_DEV_PRIVATE(dev->data->dev_private);
790 struct enetc_bdr *tx_ring;
793 tx_ring = dev->data->tx_queues[qidx];
794 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
795 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
797 tx_data = tx_data | ENETC_TBMR_EN;
798 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
800 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
807 enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
809 struct enetc_eth_adapter *priv =
810 ENETC_DEV_PRIVATE(dev->data->dev_private);
811 struct enetc_bdr *tx_ring;
814 tx_ring = dev->data->tx_queues[qidx];
815 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
816 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
818 tx_data = tx_data & (~ENETC_TBMR_EN);
819 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
821 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
828 * The set of PCI devices this driver supports
830 static const struct rte_pci_id pci_id_enetc_map[] = {
831 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) },
832 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) },
833 { .vendor_id = 0, /* sentinel */ },
836 /* Features supported by this driver */
837 static const struct eth_dev_ops enetc_ops = {
838 .dev_configure = enetc_dev_configure,
839 .dev_start = enetc_dev_start,
840 .dev_stop = enetc_dev_stop,
841 .dev_close = enetc_dev_close,
842 .link_update = enetc_link_update,
843 .stats_get = enetc_stats_get,
844 .stats_reset = enetc_stats_reset,
845 .promiscuous_enable = enetc_promiscuous_enable,
846 .promiscuous_disable = enetc_promiscuous_disable,
847 .allmulticast_enable = enetc_allmulticast_enable,
848 .allmulticast_disable = enetc_allmulticast_disable,
849 .dev_infos_get = enetc_dev_infos_get,
850 .mtu_set = enetc_mtu_set,
851 .rx_queue_setup = enetc_rx_queue_setup,
852 .rx_queue_start = enetc_rx_queue_start,
853 .rx_queue_stop = enetc_rx_queue_stop,
854 .rx_queue_release = enetc_rx_queue_release,
855 .tx_queue_setup = enetc_tx_queue_setup,
856 .tx_queue_start = enetc_tx_queue_start,
857 .tx_queue_stop = enetc_tx_queue_stop,
858 .tx_queue_release = enetc_tx_queue_release,
859 .dev_supported_ptypes_get = enetc_supported_ptypes_get,
863 * Initialisation of the enetc device
866 * - Pointer to the structure rte_eth_dev
869 * - On success, zero.
870 * - On failure, negative value.
873 enetc_dev_init(struct rte_eth_dev *eth_dev)
876 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
877 struct enetc_eth_hw *hw =
878 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
880 PMD_INIT_FUNC_TRACE();
881 eth_dev->dev_ops = &enetc_ops;
882 eth_dev->rx_pkt_burst = &enetc_recv_pkts;
883 eth_dev->tx_pkt_burst = &enetc_xmit_pkts;
885 /* Retrieving and storing the HW base address of device */
886 hw->hw.reg = (void *)pci_dev->mem_resource[0].addr;
887 hw->device_id = pci_dev->id.device_id;
889 error = enetc_hardware_init(hw);
891 ENETC_PMD_ERR("Hardware initialization failed");
895 /* Allocate memory for storing MAC addresses */
896 eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth",
897 RTE_ETHER_ADDR_LEN, 0);
898 if (!eth_dev->data->mac_addrs) {
899 ENETC_PMD_ERR("Failed to allocate %d bytes needed to "
900 "store MAC addresses",
901 RTE_ETHER_ADDR_LEN * 1);
906 /* Copy the permanent MAC address */
907 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
908 ð_dev->data->mac_addrs[0]);
911 enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM,
912 ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN));
913 eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
916 if (rte_eal_iova_mode() == RTE_IOVA_PA)
917 dpaax_iova_table_populate();
919 ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x",
920 eth_dev->data->port_id, pci_dev->id.vendor_id,
921 pci_dev->id.device_id);
926 enetc_dev_uninit(struct rte_eth_dev *eth_dev)
928 PMD_INIT_FUNC_TRACE();
930 return enetc_dev_close(eth_dev);
934 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
935 struct rte_pci_device *pci_dev)
937 return rte_eth_dev_pci_generic_probe(pci_dev,
938 sizeof(struct enetc_eth_adapter),
943 enetc_pci_remove(struct rte_pci_device *pci_dev)
945 return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit);
948 static struct rte_pci_driver rte_enetc_pmd = {
949 .id_table = pci_id_enetc_map,
950 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
951 .probe = enetc_pci_probe,
952 .remove = enetc_pci_remove,
955 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd);
956 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map);
957 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci");
958 RTE_LOG_REGISTER_DEFAULT(enetc_logtype_pmd, NOTICE);