1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2019 NXP
6 #include <rte_ethdev_pci.h>
8 #include "enetc_logs.h"
11 int enetc_logtype_pmd;
14 enetc_dev_start(struct rte_eth_dev *dev)
16 struct enetc_eth_hw *hw =
17 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
18 struct enetc_hw *enetc_hw = &hw->hw;
21 PMD_INIT_FUNC_TRACE();
22 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
23 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
24 val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
27 val = enetc_port_rd(enetc_hw, ENETC_PMR);
28 enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN);
30 /* set auto-speed for RGMII */
31 if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) {
32 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
33 ENETC_PM0_IFM_RGAUTO);
34 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
35 ENETC_PM0_IFM_RGAUTO);
37 if (enetc_global_rd(enetc_hw,
38 ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) {
39 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
41 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
49 enetc_dev_stop(struct rte_eth_dev *dev)
51 struct enetc_eth_hw *hw =
52 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
53 struct enetc_hw *enetc_hw = &hw->hw;
56 PMD_INIT_FUNC_TRACE();
58 val = enetc_port_rd(enetc_hw, ENETC_PMR);
59 enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN));
61 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
62 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
63 val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN)));
66 static const uint32_t *
67 enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
69 static const uint32_t ptypes[] = {
83 /* return 0 means link status changed, -1 means not changed */
85 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
87 struct enetc_eth_hw *hw =
88 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
89 struct enetc_hw *enetc_hw = &hw->hw;
90 struct rte_eth_link link;
93 PMD_INIT_FUNC_TRACE();
95 memset(&link, 0, sizeof(link));
97 status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS);
99 if (status & ENETC_LINK_MODE)
100 link.link_duplex = ETH_LINK_FULL_DUPLEX;
102 link.link_duplex = ETH_LINK_HALF_DUPLEX;
104 if (status & ENETC_LINK_STATUS)
105 link.link_status = ETH_LINK_UP;
107 link.link_status = ETH_LINK_DOWN;
109 switch (status & ENETC_LINK_SPEED_MASK) {
110 case ENETC_LINK_SPEED_1G:
111 link.link_speed = ETH_SPEED_NUM_1G;
114 case ENETC_LINK_SPEED_100M:
115 link.link_speed = ETH_SPEED_NUM_100M;
119 case ENETC_LINK_SPEED_10M:
120 link.link_speed = ETH_SPEED_NUM_10M;
123 return rte_eth_linkstatus_set(dev, &link);
127 enetc_hardware_init(struct enetc_eth_hw *hw)
129 struct enetc_hw *enetc_hw = &hw->hw;
130 uint32_t *mac = (uint32_t *)hw->mac.addr;
132 PMD_INIT_FUNC_TRACE();
133 /* Calculating and storing the base HW addresses */
134 hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE);
135 hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE);
137 /* Enabling Station Interface */
138 enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);
140 *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0));
142 *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0));
148 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
149 struct rte_eth_dev_info *dev_info)
151 PMD_INIT_FUNC_TRACE();
152 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
153 .nb_max = MAX_BD_COUNT,
154 .nb_min = MIN_BD_COUNT,
155 .nb_align = BD_ALIGN,
157 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
158 .nb_max = MAX_BD_COUNT,
159 .nb_min = MIN_BD_COUNT,
160 .nb_align = BD_ALIGN,
162 dev_info->max_rx_queues = MAX_RX_RINGS;
163 dev_info->max_tx_queues = MAX_TX_RINGS;
164 dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE;
165 dev_info->rx_offload_capa =
166 (DEV_RX_OFFLOAD_IPV4_CKSUM |
167 DEV_RX_OFFLOAD_UDP_CKSUM |
168 DEV_RX_OFFLOAD_TCP_CKSUM |
169 DEV_RX_OFFLOAD_KEEP_CRC |
170 DEV_RX_OFFLOAD_JUMBO_FRAME);
174 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc)
178 size = nb_desc * sizeof(struct enetc_swbd);
179 txr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
180 if (txr->q_swbd == NULL)
183 size = nb_desc * sizeof(struct enetc_tx_bd);
184 txr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
185 if (txr->bd_base == NULL) {
186 rte_free(txr->q_swbd);
191 txr->bd_count = nb_desc;
192 txr->next_to_clean = 0;
193 txr->next_to_use = 0;
199 enetc_free_bdr(struct enetc_bdr *rxr)
201 rte_free(rxr->q_swbd);
202 rte_free(rxr->bd_base);
208 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
210 int idx = tx_ring->index;
211 phys_addr_t bd_address;
213 bd_address = (phys_addr_t)
214 rte_mem_virt2iova((const void *)tx_ring->bd_base);
215 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
216 lower_32_bits((uint64_t)bd_address));
217 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
218 upper_32_bits((uint64_t)bd_address));
219 enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
220 ENETC_RTBLENR_LEN(tx_ring->bd_count));
222 enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
223 enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0);
224 tx_ring->tcir = (void *)((size_t)hw->reg +
225 ENETC_BDR(TX, idx, ENETC_TBCIR));
226 tx_ring->tcisr = (void *)((size_t)hw->reg +
227 ENETC_BDR(TX, idx, ENETC_TBCISR));
231 enetc_tx_queue_setup(struct rte_eth_dev *dev,
234 unsigned int socket_id __rte_unused,
235 const struct rte_eth_txconf *tx_conf)
238 struct enetc_bdr *tx_ring;
239 struct rte_eth_dev_data *data = dev->data;
240 struct enetc_eth_adapter *priv =
241 ENETC_DEV_PRIVATE(data->dev_private);
243 PMD_INIT_FUNC_TRACE();
244 if (nb_desc > MAX_BD_COUNT)
247 tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
248 if (tx_ring == NULL) {
249 ENETC_PMD_ERR("Failed to allocate TX ring memory");
254 err = enetc_alloc_txbdr(tx_ring, nb_desc);
258 tx_ring->index = queue_idx;
260 enetc_setup_txbdr(&priv->hw.hw, tx_ring);
261 data->tx_queues[queue_idx] = tx_ring;
263 if (!tx_conf->tx_deferred_start) {
265 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index,
266 ENETC_TBMR, ENETC_TBMR_EN);
267 dev->data->tx_queue_state[tx_ring->index] =
268 RTE_ETH_QUEUE_STATE_STARTED;
270 dev->data->tx_queue_state[tx_ring->index] =
271 RTE_ETH_QUEUE_STATE_STOPPED;
282 enetc_tx_queue_release(void *txq)
287 struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq;
288 struct enetc_eth_hw *eth_hw =
289 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private);
291 struct enetc_swbd *tx_swbd;
295 /* Disable the ring */
297 val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR);
298 val &= (~ENETC_TBMR_EN);
299 enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val);
302 i = tx_ring->next_to_clean;
303 tx_swbd = &tx_ring->q_swbd[i];
304 while (tx_swbd->buffer_addr != NULL) {
305 rte_pktmbuf_free(tx_swbd->buffer_addr);
306 tx_swbd->buffer_addr = NULL;
309 if (unlikely(i == tx_ring->bd_count)) {
311 tx_swbd = &tx_ring->q_swbd[i];
315 enetc_free_bdr(tx_ring);
320 enetc_alloc_rxbdr(struct enetc_bdr *rxr,
325 size = nb_rx_desc * sizeof(struct enetc_swbd);
326 rxr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
327 if (rxr->q_swbd == NULL)
330 size = nb_rx_desc * sizeof(union enetc_rx_bd);
331 rxr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
332 if (rxr->bd_base == NULL) {
333 rte_free(rxr->q_swbd);
338 rxr->bd_count = nb_rx_desc;
339 rxr->next_to_clean = 0;
340 rxr->next_to_use = 0;
341 rxr->next_to_alloc = 0;
347 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
348 struct rte_mempool *mb_pool)
350 int idx = rx_ring->index;
352 phys_addr_t bd_address;
354 bd_address = (phys_addr_t)
355 rte_mem_virt2iova((const void *)rx_ring->bd_base);
356 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
357 lower_32_bits((uint64_t)bd_address));
358 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
359 upper_32_bits((uint64_t)bd_address));
360 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
361 ENETC_RTBLENR_LEN(rx_ring->bd_count));
363 rx_ring->mb_pool = mb_pool;
364 rx_ring->rcir = (void *)((size_t)hw->reg +
365 ENETC_BDR(RX, idx, ENETC_RBCIR));
366 enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring)));
367 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) -
368 RTE_PKTMBUF_HEADROOM);
369 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size);
370 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
374 enetc_rx_queue_setup(struct rte_eth_dev *dev,
375 uint16_t rx_queue_id,
377 unsigned int socket_id __rte_unused,
378 const struct rte_eth_rxconf *rx_conf,
379 struct rte_mempool *mb_pool)
382 struct enetc_bdr *rx_ring;
383 struct rte_eth_dev_data *data = dev->data;
384 struct enetc_eth_adapter *adapter =
385 ENETC_DEV_PRIVATE(data->dev_private);
386 uint64_t rx_offloads = data->dev_conf.rxmode.offloads;
388 PMD_INIT_FUNC_TRACE();
389 if (nb_rx_desc > MAX_BD_COUNT)
392 rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
393 if (rx_ring == NULL) {
394 ENETC_PMD_ERR("Failed to allocate RX ring memory");
399 err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc);
403 rx_ring->index = rx_queue_id;
405 enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool);
406 data->rx_queues[rx_queue_id] = rx_ring;
408 if (!rx_conf->rx_deferred_start) {
410 enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR,
412 dev->data->rx_queue_state[rx_ring->index] =
413 RTE_ETH_QUEUE_STATE_STARTED;
415 dev->data->rx_queue_state[rx_ring->index] =
416 RTE_ETH_QUEUE_STATE_STOPPED;
419 rx_ring->crc_len = (uint8_t)((rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) ?
420 RTE_ETHER_CRC_LEN : 0);
430 enetc_rx_queue_release(void *rxq)
435 struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;
436 struct enetc_eth_hw *eth_hw =
437 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private);
438 struct enetc_swbd *q_swbd;
443 /* Disable the ring */
445 val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR);
446 val &= (~ENETC_RBMR_EN);
447 enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val);
450 i = rx_ring->next_to_clean;
451 q_swbd = &rx_ring->q_swbd[i];
452 while (i != rx_ring->next_to_use) {
453 rte_pktmbuf_free(q_swbd->buffer_addr);
454 q_swbd->buffer_addr = NULL;
457 if (unlikely(i == rx_ring->bd_count)) {
459 q_swbd = &rx_ring->q_swbd[i];
463 enetc_free_bdr(rx_ring);
468 int enetc_stats_get(struct rte_eth_dev *dev,
469 struct rte_eth_stats *stats)
471 struct enetc_eth_hw *hw =
472 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
473 struct enetc_hw *enetc_hw = &hw->hw;
475 /* Total received packets, bad + good, if we want to get counters of
476 * only good received packets then use ENETC_PM0_RFRM,
477 * ENETC_PM0_TFRM registers.
479 stats->ipackets = enetc_port_rd(enetc_hw, ENETC_PM0_RPKT);
480 stats->opackets = enetc_port_rd(enetc_hw, ENETC_PM0_TPKT);
481 stats->ibytes = enetc_port_rd(enetc_hw, ENETC_PM0_REOCT);
482 stats->obytes = enetc_port_rd(enetc_hw, ENETC_PM0_TEOCT);
483 /* Dropped + Truncated packets, use ENETC_PM0_RDRNTP for without
486 stats->imissed = enetc_port_rd(enetc_hw, ENETC_PM0_RDRP);
487 stats->ierrors = enetc_port_rd(enetc_hw, ENETC_PM0_RERR);
488 stats->oerrors = enetc_port_rd(enetc_hw, ENETC_PM0_TERR);
494 enetc_stats_reset(struct rte_eth_dev *dev)
496 struct enetc_eth_hw *hw =
497 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
498 struct enetc_hw *enetc_hw = &hw->hw;
500 enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS);
504 enetc_dev_close(struct rte_eth_dev *dev)
508 PMD_INIT_FUNC_TRACE();
511 for (i = 0; i < dev->data->nb_rx_queues; i++) {
512 enetc_rx_queue_release(dev->data->rx_queues[i]);
513 dev->data->rx_queues[i] = NULL;
515 dev->data->nb_rx_queues = 0;
517 for (i = 0; i < dev->data->nb_tx_queues; i++) {
518 enetc_tx_queue_release(dev->data->tx_queues[i]);
519 dev->data->tx_queues[i] = NULL;
521 dev->data->nb_tx_queues = 0;
525 enetc_promiscuous_enable(struct rte_eth_dev *dev)
527 struct enetc_eth_hw *hw =
528 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
529 struct enetc_hw *enetc_hw = &hw->hw;
532 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
534 /* Setting to enable promiscuous mode*/
535 psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
537 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
541 enetc_promiscuous_disable(struct rte_eth_dev *dev)
543 struct enetc_eth_hw *hw =
544 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 struct enetc_hw *enetc_hw = &hw->hw;
548 /* Setting to disable promiscuous mode for SI0*/
549 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
550 psipmr &= (~ENETC_PSIPMR_SET_UP(0));
552 if (dev->data->all_multicast == 0)
553 psipmr &= (~ENETC_PSIPMR_SET_MP(0));
555 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
559 enetc_allmulticast_enable(struct rte_eth_dev *dev)
561 struct enetc_eth_hw *hw =
562 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
563 struct enetc_hw *enetc_hw = &hw->hw;
566 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
568 /* Setting to enable allmulticast mode for SI0*/
569 psipmr |= ENETC_PSIPMR_SET_MP(0);
571 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
575 enetc_allmulticast_disable(struct rte_eth_dev *dev)
577 struct enetc_eth_hw *hw =
578 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
579 struct enetc_hw *enetc_hw = &hw->hw;
582 if (dev->data->promiscuous == 1)
583 return; /* must remain in all_multicast mode */
585 /* Setting to disable all multicast mode for SI0*/
586 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) &
587 ~(ENETC_PSIPMR_SET_MP(0));
589 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
593 enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
595 struct enetc_eth_hw *hw =
596 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
597 struct enetc_hw *enetc_hw = &hw->hw;
598 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
600 /* check that mtu is within the allowed range */
601 if (mtu < ENETC_MAC_MINFRM_SIZE || frame_size > ENETC_MAC_MAXFRM_SIZE)
605 * Refuse mtu that requires the support of scattered packets
606 * when this feature has not been enabled before.
608 if (dev->data->min_rx_buf_size &&
609 !dev->data->scattered_rx && frame_size >
610 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
611 ENETC_PMD_ERR("SG not enabled, will not fit in one buffer");
615 if (frame_size > RTE_ETHER_MAX_LEN)
616 dev->data->dev_conf.rxmode.offloads &=
617 DEV_RX_OFFLOAD_JUMBO_FRAME;
619 dev->data->dev_conf.rxmode.offloads &=
620 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
622 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
623 enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
625 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
628 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) |
629 ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE));
635 enetc_dev_configure(struct rte_eth_dev *dev)
637 struct enetc_eth_hw *hw =
638 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
639 struct enetc_hw *enetc_hw = &hw->hw;
640 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
641 uint64_t rx_offloads = eth_conf->rxmode.offloads;
642 uint32_t checksum = L3_CKSUM | L4_CKSUM;
644 PMD_INIT_FUNC_TRACE();
646 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
649 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
651 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM,
652 ENETC_SET_MAXFRM(max_len));
653 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0),
654 ENETC_MAC_MAXFRM_SIZE);
655 enetc_port_wr(enetc_hw, ENETC_PTXMBAR,
656 2 * ENETC_MAC_MAXFRM_SIZE);
657 dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
661 if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
664 config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
665 config |= ENETC_PM0_CRC;
666 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config);
669 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
670 checksum &= ~L3_CKSUM;
672 if (rx_offloads & (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM))
673 checksum &= ~L4_CKSUM;
675 enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum);
682 enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
684 struct enetc_eth_adapter *priv =
685 ENETC_DEV_PRIVATE(dev->data->dev_private);
686 struct enetc_bdr *rx_ring;
689 rx_ring = dev->data->rx_queues[qidx];
690 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
691 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
693 rx_data = rx_data | ENETC_RBMR_EN;
694 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
696 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
703 enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
705 struct enetc_eth_adapter *priv =
706 ENETC_DEV_PRIVATE(dev->data->dev_private);
707 struct enetc_bdr *rx_ring;
710 rx_ring = dev->data->rx_queues[qidx];
711 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
712 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
714 rx_data = rx_data & (~ENETC_RBMR_EN);
715 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
717 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
724 enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
726 struct enetc_eth_adapter *priv =
727 ENETC_DEV_PRIVATE(dev->data->dev_private);
728 struct enetc_bdr *tx_ring;
731 tx_ring = dev->data->tx_queues[qidx];
732 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
733 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
735 tx_data = tx_data | ENETC_TBMR_EN;
736 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
738 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
745 enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
747 struct enetc_eth_adapter *priv =
748 ENETC_DEV_PRIVATE(dev->data->dev_private);
749 struct enetc_bdr *tx_ring;
752 tx_ring = dev->data->tx_queues[qidx];
753 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
754 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
756 tx_data = tx_data & (~ENETC_TBMR_EN);
757 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
759 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
766 * The set of PCI devices this driver supports
768 static const struct rte_pci_id pci_id_enetc_map[] = {
769 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) },
770 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) },
771 { .vendor_id = 0, /* sentinel */ },
774 /* Features supported by this driver */
775 static const struct eth_dev_ops enetc_ops = {
776 .dev_configure = enetc_dev_configure,
777 .dev_start = enetc_dev_start,
778 .dev_stop = enetc_dev_stop,
779 .dev_close = enetc_dev_close,
780 .link_update = enetc_link_update,
781 .stats_get = enetc_stats_get,
782 .stats_reset = enetc_stats_reset,
783 .promiscuous_enable = enetc_promiscuous_enable,
784 .promiscuous_disable = enetc_promiscuous_disable,
785 .allmulticast_enable = enetc_allmulticast_enable,
786 .allmulticast_disable = enetc_allmulticast_disable,
787 .dev_infos_get = enetc_dev_infos_get,
788 .mtu_set = enetc_mtu_set,
789 .rx_queue_setup = enetc_rx_queue_setup,
790 .rx_queue_start = enetc_rx_queue_start,
791 .rx_queue_stop = enetc_rx_queue_stop,
792 .rx_queue_release = enetc_rx_queue_release,
793 .tx_queue_setup = enetc_tx_queue_setup,
794 .tx_queue_start = enetc_tx_queue_start,
795 .tx_queue_stop = enetc_tx_queue_stop,
796 .tx_queue_release = enetc_tx_queue_release,
797 .dev_supported_ptypes_get = enetc_supported_ptypes_get,
801 * Initialisation of the enetc device
804 * - Pointer to the structure rte_eth_dev
807 * - On success, zero.
808 * - On failure, negative value.
811 enetc_dev_init(struct rte_eth_dev *eth_dev)
814 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
815 struct enetc_eth_hw *hw =
816 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
818 PMD_INIT_FUNC_TRACE();
819 eth_dev->dev_ops = &enetc_ops;
820 eth_dev->rx_pkt_burst = &enetc_recv_pkts;
821 eth_dev->tx_pkt_burst = &enetc_xmit_pkts;
823 /* Retrieving and storing the HW base address of device */
824 hw->hw.reg = (void *)pci_dev->mem_resource[0].addr;
825 hw->device_id = pci_dev->id.device_id;
827 error = enetc_hardware_init(hw);
829 ENETC_PMD_ERR("Hardware initialization failed");
833 /* Allocate memory for storing MAC addresses */
834 eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth",
835 RTE_ETHER_ADDR_LEN, 0);
836 if (!eth_dev->data->mac_addrs) {
837 ENETC_PMD_ERR("Failed to allocate %d bytes needed to "
838 "store MAC addresses",
839 RTE_ETHER_ADDR_LEN * 1);
844 /* Copy the permanent MAC address */
845 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
846 ð_dev->data->mac_addrs[0]);
849 enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM,
850 ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN));
851 eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
854 ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x",
855 eth_dev->data->port_id, pci_dev->id.vendor_id,
856 pci_dev->id.device_id);
861 enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused)
863 PMD_INIT_FUNC_TRACE();
868 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
869 struct rte_pci_device *pci_dev)
871 return rte_eth_dev_pci_generic_probe(pci_dev,
872 sizeof(struct enetc_eth_adapter),
877 enetc_pci_remove(struct rte_pci_device *pci_dev)
879 return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit);
882 static struct rte_pci_driver rte_enetc_pmd = {
883 .id_table = pci_id_enetc_map,
884 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
885 .probe = enetc_pci_probe,
886 .remove = enetc_pci_remove,
889 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd);
890 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map);
891 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci");
893 RTE_INIT(enetc_pmd_init_log)
895 enetc_logtype_pmd = rte_log_register("pmd.net.enetc");
896 if (enetc_logtype_pmd >= 0)
897 rte_log_set_level(enetc_logtype_pmd, RTE_LOG_NOTICE);