1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2019 NXP
6 #include <rte_ethdev_pci.h>
8 #include "enetc_logs.h"
11 int enetc_logtype_pmd;
14 enetc_dev_start(struct rte_eth_dev *dev)
16 struct enetc_eth_hw *hw =
17 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
18 struct enetc_hw *enetc_hw = &hw->hw;
21 PMD_INIT_FUNC_TRACE();
22 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
23 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
24 val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
27 val = enetc_port_rd(enetc_hw, ENETC_PMR);
28 enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN);
30 /* set auto-speed for RGMII */
31 if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) {
32 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
33 ENETC_PM0_IFM_RGAUTO);
34 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
35 ENETC_PM0_IFM_RGAUTO);
37 if (enetc_global_rd(enetc_hw,
38 ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) {
39 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
41 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
49 enetc_dev_stop(struct rte_eth_dev *dev)
51 struct enetc_eth_hw *hw =
52 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
53 struct enetc_hw *enetc_hw = &hw->hw;
56 PMD_INIT_FUNC_TRACE();
58 val = enetc_port_rd(enetc_hw, ENETC_PMR);
59 enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN));
61 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
62 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
63 val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN)));
66 static const uint32_t *
67 enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
69 static const uint32_t ptypes[] = {
83 /* return 0 means link status changed, -1 means not changed */
85 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
87 struct enetc_eth_hw *hw =
88 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
89 struct enetc_hw *enetc_hw = &hw->hw;
90 struct rte_eth_link link;
93 PMD_INIT_FUNC_TRACE();
95 memset(&link, 0, sizeof(link));
97 status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS);
99 if (status & ENETC_LINK_MODE)
100 link.link_duplex = ETH_LINK_FULL_DUPLEX;
102 link.link_duplex = ETH_LINK_HALF_DUPLEX;
104 if (status & ENETC_LINK_STATUS)
105 link.link_status = ETH_LINK_UP;
107 link.link_status = ETH_LINK_DOWN;
109 switch (status & ENETC_LINK_SPEED_MASK) {
110 case ENETC_LINK_SPEED_1G:
111 link.link_speed = ETH_SPEED_NUM_1G;
114 case ENETC_LINK_SPEED_100M:
115 link.link_speed = ETH_SPEED_NUM_100M;
119 case ENETC_LINK_SPEED_10M:
120 link.link_speed = ETH_SPEED_NUM_10M;
123 return rte_eth_linkstatus_set(dev, &link);
127 enetc_hardware_init(struct enetc_eth_hw *hw)
129 struct enetc_hw *enetc_hw = &hw->hw;
130 uint32_t *mac = (uint32_t *)hw->mac.addr;
132 PMD_INIT_FUNC_TRACE();
133 /* Calculating and storing the base HW addresses */
134 hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE);
135 hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE);
137 /* Enabling Station Interface */
138 enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);
140 *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0));
142 *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0));
148 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
149 struct rte_eth_dev_info *dev_info)
151 PMD_INIT_FUNC_TRACE();
152 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
153 .nb_max = MAX_BD_COUNT,
154 .nb_min = MIN_BD_COUNT,
155 .nb_align = BD_ALIGN,
157 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
158 .nb_max = MAX_BD_COUNT,
159 .nb_min = MIN_BD_COUNT,
160 .nb_align = BD_ALIGN,
162 dev_info->max_rx_queues = MAX_RX_RINGS;
163 dev_info->max_tx_queues = MAX_TX_RINGS;
164 dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE;
165 dev_info->rx_offload_capa =
166 (DEV_RX_OFFLOAD_IPV4_CKSUM |
167 DEV_RX_OFFLOAD_UDP_CKSUM |
168 DEV_RX_OFFLOAD_TCP_CKSUM |
169 DEV_RX_OFFLOAD_KEEP_CRC |
170 DEV_RX_OFFLOAD_JUMBO_FRAME);
176 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc)
180 size = nb_desc * sizeof(struct enetc_swbd);
181 txr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
182 if (txr->q_swbd == NULL)
185 size = nb_desc * sizeof(struct enetc_tx_bd);
186 txr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
187 if (txr->bd_base == NULL) {
188 rte_free(txr->q_swbd);
193 txr->bd_count = nb_desc;
194 txr->next_to_clean = 0;
195 txr->next_to_use = 0;
201 enetc_free_bdr(struct enetc_bdr *rxr)
203 rte_free(rxr->q_swbd);
204 rte_free(rxr->bd_base);
210 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
212 int idx = tx_ring->index;
213 phys_addr_t bd_address;
215 bd_address = (phys_addr_t)
216 rte_mem_virt2iova((const void *)tx_ring->bd_base);
217 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
218 lower_32_bits((uint64_t)bd_address));
219 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
220 upper_32_bits((uint64_t)bd_address));
221 enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
222 ENETC_RTBLENR_LEN(tx_ring->bd_count));
224 enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
225 enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0);
226 tx_ring->tcir = (void *)((size_t)hw->reg +
227 ENETC_BDR(TX, idx, ENETC_TBCIR));
228 tx_ring->tcisr = (void *)((size_t)hw->reg +
229 ENETC_BDR(TX, idx, ENETC_TBCISR));
233 enetc_tx_queue_setup(struct rte_eth_dev *dev,
236 unsigned int socket_id __rte_unused,
237 const struct rte_eth_txconf *tx_conf)
240 struct enetc_bdr *tx_ring;
241 struct rte_eth_dev_data *data = dev->data;
242 struct enetc_eth_adapter *priv =
243 ENETC_DEV_PRIVATE(data->dev_private);
245 PMD_INIT_FUNC_TRACE();
246 if (nb_desc > MAX_BD_COUNT)
249 tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
250 if (tx_ring == NULL) {
251 ENETC_PMD_ERR("Failed to allocate TX ring memory");
256 err = enetc_alloc_txbdr(tx_ring, nb_desc);
260 tx_ring->index = queue_idx;
262 enetc_setup_txbdr(&priv->hw.hw, tx_ring);
263 data->tx_queues[queue_idx] = tx_ring;
265 if (!tx_conf->tx_deferred_start) {
267 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index,
268 ENETC_TBMR, ENETC_TBMR_EN);
269 dev->data->tx_queue_state[tx_ring->index] =
270 RTE_ETH_QUEUE_STATE_STARTED;
272 dev->data->tx_queue_state[tx_ring->index] =
273 RTE_ETH_QUEUE_STATE_STOPPED;
284 enetc_tx_queue_release(void *txq)
289 struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq;
290 struct enetc_eth_hw *eth_hw =
291 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private);
293 struct enetc_swbd *tx_swbd;
297 /* Disable the ring */
299 val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR);
300 val &= (~ENETC_TBMR_EN);
301 enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val);
304 i = tx_ring->next_to_clean;
305 tx_swbd = &tx_ring->q_swbd[i];
306 while (tx_swbd->buffer_addr != NULL) {
307 rte_pktmbuf_free(tx_swbd->buffer_addr);
308 tx_swbd->buffer_addr = NULL;
311 if (unlikely(i == tx_ring->bd_count)) {
313 tx_swbd = &tx_ring->q_swbd[i];
317 enetc_free_bdr(tx_ring);
322 enetc_alloc_rxbdr(struct enetc_bdr *rxr,
327 size = nb_rx_desc * sizeof(struct enetc_swbd);
328 rxr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
329 if (rxr->q_swbd == NULL)
332 size = nb_rx_desc * sizeof(union enetc_rx_bd);
333 rxr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
334 if (rxr->bd_base == NULL) {
335 rte_free(rxr->q_swbd);
340 rxr->bd_count = nb_rx_desc;
341 rxr->next_to_clean = 0;
342 rxr->next_to_use = 0;
343 rxr->next_to_alloc = 0;
349 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
350 struct rte_mempool *mb_pool)
352 int idx = rx_ring->index;
354 phys_addr_t bd_address;
356 bd_address = (phys_addr_t)
357 rte_mem_virt2iova((const void *)rx_ring->bd_base);
358 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
359 lower_32_bits((uint64_t)bd_address));
360 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
361 upper_32_bits((uint64_t)bd_address));
362 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
363 ENETC_RTBLENR_LEN(rx_ring->bd_count));
365 rx_ring->mb_pool = mb_pool;
366 rx_ring->rcir = (void *)((size_t)hw->reg +
367 ENETC_BDR(RX, idx, ENETC_RBCIR));
368 enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring)));
369 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) -
370 RTE_PKTMBUF_HEADROOM);
371 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size);
372 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
376 enetc_rx_queue_setup(struct rte_eth_dev *dev,
377 uint16_t rx_queue_id,
379 unsigned int socket_id __rte_unused,
380 const struct rte_eth_rxconf *rx_conf,
381 struct rte_mempool *mb_pool)
384 struct enetc_bdr *rx_ring;
385 struct rte_eth_dev_data *data = dev->data;
386 struct enetc_eth_adapter *adapter =
387 ENETC_DEV_PRIVATE(data->dev_private);
388 uint64_t rx_offloads = data->dev_conf.rxmode.offloads;
390 PMD_INIT_FUNC_TRACE();
391 if (nb_rx_desc > MAX_BD_COUNT)
394 rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
395 if (rx_ring == NULL) {
396 ENETC_PMD_ERR("Failed to allocate RX ring memory");
401 err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc);
405 rx_ring->index = rx_queue_id;
407 enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool);
408 data->rx_queues[rx_queue_id] = rx_ring;
410 if (!rx_conf->rx_deferred_start) {
412 enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR,
414 dev->data->rx_queue_state[rx_ring->index] =
415 RTE_ETH_QUEUE_STATE_STARTED;
417 dev->data->rx_queue_state[rx_ring->index] =
418 RTE_ETH_QUEUE_STATE_STOPPED;
421 rx_ring->crc_len = (uint8_t)((rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) ?
422 RTE_ETHER_CRC_LEN : 0);
432 enetc_rx_queue_release(void *rxq)
437 struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;
438 struct enetc_eth_hw *eth_hw =
439 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private);
440 struct enetc_swbd *q_swbd;
445 /* Disable the ring */
447 val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR);
448 val &= (~ENETC_RBMR_EN);
449 enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val);
452 i = rx_ring->next_to_clean;
453 q_swbd = &rx_ring->q_swbd[i];
454 while (i != rx_ring->next_to_use) {
455 rte_pktmbuf_free(q_swbd->buffer_addr);
456 q_swbd->buffer_addr = NULL;
459 if (unlikely(i == rx_ring->bd_count)) {
461 q_swbd = &rx_ring->q_swbd[i];
465 enetc_free_bdr(rx_ring);
470 int enetc_stats_get(struct rte_eth_dev *dev,
471 struct rte_eth_stats *stats)
473 struct enetc_eth_hw *hw =
474 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
475 struct enetc_hw *enetc_hw = &hw->hw;
477 /* Total received packets, bad + good, if we want to get counters of
478 * only good received packets then use ENETC_PM0_RFRM,
479 * ENETC_PM0_TFRM registers.
481 stats->ipackets = enetc_port_rd(enetc_hw, ENETC_PM0_RPKT);
482 stats->opackets = enetc_port_rd(enetc_hw, ENETC_PM0_TPKT);
483 stats->ibytes = enetc_port_rd(enetc_hw, ENETC_PM0_REOCT);
484 stats->obytes = enetc_port_rd(enetc_hw, ENETC_PM0_TEOCT);
485 /* Dropped + Truncated packets, use ENETC_PM0_RDRNTP for without
488 stats->imissed = enetc_port_rd(enetc_hw, ENETC_PM0_RDRP);
489 stats->ierrors = enetc_port_rd(enetc_hw, ENETC_PM0_RERR);
490 stats->oerrors = enetc_port_rd(enetc_hw, ENETC_PM0_TERR);
496 enetc_stats_reset(struct rte_eth_dev *dev)
498 struct enetc_eth_hw *hw =
499 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
500 struct enetc_hw *enetc_hw = &hw->hw;
502 enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS);
506 enetc_dev_close(struct rte_eth_dev *dev)
510 PMD_INIT_FUNC_TRACE();
513 for (i = 0; i < dev->data->nb_rx_queues; i++) {
514 enetc_rx_queue_release(dev->data->rx_queues[i]);
515 dev->data->rx_queues[i] = NULL;
517 dev->data->nb_rx_queues = 0;
519 for (i = 0; i < dev->data->nb_tx_queues; i++) {
520 enetc_tx_queue_release(dev->data->tx_queues[i]);
521 dev->data->tx_queues[i] = NULL;
523 dev->data->nb_tx_queues = 0;
527 enetc_promiscuous_enable(struct rte_eth_dev *dev)
529 struct enetc_eth_hw *hw =
530 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
531 struct enetc_hw *enetc_hw = &hw->hw;
534 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
536 /* Setting to enable promiscuous mode*/
537 psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
539 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
543 enetc_promiscuous_disable(struct rte_eth_dev *dev)
545 struct enetc_eth_hw *hw =
546 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
547 struct enetc_hw *enetc_hw = &hw->hw;
550 /* Setting to disable promiscuous mode for SI0*/
551 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
552 psipmr &= (~ENETC_PSIPMR_SET_UP(0));
554 if (dev->data->all_multicast == 0)
555 psipmr &= (~ENETC_PSIPMR_SET_MP(0));
557 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
561 enetc_allmulticast_enable(struct rte_eth_dev *dev)
563 struct enetc_eth_hw *hw =
564 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
565 struct enetc_hw *enetc_hw = &hw->hw;
568 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
570 /* Setting to enable allmulticast mode for SI0*/
571 psipmr |= ENETC_PSIPMR_SET_MP(0);
573 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
577 enetc_allmulticast_disable(struct rte_eth_dev *dev)
579 struct enetc_eth_hw *hw =
580 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
581 struct enetc_hw *enetc_hw = &hw->hw;
584 if (dev->data->promiscuous == 1)
585 return; /* must remain in all_multicast mode */
587 /* Setting to disable all multicast mode for SI0*/
588 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) &
589 ~(ENETC_PSIPMR_SET_MP(0));
591 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
595 enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
597 struct enetc_eth_hw *hw =
598 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
599 struct enetc_hw *enetc_hw = &hw->hw;
600 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
602 /* check that mtu is within the allowed range */
603 if (mtu < ENETC_MAC_MINFRM_SIZE || frame_size > ENETC_MAC_MAXFRM_SIZE)
607 * Refuse mtu that requires the support of scattered packets
608 * when this feature has not been enabled before.
610 if (dev->data->min_rx_buf_size &&
611 !dev->data->scattered_rx && frame_size >
612 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
613 ENETC_PMD_ERR("SG not enabled, will not fit in one buffer");
617 if (frame_size > RTE_ETHER_MAX_LEN)
618 dev->data->dev_conf.rxmode.offloads &=
619 DEV_RX_OFFLOAD_JUMBO_FRAME;
621 dev->data->dev_conf.rxmode.offloads &=
622 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
624 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
625 enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
627 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
630 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) |
631 ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE));
637 enetc_dev_configure(struct rte_eth_dev *dev)
639 struct enetc_eth_hw *hw =
640 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
641 struct enetc_hw *enetc_hw = &hw->hw;
642 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
643 uint64_t rx_offloads = eth_conf->rxmode.offloads;
644 uint32_t checksum = L3_CKSUM | L4_CKSUM;
646 PMD_INIT_FUNC_TRACE();
648 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
651 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
653 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM,
654 ENETC_SET_MAXFRM(max_len));
655 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0),
656 ENETC_MAC_MAXFRM_SIZE);
657 enetc_port_wr(enetc_hw, ENETC_PTXMBAR,
658 2 * ENETC_MAC_MAXFRM_SIZE);
659 dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
663 if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
666 config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
667 config |= ENETC_PM0_CRC;
668 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config);
671 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
672 checksum &= ~L3_CKSUM;
674 if (rx_offloads & (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM))
675 checksum &= ~L4_CKSUM;
677 enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum);
684 enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
686 struct enetc_eth_adapter *priv =
687 ENETC_DEV_PRIVATE(dev->data->dev_private);
688 struct enetc_bdr *rx_ring;
691 rx_ring = dev->data->rx_queues[qidx];
692 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
693 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
695 rx_data = rx_data | ENETC_RBMR_EN;
696 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
698 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
705 enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
707 struct enetc_eth_adapter *priv =
708 ENETC_DEV_PRIVATE(dev->data->dev_private);
709 struct enetc_bdr *rx_ring;
712 rx_ring = dev->data->rx_queues[qidx];
713 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
714 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
716 rx_data = rx_data & (~ENETC_RBMR_EN);
717 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
719 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
726 enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
728 struct enetc_eth_adapter *priv =
729 ENETC_DEV_PRIVATE(dev->data->dev_private);
730 struct enetc_bdr *tx_ring;
733 tx_ring = dev->data->tx_queues[qidx];
734 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
735 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
737 tx_data = tx_data | ENETC_TBMR_EN;
738 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
740 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
747 enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
749 struct enetc_eth_adapter *priv =
750 ENETC_DEV_PRIVATE(dev->data->dev_private);
751 struct enetc_bdr *tx_ring;
754 tx_ring = dev->data->tx_queues[qidx];
755 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
756 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
758 tx_data = tx_data & (~ENETC_TBMR_EN);
759 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
761 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
768 * The set of PCI devices this driver supports
770 static const struct rte_pci_id pci_id_enetc_map[] = {
771 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) },
772 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) },
773 { .vendor_id = 0, /* sentinel */ },
776 /* Features supported by this driver */
777 static const struct eth_dev_ops enetc_ops = {
778 .dev_configure = enetc_dev_configure,
779 .dev_start = enetc_dev_start,
780 .dev_stop = enetc_dev_stop,
781 .dev_close = enetc_dev_close,
782 .link_update = enetc_link_update,
783 .stats_get = enetc_stats_get,
784 .stats_reset = enetc_stats_reset,
785 .promiscuous_enable = enetc_promiscuous_enable,
786 .promiscuous_disable = enetc_promiscuous_disable,
787 .allmulticast_enable = enetc_allmulticast_enable,
788 .allmulticast_disable = enetc_allmulticast_disable,
789 .dev_infos_get = enetc_dev_infos_get,
790 .mtu_set = enetc_mtu_set,
791 .rx_queue_setup = enetc_rx_queue_setup,
792 .rx_queue_start = enetc_rx_queue_start,
793 .rx_queue_stop = enetc_rx_queue_stop,
794 .rx_queue_release = enetc_rx_queue_release,
795 .tx_queue_setup = enetc_tx_queue_setup,
796 .tx_queue_start = enetc_tx_queue_start,
797 .tx_queue_stop = enetc_tx_queue_stop,
798 .tx_queue_release = enetc_tx_queue_release,
799 .dev_supported_ptypes_get = enetc_supported_ptypes_get,
803 * Initialisation of the enetc device
806 * - Pointer to the structure rte_eth_dev
809 * - On success, zero.
810 * - On failure, negative value.
813 enetc_dev_init(struct rte_eth_dev *eth_dev)
816 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
817 struct enetc_eth_hw *hw =
818 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
820 PMD_INIT_FUNC_TRACE();
821 eth_dev->dev_ops = &enetc_ops;
822 eth_dev->rx_pkt_burst = &enetc_recv_pkts;
823 eth_dev->tx_pkt_burst = &enetc_xmit_pkts;
825 /* Retrieving and storing the HW base address of device */
826 hw->hw.reg = (void *)pci_dev->mem_resource[0].addr;
827 hw->device_id = pci_dev->id.device_id;
829 error = enetc_hardware_init(hw);
831 ENETC_PMD_ERR("Hardware initialization failed");
835 /* Allocate memory for storing MAC addresses */
836 eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth",
837 RTE_ETHER_ADDR_LEN, 0);
838 if (!eth_dev->data->mac_addrs) {
839 ENETC_PMD_ERR("Failed to allocate %d bytes needed to "
840 "store MAC addresses",
841 RTE_ETHER_ADDR_LEN * 1);
846 /* Copy the permanent MAC address */
847 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
848 ð_dev->data->mac_addrs[0]);
851 enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM,
852 ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN));
853 eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
856 ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x",
857 eth_dev->data->port_id, pci_dev->id.vendor_id,
858 pci_dev->id.device_id);
863 enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused)
865 PMD_INIT_FUNC_TRACE();
870 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
871 struct rte_pci_device *pci_dev)
873 return rte_eth_dev_pci_generic_probe(pci_dev,
874 sizeof(struct enetc_eth_adapter),
879 enetc_pci_remove(struct rte_pci_device *pci_dev)
881 return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit);
884 static struct rte_pci_driver rte_enetc_pmd = {
885 .id_table = pci_id_enetc_map,
886 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
887 .probe = enetc_pci_probe,
888 .remove = enetc_pci_remove,
891 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd);
892 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map);
893 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci");
895 RTE_INIT(enetc_pmd_init_log)
897 enetc_logtype_pmd = rte_log_register("pmd.net.enetc");
898 if (enetc_logtype_pmd >= 0)
899 rte_log_set_level(enetc_logtype_pmd, RTE_LOG_NOTICE);