1 /* SPDX-License-Identifier: BSD-3-Clause
6 #include <rte_ethdev_pci.h>
8 #include "enetc_logs.h"
11 int enetc_logtype_pmd;
13 /* Functions Prototypes */
14 static int enetc_dev_configure(struct rte_eth_dev *dev);
15 static int enetc_dev_start(struct rte_eth_dev *dev);
16 static void enetc_dev_stop(struct rte_eth_dev *dev);
17 static void enetc_dev_close(struct rte_eth_dev *dev);
18 static void enetc_dev_infos_get(struct rte_eth_dev *dev,
19 struct rte_eth_dev_info *dev_info);
20 static int enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete);
21 static int enetc_hardware_init(struct enetc_eth_hw *hw);
22 static int enetc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
23 uint16_t nb_rx_desc, unsigned int socket_id,
24 const struct rte_eth_rxconf *rx_conf,
25 struct rte_mempool *mb_pool);
26 static void enetc_rx_queue_release(void *rxq);
27 static int enetc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
28 uint16_t nb_tx_desc, unsigned int socket_id,
29 const struct rte_eth_txconf *tx_conf);
30 static void enetc_tx_queue_release(void *txq);
33 * The set of PCI devices this driver supports
35 static const struct rte_pci_id pci_id_enetc_map[] = {
36 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) },
37 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) },
38 { .vendor_id = 0, /* sentinel */ },
41 /* Features supported by this driver */
42 static const struct eth_dev_ops enetc_ops = {
43 .dev_configure = enetc_dev_configure,
44 .dev_start = enetc_dev_start,
45 .dev_stop = enetc_dev_stop,
46 .dev_close = enetc_dev_close,
47 .link_update = enetc_link_update,
48 .dev_infos_get = enetc_dev_infos_get,
49 .rx_queue_setup = enetc_rx_queue_setup,
50 .rx_queue_release = enetc_rx_queue_release,
51 .tx_queue_setup = enetc_tx_queue_setup,
52 .tx_queue_release = enetc_tx_queue_release,
56 * Initialisation of the enetc device
59 * - Pointer to the structure rte_eth_dev
63 * - On failure, negative value.
66 enetc_dev_init(struct rte_eth_dev *eth_dev)
69 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
70 struct enetc_eth_hw *hw =
71 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
73 PMD_INIT_FUNC_TRACE();
74 eth_dev->dev_ops = &enetc_ops;
75 eth_dev->rx_pkt_burst = &enetc_recv_pkts;
76 eth_dev->tx_pkt_burst = &enetc_xmit_pkts;
78 /* Retrieving and storing the HW base address of device */
79 hw->hw.reg = (void *)pci_dev->mem_resource[0].addr;
80 hw->device_id = pci_dev->id.device_id;
82 error = enetc_hardware_init(hw);
84 ENETC_PMD_ERR("Hardware initialization failed");
88 /* Allocate memory for storing MAC addresses */
89 eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth", ETHER_ADDR_LEN, 0);
90 if (!eth_dev->data->mac_addrs) {
91 ENETC_PMD_ERR("Failed to allocate %d bytes needed to "
92 "store MAC addresses",
98 /* Copy the permanent MAC address */
99 ether_addr_copy((struct ether_addr *)hw->mac.addr,
100 ð_dev->data->mac_addrs[0]);
102 ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x",
103 eth_dev->data->port_id, pci_dev->id.vendor_id,
104 pci_dev->id.device_id);
109 enetc_dev_uninit(struct rte_eth_dev *eth_dev)
111 PMD_INIT_FUNC_TRACE();
112 rte_free(eth_dev->data->mac_addrs);
118 enetc_dev_configure(struct rte_eth_dev *dev __rte_unused)
120 PMD_INIT_FUNC_TRACE();
125 enetc_dev_start(struct rte_eth_dev *dev)
127 struct enetc_eth_hw *hw =
128 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
131 PMD_INIT_FUNC_TRACE();
132 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port,
134 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG),
135 val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
138 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR));
139 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR),
146 enetc_dev_stop(struct rte_eth_dev *dev)
148 struct enetc_eth_hw *hw =
149 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
152 PMD_INIT_FUNC_TRACE();
154 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR));
155 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR),
156 val & (~ENETC_PMR_EN));
158 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port,
160 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG),
161 val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN)));
165 enetc_dev_close(struct rte_eth_dev *dev)
169 PMD_INIT_FUNC_TRACE();
172 for (i = 0; i < dev->data->nb_rx_queues; i++) {
173 enetc_rx_queue_release(dev->data->rx_queues[i]);
174 dev->data->rx_queues[i] = NULL;
176 dev->data->nb_rx_queues = 0;
178 for (i = 0; i < dev->data->nb_tx_queues; i++) {
179 enetc_tx_queue_release(dev->data->tx_queues[i]);
180 dev->data->tx_queues[i] = NULL;
182 dev->data->nb_tx_queues = 0;
185 /* return 0 means link status changed, -1 means not changed */
187 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
189 struct enetc_eth_hw *hw =
190 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
191 struct rte_eth_link link;
194 PMD_INIT_FUNC_TRACE();
196 memset(&link, 0, sizeof(link));
198 status = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port,
201 if (status & ENETC_LINK_MODE)
202 link.link_duplex = ETH_LINK_FULL_DUPLEX;
204 link.link_duplex = ETH_LINK_HALF_DUPLEX;
206 if (status & ENETC_LINK_STATUS)
207 link.link_status = ETH_LINK_UP;
209 link.link_status = ETH_LINK_DOWN;
211 switch (status & ENETC_LINK_SPEED_MASK) {
212 case ENETC_LINK_SPEED_1G:
213 link.link_speed = ETH_SPEED_NUM_1G;
216 case ENETC_LINK_SPEED_100M:
217 link.link_speed = ETH_SPEED_NUM_100M;
221 case ENETC_LINK_SPEED_10M:
222 link.link_speed = ETH_SPEED_NUM_10M;
225 return rte_eth_linkstatus_set(dev, &link);
229 enetc_hardware_init(struct enetc_eth_hw *hw)
233 PMD_INIT_FUNC_TRACE();
234 /* Calculating and storing the base HW addresses */
235 hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE);
236 hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE);
238 /* Enabling Station Interface */
239 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.reg, ENETC_SIMR),
242 /* Setting to accept broadcast packets for each inetrface */
243 psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0) |
244 ENETC_PSIPMR_SET_VLAN_MP(0);
245 psipmr |= ENETC_PSIPMR_SET_UP(1) | ENETC_PSIPMR_SET_MP(1) |
246 ENETC_PSIPMR_SET_VLAN_MP(1);
247 psipmr |= ENETC_PSIPMR_SET_UP(2) | ENETC_PSIPMR_SET_MP(2) |
248 ENETC_PSIPMR_SET_VLAN_MP(2);
250 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMR),
253 /* Enabling broadcast address */
254 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR0(0)),
256 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR1(0)),
263 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
264 struct rte_eth_dev_info *dev_info)
266 PMD_INIT_FUNC_TRACE();
267 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
268 .nb_max = MAX_BD_COUNT,
269 .nb_min = MIN_BD_COUNT,
270 .nb_align = BD_ALIGN,
272 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
273 .nb_max = MAX_BD_COUNT,
274 .nb_min = MIN_BD_COUNT,
275 .nb_align = BD_ALIGN,
277 dev_info->max_rx_queues = MAX_RX_RINGS;
278 dev_info->max_tx_queues = MAX_TX_RINGS;
279 dev_info->max_rx_pktlen = 1500;
283 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc)
287 size = nb_desc * sizeof(struct enetc_swbd);
288 txr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
289 if (txr->q_swbd == NULL)
292 size = nb_desc * sizeof(struct enetc_tx_bd);
293 txr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
294 if (txr->bd_base == NULL) {
295 rte_free(txr->q_swbd);
300 txr->bd_count = nb_desc;
301 txr->next_to_clean = 0;
302 txr->next_to_use = 0;
308 enetc_free_bdr(struct enetc_bdr *rxr)
310 rte_free(rxr->q_swbd);
311 rte_free(rxr->bd_base);
317 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
319 int idx = tx_ring->index;
323 base_addr = (uintptr_t)tx_ring->bd_base;
324 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
325 lower_32_bits((uint64_t)base_addr));
326 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
327 upper_32_bits((uint64_t)base_addr));
328 enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
329 ENETC_RTBLENR_LEN(tx_ring->bd_count));
331 tbmr = ENETC_TBMR_EN;
333 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr);
334 enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
335 enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0);
336 tx_ring->tcir = (void *)((size_t)hw->reg +
337 ENETC_BDR(TX, idx, ENETC_TBCIR));
338 tx_ring->tcisr = (void *)((size_t)hw->reg +
339 ENETC_BDR(TX, idx, ENETC_TBCISR));
343 enetc_alloc_tx_resources(struct rte_eth_dev *dev,
348 struct enetc_bdr *tx_ring;
349 struct rte_eth_dev_data *data = dev->data;
350 struct enetc_eth_adapter *priv =
351 ENETC_DEV_PRIVATE(data->dev_private);
353 tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
354 if (tx_ring == NULL) {
355 ENETC_PMD_ERR("Failed to allocate TX ring memory");
360 err = enetc_alloc_txbdr(tx_ring, nb_desc);
364 tx_ring->index = queue_idx;
366 enetc_setup_txbdr(&priv->hw.hw, tx_ring);
367 data->tx_queues[queue_idx] = tx_ring;
377 enetc_tx_queue_setup(struct rte_eth_dev *dev,
380 unsigned int socket_id __rte_unused,
381 const struct rte_eth_txconf *tx_conf __rte_unused)
385 PMD_INIT_FUNC_TRACE();
386 if (nb_desc > MAX_BD_COUNT)
389 err = enetc_alloc_tx_resources(dev, queue_idx, nb_desc);
395 enetc_tx_queue_release(void *txq)
400 struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq;
401 struct enetc_eth_hw *eth_hw =
402 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private);
404 struct enetc_swbd *tx_swbd;
408 /* Disable the ring */
410 val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR);
411 val &= (~ENETC_TBMR_EN);
412 enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val);
415 i = tx_ring->next_to_clean;
416 tx_swbd = &tx_ring->q_swbd[i];
417 while (tx_swbd->buffer_addr != NULL) {
418 rte_pktmbuf_free(tx_swbd->buffer_addr);
419 tx_swbd->buffer_addr = NULL;
422 if (unlikely(i == tx_ring->bd_count)) {
424 tx_swbd = &tx_ring->q_swbd[i];
428 enetc_free_bdr(tx_ring);
433 enetc_alloc_rxbdr(struct enetc_bdr *rxr,
438 size = nb_rx_desc * sizeof(struct enetc_swbd);
439 rxr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
440 if (rxr->q_swbd == NULL)
443 size = nb_rx_desc * sizeof(union enetc_rx_bd);
444 rxr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
445 if (rxr->bd_base == NULL) {
446 rte_free(rxr->q_swbd);
451 rxr->bd_count = nb_rx_desc;
452 rxr->next_to_clean = 0;
453 rxr->next_to_use = 0;
454 rxr->next_to_alloc = 0;
460 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
461 struct rte_mempool *mb_pool)
463 int idx = rx_ring->index;
467 base_addr = (uintptr_t)rx_ring->bd_base;
468 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
469 lower_32_bits((uint64_t)base_addr));
470 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
471 upper_32_bits((uint64_t)base_addr));
472 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
473 ENETC_RTBLENR_LEN(rx_ring->bd_count));
475 rx_ring->mb_pool = mb_pool;
477 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, ENETC_RBMR_EN);
478 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
479 rx_ring->rcir = (void *)((size_t)hw->reg +
480 ENETC_BDR(RX, idx, ENETC_RBCIR));
481 enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring)));
482 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) -
483 RTE_PKTMBUF_HEADROOM);
484 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size);
488 enetc_alloc_rx_resources(struct rte_eth_dev *dev,
489 uint16_t rx_queue_id,
491 struct rte_mempool *mb_pool)
494 struct enetc_bdr *rx_ring;
495 struct rte_eth_dev_data *data = dev->data;
496 struct enetc_eth_adapter *adapter =
497 ENETC_DEV_PRIVATE(data->dev_private);
499 rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
500 if (rx_ring == NULL) {
501 ENETC_PMD_ERR("Failed to allocate RX ring memory");
506 err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc);
510 rx_ring->index = rx_queue_id;
512 enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool);
513 data->rx_queues[rx_queue_id] = rx_ring;
523 enetc_rx_queue_setup(struct rte_eth_dev *dev,
524 uint16_t rx_queue_id,
526 unsigned int socket_id __rte_unused,
527 const struct rte_eth_rxconf *rx_conf __rte_unused,
528 struct rte_mempool *mb_pool)
532 PMD_INIT_FUNC_TRACE();
533 if (nb_rx_desc > MAX_BD_COUNT)
536 err = enetc_alloc_rx_resources(dev, rx_queue_id,
544 enetc_rx_queue_release(void *rxq)
549 struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;
550 struct enetc_eth_hw *eth_hw =
551 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private);
552 struct enetc_swbd *q_swbd;
557 /* Disable the ring */
559 val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR);
560 val &= (~ENETC_RBMR_EN);
561 enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val);
564 i = rx_ring->next_to_clean;
565 q_swbd = &rx_ring->q_swbd[i];
566 while (i != rx_ring->next_to_use) {
567 rte_pktmbuf_free(q_swbd->buffer_addr);
568 q_swbd->buffer_addr = NULL;
571 if (unlikely(i == rx_ring->bd_count)) {
573 q_swbd = &rx_ring->q_swbd[i];
577 enetc_free_bdr(rx_ring);
582 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
583 struct rte_pci_device *pci_dev)
585 return rte_eth_dev_pci_generic_probe(pci_dev,
586 sizeof(struct enetc_eth_adapter),
591 enetc_pci_remove(struct rte_pci_device *pci_dev)
593 return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit);
596 static struct rte_pci_driver rte_enetc_pmd = {
597 .id_table = pci_id_enetc_map,
598 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
599 .probe = enetc_pci_probe,
600 .remove = enetc_pci_remove,
603 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd);
604 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map);
605 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci");
607 RTE_INIT(enetc_pmd_init_log)
609 enetc_logtype_pmd = rte_log_register("pmd.net.enetc");
610 if (enetc_logtype_pmd >= 0)
611 rte_log_set_level(enetc_logtype_pmd, RTE_LOG_NOTICE);