1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020-2021 NXP
5 #ifndef __ENETFEC_ETHDEV_H__
6 #define __ENETFEC_ETHDEV_H__
8 #include <rte_ethdev.h>
11 #define ENETFEC_TX_FR_SIZE 2048
12 #define ETH_HLEN RTE_ETHER_HDR_LEN
15 #define FULL_DUPLEX 0x00
17 #define MAX_TX_BD_RING_SIZE 512 /* It should be power of 2 */
18 #define MAX_RX_BD_RING_SIZE 512
19 #define PKT_MAX_BUF_SIZE 1984
20 #define OPT_FRAME_SIZE (PKT_MAX_BUF_SIZE << 16)
21 #define ENETFEC_MAX_RX_PKT_LEN 3000
24 #if defined(RTE_ARCH_ARM)
25 #if defined(RTE_ARCH_64)
26 #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
27 #define dcbf_64(p) dcbf(p)
29 #else /* RTE_ARCH_32 */
30 #define dcbf(p) RTE_SET_USED(p)
31 #define dcbf_64(p) dcbf(p)
35 #define dcbf(p) RTE_SET_USED(p)
36 #define dcbf_64(p) dcbf(p)
40 * ENETFEC can support 1 rx and tx queue..
43 #define ENETFEC_MAX_Q 1
45 #define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
46 #define readl(p) rte_read32(p)
49 uint16_t bd_datlen; /* buffer data length */
50 uint16_t bd_sc; /* buffer control & status */
51 uint32_t bd_bufaddr; /* buffer address */
65 /* Addresses of Tx and Rx buffers */
69 void __iomem *active_reg_desc;
70 uint64_t descr_baseaddr_p;
71 unsigned short ring_size;
73 unsigned char d_size_log2;
76 struct enetfec_priv_tx_q {
77 struct bufdesc_prop bd;
78 struct rte_mbuf *tx_mbuf[MAX_TX_BD_RING_SIZE];
79 struct bufdesc *dirty_tx;
80 struct rte_mempool *pool;
81 struct enetfec_private *fep;
84 struct enetfec_priv_rx_q {
85 struct bufdesc_prop bd;
86 struct rte_mbuf *rx_mbuf[MAX_RX_BD_RING_SIZE];
87 struct rte_mempool *pool;
88 struct enetfec_private *fep;
91 struct enetfec_private {
92 struct rte_eth_dev *dev;
93 struct rte_eth_stats stats;
99 uint32_t enetfec_e_cntl;
100 uint16_t max_rx_queues;
101 uint16_t max_tx_queues;
102 unsigned int total_tx_ring_size;
103 unsigned int total_rx_ring_size;
104 unsigned int reg_size;
105 unsigned int bd_size;
107 bool rgmii_txc_delay;
108 bool rgmii_rxc_delay;
111 uint32_t hw_baseaddr_p;
113 uint32_t bd_addr_p_r[ENETFEC_MAX_Q];
114 uint32_t bd_addr_p_t[ENETFEC_MAX_Q];
115 void *dma_baseaddr_r[ENETFEC_MAX_Q];
116 void *dma_baseaddr_t[ENETFEC_MAX_Q];
117 struct enetfec_priv_rx_q *rx_queues[ENETFEC_MAX_Q];
118 struct enetfec_priv_tx_q *tx_queues[ENETFEC_MAX_Q];
122 bufdesc *enet_get_nextdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
124 return (bdp >= bd->last) ? bd->base
125 : (struct bufdesc *)(((uintptr_t)bdp) + bd->d_size);
129 fls64(unsigned long word)
131 return (64 - __builtin_clzl(word)) - 1;
135 bufdesc *enet_get_prevdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
137 return (bdp <= bd->base) ? bd->last
138 : (struct bufdesc *)(((uintptr_t)bdp) - bd->d_size);
142 enet_get_bd_index(struct bufdesc *bdp, struct bufdesc_prop *bd)
144 return ((const char *)bdp - (const char *)bd->base) >> bd->d_size_log2;
147 uint16_t enetfec_recv_pkts(void *rxq1, struct rte_mbuf **rx_pkts,
149 uint16_t enetfec_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
152 #endif /*__ENETFEC_ETHDEV_H__*/