1 /* SPDX-License-Identifier: BSD-3-Clause
5 #ifndef __ENETFEC_REGS_H
6 #define __ENETFEC_REGS_H
8 /* Ethernet receive use control and status of buffer descriptor
10 #define RX_BD_TR ((ushort)0x0001) /* Truncated */
11 #define RX_BD_OV ((ushort)0x0002) /* Over-run */
12 #define RX_BD_CR ((ushort)0x0004) /* CRC or Frame error */
13 #define RX_BD_SH ((ushort)0x0008) /* Reserved */
14 #define RX_BD_NO ((ushort)0x0010) /* Rcvd non-octet aligned frame */
15 #define RX_BD_LG ((ushort)0x0020) /* Rcvd frame length violation */
16 #define RX_BD_FIRST ((ushort)0x0400) /* Reserved */
17 #define RX_BD_LAST ((ushort)0x0800) /* last buffer in the frame */
18 #define RX_BD_INT 0x00800000
19 #define RX_BD_ICE 0x00000020
20 #define RX_BD_PCR 0x00000010
23 * 0 The next BD in consecutive location
24 * 1 The next BD in ENETFECn_RDSR.
26 #define RX_BD_WRAP ((ushort)0x2000)
27 #define RX_BD_EMPTY ((ushort)0x8000) /* BD is empty */
28 #define RX_BD_STATS ((ushort)0x013f) /* All buffer descriptor status bits */
30 /* Ethernet receive use control and status of enhanced buffer descriptor */
31 #define BD_ENETFEC_RX_VLAN 0x00000004
33 #define RX_FLAG_CSUM_EN (RX_BD_ICE | RX_BD_PCR)
34 #define RX_FLAG_CSUM_ERR (RX_BD_ICE | RX_BD_PCR)
36 /* Ethernet transmit use control and status of buffer descriptor */
37 #define TX_BD_TC ((ushort)0x0400) /* Transmit CRC */
38 #define TX_BD_LAST ((ushort)0x0800) /* Last in frame */
39 #define TX_BD_READY ((ushort)0x8000) /* Data is ready */
40 #define TX_BD_STATS ((ushort)0x0fff) /* All buffer descriptor status bits */
41 #define TX_BD_WRAP ((ushort)0x2000)
43 /* Ethernet transmit use control and status of enhanced buffer descriptor */
44 #define TX_BD_IINS 0x08000000
45 #define TX_BD_PINS 0x10000000
47 #define ENETFEC_RD_START(X) (((X) == 1) ? ENETFEC_RD_START_1 : \
49 ENETFEC_RD_START_2 : ENETFEC_RD_START_0))
50 #define ENETFEC_TD_START(X) (((X) == 1) ? ENETFEC_TD_START_1 : \
52 ENETFEC_TD_START_2 : ENETFEC_TD_START_0))
53 #define ENETFEC_MRB_SIZE(X) (((X) == 1) ? ENETFEC_MRB_SIZE_1 : \
55 ENETFEC_MRB_SIZE_2 : ENETFEC_MRB_SIZE_0))
57 #define ENETFEC_ETHEREN ((uint)0x00000002)
58 #define ENETFEC_TXC_DLY ((uint)0x00010000)
59 #define ENETFEC_RXC_DLY ((uint)0x00020000)
61 /* ENETFEC MAC is in controller */
62 #define QUIRK_HAS_ENETFEC_MAC (1 << 0)
63 /* GBIT supported in controller */
64 #define QUIRK_GBIT (1 << 3)
65 /* Controller support hardware checksum */
66 #define QUIRK_CSUM (1 << 5)
67 /* Controller support hardware vlan */
68 #define QUIRK_VLAN (1 << 6)
69 /* RACC register supported by controller */
70 #define QUIRK_RACC (1 << 12)
71 /* i.MX8 ENETFEC IP version added the feature to generate the delayed TXC or
72 * RXC. For its implementation, ENETFEC uses synchronized clocks (250MHz) for
73 * generating delay of 2ns.
75 #define QUIRK_SUPPORT_DELAYED_CLKS (1 << 18)
77 #define ENETFEC_EIR 0x004 /* Interrupt event register */
78 #define ENETFEC_EIMR 0x008 /* Interrupt mask register */
79 #define ENETFEC_RDAR_0 0x010 /* Receive descriptor active register ring0 */
80 #define ENETFEC_TDAR_0 0x014 /* Transmit descriptor active register ring0 */
81 #define ENETFEC_ECR 0x024 /* Ethernet control register */
82 #define ENETFEC_MSCR 0x044 /* MII speed control register */
83 #define ENETFEC_MIBC 0x064 /* MIB control and status register */
84 #define ENETFEC_RCR 0x084 /* Receive control register */
85 #define ENETFEC_TCR 0x0c4 /* Transmit Control register */
86 #define ENETFEC_PALR 0x0e4 /* MAC address low 32 bits */
87 #define ENETFEC_PAUR 0x0e8 /* MAC address high 16 bits */
88 #define ENETFEC_OPD 0x0ec /* Opcode/Pause duration register */
89 #define ENETFEC_IAUR 0x118 /* hash table 32 bits high */
90 #define ENETFEC_IALR 0x11c /* hash table 32 bits low */
91 #define ENETFEC_GAUR 0x120 /* grp hash table 32 bits high */
92 #define ENETFEC_GALR 0x124 /* grp hash table 32 bits low */
93 #define ENETFEC_TFWR 0x144 /* transmit FIFO water_mark */
94 #define ENETFEC_RACC 0x1c4 /* Receive Accelerator function configuration*/
95 #define ENETFEC_DMA1CFG 0x1d8 /* DMA class based configuration ring1 */
96 #define ENETFEC_DMA2CFG 0x1dc /* DMA class based Configuration ring2 */
97 #define ENETFEC_RDAR_1 0x1e0 /* Rx descriptor active register ring1 */
98 #define ENETFEC_TDAR_1 0x1e4 /* Tx descriptor active register ring1 */
99 #define ENETFEC_RDAR_2 0x1e8 /* Rx descriptor active register ring2 */
100 #define ENETFEC_TDAR_2 0x1ec /* Tx descriptor active register ring2 */
101 #define ENETFEC_RD_START_1 0x160 /* Receive descriptor ring1 start reg */
102 #define ENETFEC_TD_START_1 0x164 /* Transmit descriptor ring1 start reg */
103 #define ENETFEC_MRB_SIZE_1 0x168 /* Max receive buffer size reg ring1 */
104 #define ENETFEC_RD_START_2 0x16c /* Receive descriptor ring2 start reg */
105 #define ENETFEC_TD_START_2 0x170 /* Transmit descriptor ring2 start reg */
106 #define ENETFEC_MRB_SIZE_2 0x174 /* Max receive buffer size reg ring2 */
107 #define ENETFEC_RD_START_0 0x180 /* Receive descriptor ring0 start reg */
108 #define ENETFEC_TD_START_0 0x184 /* Transmit descriptor ring0 start reg */
109 #define ENETFEC_MRB_SIZE_0 0x188 /* Max receive buffer size reg ring0*/
110 #define ENETFEC_R_FIFO_SFL 0x190 /* Rx FIFO full threshold */
111 #define ENETFEC_R_FIFO_SEM 0x194 /* Rx FIFO empty threshold */
112 #define ENETFEC_R_FIFO_AEM 0x198 /* Rx FIFO almost empty threshold */
113 #define ENETFEC_R_FIFO_AFL 0x19c /* Rx FIFO almost full threshold */
114 #define ENETFEC_FRAME_TRL 0x1b0 /* Frame truncation length */
116 #endif /*__ENETFEC_REGS_H */