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35 #ifndef _VNIC_RESOURCE_H_
36 #define _VNIC_RESOURCE_H_
38 #define VNIC_RES_MAGIC 0x766E6963L /* 'vnic' */
39 #define VNIC_RES_VERSION 0x00000000L
40 #define MGMTVNIC_MAGIC 0x544d474dL /* 'MGMT' */
41 #define MGMTVNIC_VERSION 0x00000000L
43 /* The MAC address assigned to the CFG vNIC is fixed. */
44 #define MGMTVNIC_MAC { 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d }
46 /* vNIC resource types */
48 RES_TYPE_EOL, /* End-of-list */
49 RES_TYPE_WQ, /* Work queues */
50 RES_TYPE_RQ, /* Receive queues */
51 RES_TYPE_CQ, /* Completion queues */
52 RES_TYPE_MEM, /* Window to dev memory */
53 RES_TYPE_NIC_CFG, /* Enet NIC config registers */
54 RES_TYPE_RSS_KEY, /* Enet RSS secret key */
55 RES_TYPE_RSS_CPU, /* Enet RSS indirection table */
56 RES_TYPE_TX_STATS, /* Netblock Tx statistic regs */
57 RES_TYPE_RX_STATS, /* Netblock Rx statistic regs */
58 RES_TYPE_INTR_CTRL, /* Interrupt ctrl table */
59 RES_TYPE_INTR_TABLE, /* MSI/MSI-X Interrupt table */
60 RES_TYPE_INTR_PBA, /* MSI/MSI-X PBA table */
61 RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */
62 RES_TYPE_DEBUG, /* Debug-only info */
63 RES_TYPE_DEV, /* Device-specific region */
64 RES_TYPE_DEVCMD, /* Device command region */
65 RES_TYPE_PASS_THRU_PAGE, /* Pass-thru page */
66 RES_TYPE_SUBVNIC, /* subvnic resource type */
67 RES_TYPE_MQ_WQ, /* MQ Work queues */
68 RES_TYPE_MQ_RQ, /* MQ Receive queues */
69 RES_TYPE_MQ_CQ, /* MQ Completion queues */
70 RES_TYPE_DEPRECATED1, /* Old version of devcmd 2 */
71 RES_TYPE_DEVCMD2, /* Device control region */
72 RES_TYPE_MAX, /* Count of resource types */
75 struct vnic_resource_header {
80 struct mgmt_barmap_hdr {
81 u32 magic; /* magic number */
82 u32 version; /* header format version */
83 u16 lif; /* loopback lif for mgmt frames */
84 u16 pci_slot; /* installed pci slot */
85 char serial[16]; /* card serial number */
88 struct vnic_resource {
96 #endif /* _VNIC_RESOURCE_H_ */