1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
12 #include <rte_memzone.h>
14 /* Work queue control */
16 u64 ring_base; /* 0x00 */
17 u32 ring_size; /* 0x08 */
19 u32 posted_index; /* 0x10 */
21 u32 cq_index; /* 0x18 */
23 u32 enable; /* 0x20 */
25 u32 running; /* 0x28 */
27 u32 fetch_index; /* 0x30 */
29 u32 dca_value; /* 0x38 */
31 u32 error_interrupt_enable; /* 0x40 */
33 u32 error_interrupt_offset; /* 0x48 */
35 u32 error_status; /* 0x50 */
41 struct rte_mempool *pool;
47 uint64_t tx_offload_notsup_mask;
48 struct vnic_dev *vdev;
49 struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
50 struct vnic_dev_ring ring;
51 struct vnic_wq_buf *bufs;
52 unsigned int head_idx;
53 unsigned int tail_idx;
54 unsigned int socket_id;
55 const struct rte_memzone *cqmsg_rz;
56 uint16_t last_completed_index;
59 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
61 /* how many does SW own? */
62 return wq->ring.desc_avail;
65 static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
67 /* how many does HW own? */
68 return wq->ring.desc_count - wq->ring.desc_avail - 1;
71 #define PI_LOG2_CACHE_LINE_SIZE 5
72 #define PI_INDEX_BITS 12
73 #define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
74 #define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
75 #define PI_PREFETCH_LEN_OFF 16
76 #define PI_PREFETCH_ADDR_BITS 43
77 #define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
78 #define PI_PREFETCH_ADDR_OFF 21
80 /** How many cache lines are touched by buffer (addr, len). */
81 static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
84 const unsigned long mask = PI_PREFETCH_LEN_MASK;
85 const unsigned long laddr = (unsigned long)addr;
86 unsigned long lines, equiv_len;
87 /* A. If addr is aligned, our solution is just to round up len to the
90 e.g. addr = 0, len = 48
91 +--------------------+
92 |XXXXXXXXXXXXXXXXXXXX| 32-byte cacheline a
93 +--------------------+
94 |XXXXXXXXXX | cacheline b
95 +--------------------+
97 B. If addr is not aligned, however, we may use an extra
98 cacheline. e.g. addr = 12, len = 22
100 +--------------------+
102 +--------------------+
104 +--------------------+
106 Our solution is to make the problem equivalent to case A
107 above by adding the empty space in the first cacheline to the length:
110 +--------------------+
111 |eeeeeeeXXXXXXXXXXXXX| "e" is empty space, which we add to len
112 +--------------------+
114 +--------------------+
117 equiv_len = len + (laddr & mask);
119 /* Now we can just round up this len to the next 32-byte boundary. */
120 lines = (equiv_len + mask) & (~mask);
122 /* Scale bytes -> cachelines. */
123 return lines >> PI_LOG2_CACHE_LINE_SIZE;
126 static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
129 unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
130 /* Wish we could avoid a branch here. We could have separate
131 * vnic_wq_post() and vinc_wq_post_inline(), the latter
132 * only supporting < 1k (2^5 * 2^5) sends, I suppose. This would
133 * eliminate the if (eop) branch as well.
135 if (num_cache_lines > PI_PREFETCH_LEN_MASK)
137 return (index & PI_INDEX_MASK) |
138 ((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |
139 (((addr >> PI_LOG2_CACHE_LINE_SIZE) &
140 PI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);
143 static inline uint32_t
144 buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
147 if (unlikely(idx == n_descriptors))
152 void vnic_wq_free(struct vnic_wq *wq);
153 int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
154 unsigned int desc_count, unsigned int desc_size);
155 void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
156 unsigned int fetch_index, unsigned int posted_index,
157 unsigned int error_interrupt_enable,
158 unsigned int error_interrupt_offset);
159 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
160 unsigned int error_interrupt_enable,
161 unsigned int error_interrupt_offset);
162 void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
163 unsigned int vnic_wq_error_status(struct vnic_wq *wq);
164 void vnic_wq_enable(struct vnic_wq *wq);
165 int vnic_wq_disable(struct vnic_wq *wq);
166 void vnic_wq_clean(struct vnic_wq *wq,
167 void (*buf_clean)(struct vnic_wq_buf *buf));
168 #endif /* _VNIC_WQ_H_ */