1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
12 #include <rte_memzone.h>
14 /* Work queue control */
16 u64 ring_base; /* 0x00 */
17 u32 ring_size; /* 0x08 */
19 u32 posted_index; /* 0x10 */
21 u32 cq_index; /* 0x18 */
23 u32 enable; /* 0x20 */
25 u32 running; /* 0x28 */
27 u32 fetch_index; /* 0x30 */
29 u32 dca_value; /* 0x38 */
31 u32 error_interrupt_enable; /* 0x40 */
33 u32 error_interrupt_offset; /* 0x48 */
35 u32 error_status; /* 0x50 */
41 struct rte_mempool *pool;
47 struct vnic_dev *vdev;
48 struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
49 struct vnic_dev_ring ring;
50 struct vnic_wq_buf *bufs;
51 unsigned int head_idx;
52 unsigned int tail_idx;
53 unsigned int socket_id;
54 const struct rte_memzone *cqmsg_rz;
55 uint16_t last_completed_index;
58 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
60 /* how many does SW own? */
61 return wq->ring.desc_avail;
64 static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
66 /* how many does HW own? */
67 return wq->ring.desc_count - wq->ring.desc_avail - 1;
70 #define PI_LOG2_CACHE_LINE_SIZE 5
71 #define PI_INDEX_BITS 12
72 #define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
73 #define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
74 #define PI_PREFETCH_LEN_OFF 16
75 #define PI_PREFETCH_ADDR_BITS 43
76 #define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
77 #define PI_PREFETCH_ADDR_OFF 21
79 /** How many cache lines are touched by buffer (addr, len). */
80 static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
83 const unsigned long mask = PI_PREFETCH_LEN_MASK;
84 const unsigned long laddr = (unsigned long)addr;
85 unsigned long lines, equiv_len;
86 /* A. If addr is aligned, our solution is just to round up len to the
89 e.g. addr = 0, len = 48
90 +--------------------+
91 |XXXXXXXXXXXXXXXXXXXX| 32-byte cacheline a
92 +--------------------+
93 |XXXXXXXXXX | cacheline b
94 +--------------------+
96 B. If addr is not aligned, however, we may use an extra
97 cacheline. e.g. addr = 12, len = 22
99 +--------------------+
101 +--------------------+
103 +--------------------+
105 Our solution is to make the problem equivalent to case A
106 above by adding the empty space in the first cacheline to the length:
109 +--------------------+
110 |eeeeeeeXXXXXXXXXXXXX| "e" is empty space, which we add to len
111 +--------------------+
113 +--------------------+
116 equiv_len = len + (laddr & mask);
118 /* Now we can just round up this len to the next 32-byte boundary. */
119 lines = (equiv_len + mask) & (~mask);
121 /* Scale bytes -> cachelines. */
122 return lines >> PI_LOG2_CACHE_LINE_SIZE;
125 static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
128 unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
129 /* Wish we could avoid a branch here. We could have separate
130 * vnic_wq_post() and vinc_wq_post_inline(), the latter
131 * only supporting < 1k (2^5 * 2^5) sends, I suppose. This would
132 * eliminate the if (eop) branch as well.
134 if (num_cache_lines > PI_PREFETCH_LEN_MASK)
136 return (index & PI_INDEX_MASK) |
137 ((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |
138 (((addr >> PI_LOG2_CACHE_LINE_SIZE) &
139 PI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);
142 static inline uint32_t
143 buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
146 if (unlikely(idx == n_descriptors))
151 void vnic_wq_free(struct vnic_wq *wq);
152 int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
153 unsigned int desc_count, unsigned int desc_size);
154 void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
155 unsigned int fetch_index, unsigned int posted_index,
156 unsigned int error_interrupt_enable,
157 unsigned int error_interrupt_offset);
158 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
159 unsigned int error_interrupt_enable,
160 unsigned int error_interrupt_offset);
161 void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
162 unsigned int vnic_wq_error_status(struct vnic_wq *wq);
163 void vnic_wq_enable(struct vnic_wq *wq);
164 int vnic_wq_disable(struct vnic_wq *wq);
165 void vnic_wq_clean(struct vnic_wq *wq,
166 void (*buf_clean)(struct vnic_wq_buf *buf));
167 #endif /* _VNIC_WQ_H_ */