1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
12 #include <rte_memzone.h>
14 /* Work queue control */
16 u64 ring_base; /* 0x00 */
17 u32 ring_size; /* 0x08 */
19 u32 posted_index; /* 0x10 */
21 u32 cq_index; /* 0x18 */
23 u32 enable; /* 0x20 */
25 u32 running; /* 0x28 */
27 u32 fetch_index; /* 0x30 */
29 u32 dca_value; /* 0x38 */
31 u32 error_interrupt_enable; /* 0x40 */
33 u32 error_interrupt_offset; /* 0x48 */
35 u32 error_status; /* 0x50 */
41 uint64_t tx_offload_notsup_mask;
42 struct vnic_dev *vdev;
43 struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
44 struct vnic_dev_ring ring;
45 struct rte_mbuf **bufs;
46 unsigned int head_idx;
47 unsigned int tail_idx;
48 unsigned int socket_id;
49 const struct rte_memzone *cqmsg_rz;
50 uint16_t last_completed_index;
53 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
55 /* how many does SW own? */
56 return wq->ring.desc_avail;
59 static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
61 /* how many does HW own? */
62 return wq->ring.desc_count - wq->ring.desc_avail - 1;
65 #define PI_LOG2_CACHE_LINE_SIZE 5
66 #define PI_INDEX_BITS 12
67 #define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
68 #define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
69 #define PI_PREFETCH_LEN_OFF 16
70 #define PI_PREFETCH_ADDR_BITS 43
71 #define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
72 #define PI_PREFETCH_ADDR_OFF 21
74 /** How many cache lines are touched by buffer (addr, len). */
75 static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
78 const unsigned long mask = PI_PREFETCH_LEN_MASK;
79 const unsigned long laddr = (unsigned long)addr;
80 unsigned long lines, equiv_len;
81 /* A. If addr is aligned, our solution is just to round up len to the
84 e.g. addr = 0, len = 48
85 +--------------------+
86 |XXXXXXXXXXXXXXXXXXXX| 32-byte cacheline a
87 +--------------------+
88 |XXXXXXXXXX | cacheline b
89 +--------------------+
91 B. If addr is not aligned, however, we may use an extra
92 cacheline. e.g. addr = 12, len = 22
94 +--------------------+
96 +--------------------+
98 +--------------------+
100 Our solution is to make the problem equivalent to case A
101 above by adding the empty space in the first cacheline to the length:
104 +--------------------+
105 |eeeeeeeXXXXXXXXXXXXX| "e" is empty space, which we add to len
106 +--------------------+
108 +--------------------+
111 equiv_len = len + (laddr & mask);
113 /* Now we can just round up this len to the next 32-byte boundary. */
114 lines = (equiv_len + mask) & (~mask);
116 /* Scale bytes -> cachelines. */
117 return lines >> PI_LOG2_CACHE_LINE_SIZE;
120 static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
123 unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
124 /* Wish we could avoid a branch here. We could have separate
125 * vnic_wq_post() and vinc_wq_post_inline(), the latter
126 * only supporting < 1k (2^5 * 2^5) sends, I suppose. This would
127 * eliminate the if (eop) branch as well.
129 if (num_cache_lines > PI_PREFETCH_LEN_MASK)
131 return (index & PI_INDEX_MASK) |
132 ((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |
133 (((addr >> PI_LOG2_CACHE_LINE_SIZE) &
134 PI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);
137 static inline uint32_t
138 buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
141 if (unlikely(idx == n_descriptors))
146 void vnic_wq_free(struct vnic_wq *wq);
147 int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
148 unsigned int desc_count, unsigned int desc_size);
149 void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
150 unsigned int fetch_index, unsigned int posted_index,
151 unsigned int error_interrupt_enable,
152 unsigned int error_interrupt_offset);
153 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
154 unsigned int error_interrupt_enable,
155 unsigned int error_interrupt_offset);
156 void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
157 unsigned int vnic_wq_error_status(struct vnic_wq *wq);
158 void vnic_wq_enable(struct vnic_wq *wq);
159 int vnic_wq_disable(struct vnic_wq *wq);
160 void vnic_wq_clean(struct vnic_wq *wq,
161 void (*buf_clean)(struct rte_mbuf **buf));
162 #endif /* _VNIC_WQ_H_ */