2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
5 * Copyright (c) 2014, Cisco Systems, Inc.
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42 /* Work queue control */
44 u64 ring_base; /* 0x00 */
45 u32 ring_size; /* 0x08 */
47 u32 posted_index; /* 0x10 */
49 u32 cq_index; /* 0x18 */
51 u32 enable; /* 0x20 */
53 u32 running; /* 0x28 */
55 u32 fetch_index; /* 0x30 */
57 u32 dca_value; /* 0x38 */
59 u32 error_interrupt_enable; /* 0x40 */
61 u32 error_interrupt_offset; /* 0x48 */
63 u32 error_status; /* 0x50 */
74 struct vnic_dev *vdev;
75 struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
76 struct vnic_dev_ring ring;
77 struct vnic_wq_buf *bufs;
78 unsigned int head_idx;
79 unsigned int tail_idx;
80 unsigned int pkts_outstanding;
81 unsigned int socket_id;
84 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
86 /* how many does SW own? */
87 return wq->ring.desc_avail;
90 static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
92 /* how many does HW own? */
93 return wq->ring.desc_count - wq->ring.desc_avail - 1;
96 #define PI_LOG2_CACHE_LINE_SIZE 5
97 #define PI_INDEX_BITS 12
98 #define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
99 #define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
100 #define PI_PREFETCH_LEN_OFF 16
101 #define PI_PREFETCH_ADDR_BITS 43
102 #define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
103 #define PI_PREFETCH_ADDR_OFF 21
105 /** How many cache lines are touched by buffer (addr, len). */
106 static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
109 const unsigned long mask = PI_PREFETCH_LEN_MASK;
110 const unsigned long laddr = (unsigned long)addr;
111 unsigned long lines, equiv_len;
112 /* A. If addr is aligned, our solution is just to round up len to the
115 e.g. addr = 0, len = 48
116 +--------------------+
117 |XXXXXXXXXXXXXXXXXXXX| 32-byte cacheline a
118 +--------------------+
119 |XXXXXXXXXX | cacheline b
120 +--------------------+
122 B. If addr is not aligned, however, we may use an extra
123 cacheline. e.g. addr = 12, len = 22
125 +--------------------+
127 +--------------------+
129 +--------------------+
131 Our solution is to make the problem equivalent to case A
132 above by adding the empty space in the first cacheline to the length:
135 +--------------------+
136 |eeeeeeeXXXXXXXXXXXXX| "e" is empty space, which we add to len
137 +--------------------+
139 +--------------------+
142 equiv_len = len + (laddr & mask);
144 /* Now we can just round up this len to the next 32-byte boundary. */
145 lines = (equiv_len + mask) & (~mask);
147 /* Scale bytes -> cachelines. */
148 return lines >> PI_LOG2_CACHE_LINE_SIZE;
151 static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
154 unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
155 /* Wish we could avoid a branch here. We could have separate
156 * vnic_wq_post() and vinc_wq_post_inline(), the latter
157 * only supporting < 1k (2^5 * 2^5) sends, I suppose. This would
158 * eliminate the if (eop) branch as well.
160 if (num_cache_lines > PI_PREFETCH_LEN_MASK)
162 return (index & PI_INDEX_MASK) |
163 ((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |
164 (((addr >> PI_LOG2_CACHE_LINE_SIZE) &
165 PI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);
168 static inline uint32_t
169 buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
172 if (unlikely(idx == n_descriptors))
177 static inline void vnic_wq_service(struct vnic_wq *wq,
178 struct cq_desc *cq_desc, u16 completed_index,
179 void (*buf_service)(struct vnic_wq *wq,
180 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
183 struct vnic_wq_buf *buf;
184 unsigned int to_clean = wq->tail_idx;
186 buf = &wq->bufs[to_clean];
189 (*buf_service)(wq, cq_desc, buf, opaque);
191 wq->ring.desc_avail++;
194 to_clean = buf_idx_incr(wq->ring.desc_count, to_clean);
196 if (to_clean == completed_index)
199 buf = &wq->bufs[to_clean];
201 wq->tail_idx = to_clean;
204 void vnic_wq_free(struct vnic_wq *wq);
205 int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
206 unsigned int desc_count, unsigned int desc_size);
207 void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
208 unsigned int fetch_index, unsigned int posted_index,
209 unsigned int error_interrupt_enable,
210 unsigned int error_interrupt_offset);
211 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
212 unsigned int error_interrupt_enable,
213 unsigned int error_interrupt_offset);
214 void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
215 unsigned int vnic_wq_error_status(struct vnic_wq *wq);
216 void vnic_wq_enable(struct vnic_wq *wq);
217 int vnic_wq_disable(struct vnic_wq *wq);
218 void vnic_wq_clean(struct vnic_wq *wq,
219 void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
220 int vnic_wq_mem_size(struct vnic_wq *wq, unsigned int desc_count,
221 unsigned int desc_size);
223 #endif /* _VNIC_WQ_H_ */