drivers/net/enic/enic_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  */
   5
   6 #include <stdio.h>
   7 #include <stdint.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_pci.h>
  11 #include <rte_bus_pci.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_ethdev_pci.h>
  14 #include <rte_kvargs.h>
  15 #include <rte_string_fns.h>
  16
  17 #include "vnic_intr.h"
  18 #include "vnic_cq.h"
  19 #include "vnic_wq.h"
  20 #include "vnic_rq.h"
  21 #include "vnic_enet.h"
  22 #include "enic.h"
  23
  24 int enic_pmd_logtype;
  25
  26 /*
  27  * The set of PCI devices this driver supports
  28  */
  29 #define CISCO_PCI_VENDOR_ID 0x1137
  30 static const struct rte_pci_id pci_id_enic_map[] = {
  31         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)},
  32         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)},
  33         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)},
  34         {.vendor_id = 0, /* sentinel */},
  35 };
  36
  37 /* Supported link speeds of production VIC models */
  38 static const struct vic_speed_capa {
  39         uint16_t sub_devid;
  40         uint32_t capa;
  41 } vic_speed_capa_map[] = {
  42         { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */
  43         { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */
  44         { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */
  45         { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */
  46         { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */
  47         { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */
  48         { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */
  49         { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */
  50         { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */
  51         { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */
  52         { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */
  53         { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */
  54         { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */
  55         { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */
  56         { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  57                   ETH_LINK_SPEED_40G }, /* 1440 Mezz */
  58         { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  59                   ETH_LINK_SPEED_40G }, /* 1480 MLOM */
  60         { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */
  61         { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */
  62         { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */
  63         { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */
  64         { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */
  65         { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */
  66         { 0, 0 }, /* End marker */
  67 };
  68
  69 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
  70 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx"
  71 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt"
  72 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite"
  73
  74 RTE_INIT(enicpmd_init_log)
  75 {
  76         enic_pmd_logtype = rte_log_register("pmd.net.enic");
  77         if (enic_pmd_logtype >= 0)
  78                 rte_log_set_level(enic_pmd_logtype, RTE_LOG_INFO);
  79 }
  80
  81 static int
  82 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev,
  83                         enum rte_filter_op filter_op, void *arg)
  84 {
  85         struct enic *enic = pmd_priv(eth_dev);
  86         int ret = 0;
  87
  88         ENICPMD_FUNC_TRACE();
  89         if (filter_op == RTE_ETH_FILTER_NOP)
  90                 return 0;
  91
  92         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
  93                 return -EINVAL;
  94
  95         switch (filter_op) {
  96         case RTE_ETH_FILTER_ADD:
  97         case RTE_ETH_FILTER_UPDATE:
  98                 ret = enic_fdir_add_fltr(enic,
  99                         (struct rte_eth_fdir_filter *)arg);
 100                 break;
 101
 102         case RTE_ETH_FILTER_DELETE:
 103                 ret = enic_fdir_del_fltr(enic,
 104                         (struct rte_eth_fdir_filter *)arg);
 105                 break;
 106
 107         case RTE_ETH_FILTER_STATS:
 108                 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg);
 109                 break;
 110
 111         case RTE_ETH_FILTER_FLUSH:
 112                 dev_warning(enic, "unsupported operation %u", filter_op);
 113                 ret = -ENOTSUP;
 114                 break;
 115         case RTE_ETH_FILTER_INFO:
 116                 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg);
 117                 break;
 118         default:
 119                 dev_err(enic, "unknown operation %u", filter_op);
 120                 ret = -EINVAL;
 121                 break;
 122         }
 123         return ret;
 124 }
 125
 126 static int
 127 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev,
 128                      enum rte_filter_type filter_type,
 129                      enum rte_filter_op filter_op,
 130                      void *arg)
 131 {
 132         struct enic *enic = pmd_priv(dev);
 133         int ret = 0;
 134
 135         ENICPMD_FUNC_TRACE();
 136
 137         /*
 138          * Currently, when Geneve with options offload is enabled, host
 139          * cannot insert match-action rules.
 140          */
 141         if (enic->geneve_opt_enabled)
 142                 return -ENOTSUP;
 143         switch (filter_type) {
 144         case RTE_ETH_FILTER_GENERIC:
 145                 if (filter_op != RTE_ETH_FILTER_GET)
 146                         return -EINVAL;
 147                 if (enic->flow_filter_mode == FILTER_FLOWMAN)
 148                         *(const void **)arg = &enic_fm_flow_ops;
 149                 else
 150                         *(const void **)arg = &enic_flow_ops;
 151                 break;
 152         case RTE_ETH_FILTER_FDIR:
 153                 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg);
 154                 break;
 155         default:
 156                 dev_warning(enic, "Filter type (%d) not supported",
 157                         filter_type);
 158                 ret = -EINVAL;
 159                 break;
 160         }
 161
 162         return ret;
 163 }
 164
 165 static void enicpmd_dev_tx_queue_release(void *txq)
 166 {
 167         ENICPMD_FUNC_TRACE();
 168
 169         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 170                 return;
 171
 172         enic_free_wq(txq);
 173 }
 174
 175 static int enicpmd_dev_setup_intr(struct enic *enic)
 176 {
 177         int ret;
 178         unsigned int index;
 179
 180         ENICPMD_FUNC_TRACE();
 181
 182         /* Are we done with the init of all the queues? */
 183         for (index = 0; index < enic->cq_count; index++) {
 184                 if (!enic->cq[index].ctrl)
 185                         break;
 186         }
 187         if (enic->cq_count != index)
 188                 return 0;
 189         for (index = 0; index < enic->wq_count; index++) {
 190                 if (!enic->wq[index].ctrl)
 191                         break;
 192         }
 193         if (enic->wq_count != index)
 194                 return 0;
 195         /* check start of packet (SOP) RQs only in case scatter is disabled. */
 196         for (index = 0; index < enic->rq_count; index++) {
 197                 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl)
 198                         break;
 199         }
 200         if (enic->rq_count != index)
 201                 return 0;
 202
 203         ret = enic_alloc_intr_resources(enic);
 204         if (ret) {
 205                 dev_err(enic, "alloc intr failed\n");
 206                 return ret;
 207         }
 208         enic_init_vnic_resources(enic);
 209
 210         ret = enic_setup_finish(enic);
 211         if (ret)
 212                 dev_err(enic, "setup could not be finished\n");
 213
 214         return ret;
 215 }
 216
 217 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 218         uint16_t queue_idx,
 219         uint16_t nb_desc,
 220         unsigned int socket_id,
 221         const struct rte_eth_txconf *tx_conf)
 222 {
 223         int ret;
 224         struct enic *enic = pmd_priv(eth_dev);
 225         struct vnic_wq *wq;
 226
 227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 228                 return -E_RTE_SECONDARY;
 229
 230         ENICPMD_FUNC_TRACE();
 231         RTE_ASSERT(queue_idx < enic->conf_wq_count);
 232         wq = &enic->wq[queue_idx];
 233         wq->offloads = tx_conf->offloads |
 234                 eth_dev->data->dev_conf.txmode.offloads;
 235         eth_dev->data->tx_queues[queue_idx] = (void *)wq;
 236
 237         ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc);
 238         if (ret) {
 239                 dev_err(enic, "error in allocating wq\n");
 240                 return ret;
 241         }
 242
 243         return enicpmd_dev_setup_intr(enic);
 244 }
 245
 246 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
 247         uint16_t queue_idx)
 248 {
 249         struct enic *enic = pmd_priv(eth_dev);
 250
 251         ENICPMD_FUNC_TRACE();
 252
 253         enic_start_wq(enic, queue_idx);
 254
 255         return 0;
 256 }
 257
 258 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
 259         uint16_t queue_idx)
 260 {
 261         int ret;
 262         struct enic *enic = pmd_priv(eth_dev);
 263
 264         ENICPMD_FUNC_TRACE();
 265
 266         ret = enic_stop_wq(enic, queue_idx);
 267         if (ret)
 268                 dev_err(enic, "error in stopping wq %d\n", queue_idx);
 269
 270         return ret;
 271 }
 272
 273 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
 274         uint16_t queue_idx)
 275 {
 276         struct enic *enic = pmd_priv(eth_dev);
 277
 278         ENICPMD_FUNC_TRACE();
 279
 280         enic_start_rq(enic, queue_idx);
 281
 282         return 0;
 283 }
 284
 285 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
 286         uint16_t queue_idx)
 287 {
 288         int ret;
 289         struct enic *enic = pmd_priv(eth_dev);
 290
 291         ENICPMD_FUNC_TRACE();
 292
 293         ret = enic_stop_rq(enic, queue_idx);
 294         if (ret)
 295                 dev_err(enic, "error in stopping rq %d\n", queue_idx);
 296
 297         return ret;
 298 }
 299
 300 static void enicpmd_dev_rx_queue_release(void *rxq)
 301 {
 302         ENICPMD_FUNC_TRACE();
 303
 304         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 305                 return;
 306
 307         enic_free_rq(rxq);
 308 }
 309
 310 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev,
 311                                            uint16_t rx_queue_id)
 312 {
 313         struct enic *enic = pmd_priv(dev);
 314         uint32_t queue_count = 0;
 315         struct vnic_cq *cq;
 316         uint32_t cq_tail;
 317         uint16_t cq_idx;
 318         int rq_num;
 319
 320         rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 321         cq = &enic->cq[enic_cq_rq(enic, rq_num)];
 322         cq_idx = cq->to_clean;
 323
 324         cq_tail = ioread32(&cq->ctrl->cq_tail);
 325
 326         if (cq_tail < cq_idx)
 327                 cq_tail += cq->ring.desc_count;
 328
 329         queue_count = cq_tail - cq_idx;
 330
 331         return queue_count;
 332 }
 333
 334 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 335         uint16_t queue_idx,
 336         uint16_t nb_desc,
 337         unsigned int socket_id,
 338         const struct rte_eth_rxconf *rx_conf,
 339         struct rte_mempool *mp)
 340 {
 341         int ret;
 342         struct enic *enic = pmd_priv(eth_dev);
 343
 344         ENICPMD_FUNC_TRACE();
 345
 346         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 347                 return -E_RTE_SECONDARY;
 348         RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count);
 349         eth_dev->data->rx_queues[queue_idx] =
 350                 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)];
 351
 352         ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc,
 353                             rx_conf->rx_free_thresh);
 354         if (ret) {
 355                 dev_err(enic, "error in allocating rq\n");
 356                 return ret;
 357         }
 358
 359         return enicpmd_dev_setup_intr(enic);
 360 }
 361
 362 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 363 {
 364         struct enic *enic = pmd_priv(eth_dev);
 365         uint64_t offloads;
 366
 367         ENICPMD_FUNC_TRACE();
 368
 369         offloads = eth_dev->data->dev_conf.rxmode.offloads;
 370         if (mask & ETH_VLAN_STRIP_MASK) {
 371                 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 372                         enic->ig_vlan_strip_en = 1;
 373                 else
 374                         enic->ig_vlan_strip_en = 0;
 375         }
 376
 377         if ((mask & ETH_VLAN_FILTER_MASK) &&
 378             (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
 379                 dev_warning(enic,
 380                         "Configuration of VLAN filter is not supported\n");
 381         }
 382
 383         if ((mask & ETH_VLAN_EXTEND_MASK) &&
 384             (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) {
 385                 dev_warning(enic,
 386                         "Configuration of extended VLAN is not supported\n");
 387         }
 388
 389         return enic_set_vlan_strip(enic);
 390 }
 391
 392 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev)
 393 {
 394         int ret;
 395         int mask;
 396         struct enic *enic = pmd_priv(eth_dev);
 397
 398         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 399                 return -E_RTE_SECONDARY;
 400
 401         ENICPMD_FUNC_TRACE();
 402         ret = enic_set_vnic_res(enic);
 403         if (ret) {
 404                 dev_err(enic, "Set vNIC resource num  failed, aborting\n");
 405                 return ret;
 406         }
 407
 408         enic->mc_count = 0;
 409         enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads &
 410                                   DEV_RX_OFFLOAD_CHECKSUM);
 411         /* All vlan offload masks to apply the current settings */
 412         mask = ETH_VLAN_STRIP_MASK |
 413                 ETH_VLAN_FILTER_MASK |
 414                 ETH_VLAN_EXTEND_MASK;
 415         ret = enicpmd_vlan_offload_set(eth_dev, mask);
 416         if (ret) {
 417                 dev_err(enic, "Failed to configure VLAN offloads\n");
 418                 return ret;
 419         }
 420         /*
 421          * Initialize RSS with the default reta and key. If the user key is
 422          * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the
 423          * default key.
 424          */
 425         return enic_init_rss_nic_cfg(enic);
 426 }
 427
 428 /* Start the device.
 429  * It returns 0 on success.
 430  */
 431 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev)
 432 {
 433         struct enic *enic = pmd_priv(eth_dev);
 434
 435         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 436                 return -E_RTE_SECONDARY;
 437
 438         ENICPMD_FUNC_TRACE();
 439         return enic_enable(enic);
 440 }
 441
 442 /*
 443  * Stop device: disable rx and tx functions to allow for reconfiguring.
 444  */
 445 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev)
 446 {
 447         struct rte_eth_link link;
 448         struct enic *enic = pmd_priv(eth_dev);
 449
 450         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 451                 return;
 452
 453         ENICPMD_FUNC_TRACE();
 454         enic_disable(enic);
 455
 456         memset(&link, 0, sizeof(link));
 457         rte_eth_linkstatus_set(eth_dev, &link);
 458 }
 459
 460 /*
 461  * Stop device.
 462  */
 463 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev)
 464 {
 465         struct enic *enic = pmd_priv(eth_dev);
 466
 467         ENICPMD_FUNC_TRACE();
 468         enic_remove(enic);
 469 }
 470
 471 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,
 472         __rte_unused int wait_to_complete)
 473 {
 474         ENICPMD_FUNC_TRACE();
 475         return enic_link_update(eth_dev);
 476 }
 477
 478 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,
 479         struct rte_eth_stats *stats)
 480 {
 481         struct enic *enic = pmd_priv(eth_dev);
 482
 483         ENICPMD_FUNC_TRACE();
 484         return enic_dev_stats_get(enic, stats);
 485 }
 486
 487 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)
 488 {
 489         struct enic *enic = pmd_priv(eth_dev);
 490
 491         ENICPMD_FUNC_TRACE();
 492         return enic_dev_stats_clear(enic);
 493 }
 494
 495 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev)
 496 {
 497         const struct vic_speed_capa *m;
 498         struct rte_pci_device *pdev;
 499         uint16_t id;
 500
 501         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
 502         id = pdev->id.subsystem_device_id;
 503         for (m = vic_speed_capa_map; m->sub_devid != 0; m++) {
 504                 if (m->sub_devid == id)
 505                         return m->capa;
 506         }
 507         /* 1300 and later models are at least 40G */
 508         if (id >= 0x0100)
 509                 return ETH_LINK_SPEED_40G;
 510         return ETH_LINK_SPEED_10G;
 511 }
 512
 513 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
 514         struct rte_eth_dev_info *device_info)
 515 {
 516         struct enic *enic = pmd_priv(eth_dev);
 517
 518         ENICPMD_FUNC_TRACE();
 519         /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */
 520         device_info->max_rx_queues = enic->conf_rq_count / 2;
 521         device_info->max_tx_queues = enic->conf_wq_count;
 522         device_info->min_rx_bufsize = ENIC_MIN_MTU;
 523         /* "Max" mtu is not a typo. HW receives packet sizes up to the
 524          * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is
 525          * a hint to the driver to size receive buffers accordingly so that
 526          * larger-than-vnic-mtu packets get truncated.. For DPDK, we let
 527          * the user decide the buffer size via rxmode.max_rx_pkt_len, basically
 528          * ignoring vNIC mtu.
 529          */
 530         device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu);
 531         device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS;
 532         device_info->min_mtu = ENIC_MIN_MTU;
 533         device_info->max_mtu = enic->max_mtu;
 534         device_info->rx_offload_capa = enic->rx_offload_capa;
 535         device_info->tx_offload_capa = enic->tx_offload_capa;
 536         device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa;
 537         device_info->default_rxconf = (struct rte_eth_rxconf) {
 538                 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH
 539         };
 540         device_info->reta_size = enic->reta_size;
 541         device_info->hash_key_size = enic->hash_key_size;
 542         device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads;
 543         device_info->rx_desc_lim = (struct rte_eth_desc_lim) {
 544                 .nb_max = enic->config.rq_desc_count,
 545                 .nb_min = ENIC_MIN_RQ_DESCS,
 546                 .nb_align = ENIC_ALIGN_DESCS,
 547         };
 548         device_info->tx_desc_lim = (struct rte_eth_desc_lim) {
 549                 .nb_max = enic->config.wq_desc_count,
 550                 .nb_min = ENIC_MIN_WQ_DESCS,
 551                 .nb_align = ENIC_ALIGN_DESCS,
 552                 .nb_seg_max = ENIC_TX_XMIT_MAX,
 553                 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC,
 554         };
 555         device_info->default_rxportconf = (struct rte_eth_dev_portconf) {
 556                 .burst_size = ENIC_DEFAULT_RX_BURST,
 557                 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max,
 558                         ENIC_DEFAULT_RX_RING_SIZE),
 559                 .nb_queues = ENIC_DEFAULT_RX_RINGS,
 560         };
 561         device_info->default_txportconf = (struct rte_eth_dev_portconf) {
 562                 .burst_size = ENIC_DEFAULT_TX_BURST,
 563                 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max,
 564                         ENIC_DEFAULT_TX_RING_SIZE),
 565                 .nb_queues = ENIC_DEFAULT_TX_RINGS,
 566         };
 567         device_info->speed_capa = speed_capa_from_pci_id(eth_dev);
 568
 569         return 0;
 570 }
 571
 572 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 573 {
 574         static const uint32_t ptypes[] = {
 575                 RTE_PTYPE_L2_ETHER,
 576                 RTE_PTYPE_L2_ETHER_VLAN,
 577                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 578                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 579                 RTE_PTYPE_L4_TCP,
 580                 RTE_PTYPE_L4_UDP,
 581                 RTE_PTYPE_L4_FRAG,
 582                 RTE_PTYPE_L4_NONFRAG,
 583                 RTE_PTYPE_UNKNOWN
 584         };
 585         static const uint32_t ptypes_overlay[] = {
 586                 RTE_PTYPE_L2_ETHER,
 587                 RTE_PTYPE_L2_ETHER_VLAN,
 588                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 589                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 590                 RTE_PTYPE_L4_TCP,
 591                 RTE_PTYPE_L4_UDP,
 592                 RTE_PTYPE_L4_FRAG,
 593                 RTE_PTYPE_L4_NONFRAG,
 594                 RTE_PTYPE_TUNNEL_GRENAT,
 595                 RTE_PTYPE_INNER_L2_ETHER,
 596                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 597                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 598                 RTE_PTYPE_INNER_L4_TCP,
 599                 RTE_PTYPE_INNER_L4_UDP,
 600                 RTE_PTYPE_INNER_L4_FRAG,
 601                 RTE_PTYPE_INNER_L4_NONFRAG,
 602                 RTE_PTYPE_UNKNOWN
 603         };
 604
 605         if (dev->rx_pkt_burst != enic_dummy_recv_pkts &&
 606             dev->rx_pkt_burst != NULL) {
 607                 struct enic *enic = pmd_priv(dev);
 608                 if (enic->overlay_offload)
 609                         return ptypes_overlay;
 610                 else
 611                         return ptypes;
 612         }
 613         return NULL;
 614 }
 615
 616 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 617 {
 618         struct enic *enic = pmd_priv(eth_dev);
 619         int ret;
 620
 621         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 622                 return -E_RTE_SECONDARY;
 623
 624         ENICPMD_FUNC_TRACE();
 625
 626         enic->promisc = 1;
 627         ret = enic_add_packet_filter(enic);
 628         if (ret != 0)
 629                 enic->promisc = 0;
 630
 631         return ret;
 632 }
 633
 634 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 635 {
 636         struct enic *enic = pmd_priv(eth_dev);
 637         int ret;
 638
 639         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 640                 return -E_RTE_SECONDARY;
 641
 642         ENICPMD_FUNC_TRACE();
 643         enic->promisc = 0;
 644         ret = enic_add_packet_filter(enic);
 645         if (ret != 0)
 646                 enic->promisc = 1;
 647
 648         return ret;
 649 }
 650
 651 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 652 {
 653         struct enic *enic = pmd_priv(eth_dev);
 654         int ret;
 655
 656         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 657                 return -E_RTE_SECONDARY;
 658
 659         ENICPMD_FUNC_TRACE();
 660         enic->allmulti = 1;
 661         ret = enic_add_packet_filter(enic);
 662         if (ret != 0)
 663                 enic->allmulti = 0;
 664
 665         return ret;
 666 }
 667
 668 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 669 {
 670         struct enic *enic = pmd_priv(eth_dev);
 671         int ret;
 672
 673         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 674                 return -E_RTE_SECONDARY;
 675
 676         ENICPMD_FUNC_TRACE();
 677         enic->allmulti = 0;
 678         ret = enic_add_packet_filter(enic);
 679         if (ret != 0)
 680                 enic->allmulti = 1;
 681
 682         return ret;
 683 }
 684
 685 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev,
 686         struct rte_ether_addr *mac_addr,
 687         __rte_unused uint32_t index, __rte_unused uint32_t pool)
 688 {
 689         struct enic *enic = pmd_priv(eth_dev);
 690
 691         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 692                 return -E_RTE_SECONDARY;
 693
 694         ENICPMD_FUNC_TRACE();
 695         return enic_set_mac_address(enic, mac_addr->addr_bytes);
 696 }
 697
 698 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index)
 699 {
 700         struct enic *enic = pmd_priv(eth_dev);
 701
 702         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 703                 return;
 704
 705         ENICPMD_FUNC_TRACE();
 706         if (enic_del_mac_address(enic, index))
 707                 dev_err(enic, "del mac addr failed\n");
 708 }
 709
 710 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev,
 711                                 struct rte_ether_addr *addr)
 712 {
 713         struct enic *enic = pmd_priv(eth_dev);
 714         int ret;
 715
 716         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 717                 return -E_RTE_SECONDARY;
 718
 719         ENICPMD_FUNC_TRACE();
 720         ret = enic_del_mac_address(enic, 0);
 721         if (ret)
 722                 return ret;
 723         return enic_set_mac_address(enic, addr->addr_bytes);
 724 }
 725
 726 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add)
 727 {
 728         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 729
 730         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 731         ENICPMD_LOG(DEBUG, " %s address %s\n",
 732                      add ? "add" : "remove", mac_str);
 733 }
 734
 735 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev,
 736                                     struct rte_ether_addr *mc_addr_set,
 737                                     uint32_t nb_mc_addr)
 738 {
 739         struct enic *enic = pmd_priv(eth_dev);
 740         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 741         struct rte_ether_addr *addr;
 742         uint32_t i, j;
 743         int ret;
 744
 745         ENICPMD_FUNC_TRACE();
 746
 747         /* Validate the given addresses first */
 748         for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) {
 749                 addr = &mc_addr_set[i];
 750                 if (!rte_is_multicast_ether_addr(addr) ||
 751                     rte_is_broadcast_ether_addr(addr)) {
 752                         rte_ether_format_addr(mac_str,
 753                                         RTE_ETHER_ADDR_FMT_SIZE, addr);
 754                         ENICPMD_LOG(ERR, " invalid multicast address %s\n",
 755                                      mac_str);
 756                         return -EINVAL;
 757                 }
 758         }
 759
 760         /* Flush all if requested */
 761         if (nb_mc_addr == 0 || mc_addr_set == NULL) {
 762                 ENICPMD_LOG(DEBUG, " flush multicast addresses\n");
 763                 for (i = 0; i < enic->mc_count; i++) {
 764                         addr = &enic->mc_addrs[i];
 765                         debug_log_add_del_addr(addr, false);
 766                         ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 767                         if (ret)
 768                                 return ret;
 769                 }
 770                 enic->mc_count = 0;
 771                 return 0;
 772         }
 773
 774         if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) {
 775                 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n",
 776                              ENIC_MULTICAST_PERFECT_FILTERS);
 777                 return -ENOSPC;
 778         }
 779         /*
 780          * devcmd is slow, so apply the difference instead of flushing and
 781          * adding everything.
 782          * 1. Delete addresses on the NIC but not on the host
 783          */
 784         for (i = 0; i < enic->mc_count; i++) {
 785                 addr = &enic->mc_addrs[i];
 786                 for (j = 0; j < nb_mc_addr; j++) {
 787                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j]))
 788                                 break;
 789                 }
 790                 if (j < nb_mc_addr)
 791                         continue;
 792                 debug_log_add_del_addr(addr, false);
 793                 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 794                 if (ret)
 795                         return ret;
 796         }
 797         /* 2. Add addresses on the host but not on the NIC */
 798         for (i = 0; i < nb_mc_addr; i++) {
 799                 addr = &mc_addr_set[i];
 800                 for (j = 0; j < enic->mc_count; j++) {
 801                         if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j]))
 802                                 break;
 803                 }
 804                 if (j < enic->mc_count)
 805                         continue;
 806                 debug_log_add_del_addr(addr, true);
 807                 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes);
 808                 if (ret)
 809                         return ret;
 810         }
 811         /* Keep a copy so we can flush/apply later on.. */
 812         memcpy(enic->mc_addrs, mc_addr_set,
 813                nb_mc_addr * sizeof(struct rte_ether_addr));
 814         enic->mc_count = nb_mc_addr;
 815         return 0;
 816 }
 817
 818 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 819 {
 820         struct enic *enic = pmd_priv(eth_dev);
 821
 822         ENICPMD_FUNC_TRACE();
 823         return enic_set_mtu(enic, mtu);
 824 }
 825
 826 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev,
 827                                       struct rte_eth_rss_reta_entry64
 828                                       *reta_conf,
 829                                       uint16_t reta_size)
 830 {
 831         struct enic *enic = pmd_priv(dev);
 832         uint16_t i, idx, shift;
 833
 834         ENICPMD_FUNC_TRACE();
 835         if (reta_size != ENIC_RSS_RETA_SIZE) {
 836                 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n",
 837                         reta_size, ENIC_RSS_RETA_SIZE);
 838                 return -EINVAL;
 839         }
 840
 841         for (i = 0; i < reta_size; i++) {
 842                 idx = i / RTE_RETA_GROUP_SIZE;
 843                 shift = i % RTE_RETA_GROUP_SIZE;
 844                 if (reta_conf[idx].mask & (1ULL << shift))
 845                         reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx(
 846                                 enic->rss_cpu.cpu[i / 4].b[i % 4]);
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev,
 853                                        struct rte_eth_rss_reta_entry64
 854                                        *reta_conf,
 855                                        uint16_t reta_size)
 856 {
 857         struct enic *enic = pmd_priv(dev);
 858         union vnic_rss_cpu rss_cpu;
 859         uint16_t i, idx, shift;
 860
 861         ENICPMD_FUNC_TRACE();
 862         if (reta_size != ENIC_RSS_RETA_SIZE) {
 863                 dev_err(enic, "reta_update: wrong reta_size. given=%u"
 864                         " expected=%u\n",
 865                         reta_size, ENIC_RSS_RETA_SIZE);
 866                 return -EINVAL;
 867         }
 868         /*
 869          * Start with the current reta and modify it per reta_conf, as we
 870          * need to push the entire reta even if we only modify one entry.
 871          */
 872         rss_cpu = enic->rss_cpu;
 873         for (i = 0; i < reta_size; i++) {
 874                 idx = i / RTE_RETA_GROUP_SIZE;
 875                 shift = i % RTE_RETA_GROUP_SIZE;
 876                 if (reta_conf[idx].mask & (1ULL << shift))
 877                         rss_cpu.cpu[i / 4].b[i % 4] =
 878                                 enic_rte_rq_idx_to_sop_idx(
 879                                         reta_conf[idx].reta[shift]);
 880         }
 881         return enic_set_rss_reta(enic, &rss_cpu);
 882 }
 883
 884 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev,
 885                                        struct rte_eth_rss_conf *rss_conf)
 886 {
 887         struct enic *enic = pmd_priv(dev);
 888
 889         ENICPMD_FUNC_TRACE();
 890         return enic_set_rss_conf(enic, rss_conf);
 891 }
 892
 893 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 894                                          struct rte_eth_rss_conf *rss_conf)
 895 {
 896         struct enic *enic = pmd_priv(dev);
 897
 898         ENICPMD_FUNC_TRACE();
 899         if (rss_conf == NULL)
 900                 return -EINVAL;
 901         if (rss_conf->rss_key != NULL &&
 902             rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) {
 903                 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u"
 904                         " expected=%u+\n",
 905                         rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE);
 906                 return -EINVAL;
 907         }
 908         rss_conf->rss_hf = enic->rss_hf;
 909         if (rss_conf->rss_key != NULL) {
 910                 int i;
 911                 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) {
 912                         rss_conf->rss_key[i] =
 913                                 enic->rss_key.key[i / 10].b[i % 10];
 914                 }
 915                 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE;
 916         }
 917         return 0;
 918 }
 919
 920 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev,
 921                                      uint16_t rx_queue_id,
 922                                      struct rte_eth_rxq_info *qinfo)
 923 {
 924         struct enic *enic = pmd_priv(dev);
 925         struct vnic_rq *rq_sop;
 926         struct vnic_rq *rq_data;
 927         struct rte_eth_rxconf *conf;
 928         uint16_t sop_queue_idx;
 929         uint16_t data_queue_idx;
 930
 931         ENICPMD_FUNC_TRACE();
 932         sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 933         data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id);
 934         rq_sop = &enic->rq[sop_queue_idx];
 935         rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */
 936         qinfo->mp = rq_sop->mp;
 937         qinfo->scattered_rx = rq_sop->data_queue_enable;
 938         qinfo->nb_desc = rq_sop->ring.desc_count;
 939         if (qinfo->scattered_rx)
 940                 qinfo->nb_desc += rq_data->ring.desc_count;
 941         conf = &qinfo->conf;
 942         memset(conf, 0, sizeof(*conf));
 943         conf->rx_free_thresh = rq_sop->rx_free_thresh;
 944         conf->rx_drop_en = 1;
 945         /*
 946          * Except VLAN stripping (port setting), all the checksum offloads
 947          * are always enabled.
 948          */
 949         conf->offloads = enic->rx_offload_capa;
 950         if (!enic->ig_vlan_strip_en)
 951                 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
 952         /* rx_thresh and other fields are not applicable for enic */
 953 }
 954
 955 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev,
 956                                      uint16_t tx_queue_id,
 957                                      struct rte_eth_txq_info *qinfo)
 958 {
 959         struct enic *enic = pmd_priv(dev);
 960         struct vnic_wq *wq = &enic->wq[tx_queue_id];
 961
 962         ENICPMD_FUNC_TRACE();
 963         qinfo->nb_desc = wq->ring.desc_count;
 964         memset(&qinfo->conf, 0, sizeof(qinfo->conf));
 965         qinfo->conf.offloads = wq->offloads;
 966         /* tx_thresh, and all the other fields are not applicable for enic */
 967 }
 968
 969 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 970                                             uint16_t rx_queue_id)
 971 {
 972         struct enic *enic = pmd_priv(eth_dev);
 973
 974         ENICPMD_FUNC_TRACE();
 975         vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 976         return 0;
 977 }
 978
 979 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 980                                              uint16_t rx_queue_id)
 981 {
 982         struct enic *enic = pmd_priv(eth_dev);
 983
 984         ENICPMD_FUNC_TRACE();
 985         vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 986         return 0;
 987 }
 988
 989 static int udp_tunnel_common_check(struct enic *enic,
 990                                    struct rte_eth_udp_tunnel *tnl)
 991 {
 992         if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN)
 993                 return -ENOTSUP;
 994         if (!enic->overlay_offload) {
 995                 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not "
 996                              "supported\n");
 997                 return -ENOTSUP;
 998         }
 999         return 0;
1000 }
1001
1002 static int update_vxlan_port(struct enic *enic, uint16_t port)
1003 {
1004         if (vnic_dev_overlay_offload_cfg(enic->vdev,
1005                                          OVERLAY_CFG_VXLAN_PORT_UPDATE,
1006                                          port)) {
1007                 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n");
1008                 return -EINVAL;
1009         }
1010         ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port);
1011         enic->vxlan_port = port;
1012         return 0;
1013 }
1014
1015 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev,
1016                                            struct rte_eth_udp_tunnel *tnl)
1017 {
1018         struct enic *enic = pmd_priv(eth_dev);
1019         int ret;
1020
1021         ENICPMD_FUNC_TRACE();
1022         ret = udp_tunnel_common_check(enic, tnl);
1023         if (ret)
1024                 return ret;
1025         /*
1026          * The NIC has 1 configurable VXLAN port number. "Adding" a new port
1027          * number replaces it.
1028          */
1029         if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) {
1030                 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n",
1031                              tnl->udp_port);
1032                 return -EINVAL;
1033         }
1034         return update_vxlan_port(enic, tnl->udp_port);
1035 }
1036
1037 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev,
1038                                            struct rte_eth_udp_tunnel *tnl)
1039 {
1040         struct enic *enic = pmd_priv(eth_dev);
1041         int ret;
1042
1043         ENICPMD_FUNC_TRACE();
1044         ret = udp_tunnel_common_check(enic, tnl);
1045         if (ret)
1046                 return ret;
1047         /*
1048          * Clear the previously set port number and restore the
1049          * hardware default port number. Some drivers disable VXLAN
1050          * offloads when there are no configured port numbers. But
1051          * enic does not do that as VXLAN is part of overlay offload,
1052          * which is tied to inner RSS and TSO.
1053          */
1054         if (tnl->udp_port != enic->vxlan_port) {
1055                 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n",
1056                              tnl->udp_port);
1057                 return -EINVAL;
1058         }
1059         return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT);
1060 }
1061
1062 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev,
1063                                       char *fw_version, size_t fw_size)
1064 {
1065         struct vnic_devcmd_fw_info *info;
1066         struct enic *enic;
1067         int ret;
1068
1069         ENICPMD_FUNC_TRACE();
1070         if (fw_version == NULL || fw_size <= 0)
1071                 return -EINVAL;
1072         enic = pmd_priv(eth_dev);
1073         ret = vnic_dev_fw_info(enic->vdev, &info);
1074         if (ret)
1075                 return ret;
1076         snprintf(fw_version, fw_size, "%s %s",
1077                  info->fw_version, info->fw_build);
1078         fw_version[fw_size - 1] = '\0';
1079         return 0;
1080 }
1081
1082 static const struct eth_dev_ops enicpmd_eth_dev_ops = {
1083         .dev_configure        = enicpmd_dev_configure,
1084         .dev_start            = enicpmd_dev_start,
1085         .dev_stop             = enicpmd_dev_stop,
1086         .dev_set_link_up      = NULL,
1087         .dev_set_link_down    = NULL,
1088         .dev_close            = enicpmd_dev_close,
1089         .promiscuous_enable   = enicpmd_dev_promiscuous_enable,
1090         .promiscuous_disable  = enicpmd_dev_promiscuous_disable,
1091         .allmulticast_enable  = enicpmd_dev_allmulticast_enable,
1092         .allmulticast_disable = enicpmd_dev_allmulticast_disable,
1093         .link_update          = enicpmd_dev_link_update,
1094         .stats_get            = enicpmd_dev_stats_get,
1095         .stats_reset          = enicpmd_dev_stats_reset,
1096         .queue_stats_mapping_set = NULL,
1097         .dev_infos_get        = enicpmd_dev_info_get,
1098         .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get,
1099         .mtu_set              = enicpmd_mtu_set,
1100         .vlan_filter_set      = NULL,
1101         .vlan_tpid_set        = NULL,
1102         .vlan_offload_set     = enicpmd_vlan_offload_set,
1103         .vlan_strip_queue_set = NULL,
1104         .rx_queue_start       = enicpmd_dev_rx_queue_start,
1105         .rx_queue_stop        = enicpmd_dev_rx_queue_stop,
1106         .tx_queue_start       = enicpmd_dev_tx_queue_start,
1107         .tx_queue_stop        = enicpmd_dev_tx_queue_stop,
1108         .rx_queue_setup       = enicpmd_dev_rx_queue_setup,
1109         .rx_queue_release     = enicpmd_dev_rx_queue_release,
1110         .rx_queue_count       = enicpmd_dev_rx_queue_count,
1111         .rx_descriptor_done   = NULL,
1112         .tx_queue_setup       = enicpmd_dev_tx_queue_setup,
1113         .tx_queue_release     = enicpmd_dev_tx_queue_release,
1114         .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable,
1115         .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable,
1116         .rxq_info_get         = enicpmd_dev_rxq_info_get,
1117         .txq_info_get         = enicpmd_dev_txq_info_get,
1118         .dev_led_on           = NULL,
1119         .dev_led_off          = NULL,
1120         .flow_ctrl_get        = NULL,
1121         .flow_ctrl_set        = NULL,
1122         .priority_flow_ctrl_set = NULL,
1123         .mac_addr_add         = enicpmd_add_mac_addr,
1124         .mac_addr_remove      = enicpmd_remove_mac_addr,
1125         .mac_addr_set         = enicpmd_set_mac_addr,
1126         .set_mc_addr_list     = enicpmd_set_mc_addr_list,
1127         .filter_ctrl          = enicpmd_dev_filter_ctrl,
1128         .reta_query           = enicpmd_dev_rss_reta_query,
1129         .reta_update          = enicpmd_dev_rss_reta_update,
1130         .rss_hash_conf_get    = enicpmd_dev_rss_hash_conf_get,
1131         .rss_hash_update      = enicpmd_dev_rss_hash_update,
1132         .udp_tunnel_port_add  = enicpmd_dev_udp_tunnel_port_add,
1133         .udp_tunnel_port_del  = enicpmd_dev_udp_tunnel_port_del,
1134         .fw_version_get       = enicpmd_dev_fw_version_get,
1135 };
1136
1137 static int enic_parse_zero_one(const char *key,
1138                                const char *value,
1139                                void *opaque)
1140 {
1141         struct enic *enic;
1142         bool b;
1143
1144         enic = (struct enic *)opaque;
1145         if (strcmp(value, "0") == 0) {
1146                 b = false;
1147         } else if (strcmp(value, "1") == 0) {
1148                 b = true;
1149         } else {
1150                 dev_err(enic, "Invalid value for %s"
1151                         ": expected=0|1 given=%s\n", key, value);
1152                 return -EINVAL;
1153         }
1154         if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0)
1155                 enic->disable_overlay = b;
1156         if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0)
1157                 enic->enable_avx2_rx = b;
1158         if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0)
1159                 enic->geneve_opt_request = b;
1160         return 0;
1161 }
1162
1163 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key,
1164                                       const char *value,
1165                                       void *opaque)
1166 {
1167         struct enic *enic;
1168
1169         enic = (struct enic *)opaque;
1170         if (strcmp(value, "trunk") == 0) {
1171                 /* Trunk mode: always tag */
1172                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK;
1173         } else if (strcmp(value, "untag") == 0) {
1174                 /* Untag default VLAN mode: untag if VLAN = default VLAN */
1175                 enic->ig_vlan_rewrite_mode =
1176                         IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN;
1177         } else if (strcmp(value, "priority") == 0) {
1178                 /*
1179                  * Priority-tag default VLAN mode: priority tag (VLAN header
1180                  * with ID=0) if VLAN = default
1181                  */
1182                 enic->ig_vlan_rewrite_mode =
1183                         IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN;
1184         } else if (strcmp(value, "pass") == 0) {
1185                 /* Pass through mode: do not touch tags */
1186                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1187         } else {
1188                 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE
1189                         ": expected=trunk|untag|priority|pass given=%s\n",
1190                         value);
1191                 return -EINVAL;
1192         }
1193         return 0;
1194 }
1195
1196 static int enic_check_devargs(struct rte_eth_dev *dev)
1197 {
1198         static const char *const valid_keys[] = {
1199                 ENIC_DEVARG_DISABLE_OVERLAY,
1200                 ENIC_DEVARG_ENABLE_AVX2_RX,
1201                 ENIC_DEVARG_GENEVE_OPT,
1202                 ENIC_DEVARG_IG_VLAN_REWRITE,
1203                 NULL};
1204         struct enic *enic = pmd_priv(dev);
1205         struct rte_kvargs *kvlist;
1206
1207         ENICPMD_FUNC_TRACE();
1208
1209         enic->disable_overlay = false;
1210         enic->enable_avx2_rx = false;
1211         enic->geneve_opt_request = false;
1212         enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1213         if (!dev->device->devargs)
1214                 return 0;
1215         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1216         if (!kvlist)
1217                 return -EINVAL;
1218         if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY,
1219                                enic_parse_zero_one, enic) < 0 ||
1220             rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX,
1221                                enic_parse_zero_one, enic) < 0 ||
1222             rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT,
1223                                enic_parse_zero_one, enic) < 0 ||
1224             rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE,
1225                                enic_parse_ig_vlan_rewrite, enic) < 0) {
1226                 rte_kvargs_free(kvlist);
1227                 return -EINVAL;
1228         }
1229         rte_kvargs_free(kvlist);
1230         return 0;
1231 }
1232
1233 /* Initialize the driver
1234  * It returns 0 on success.
1235  */
1236 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev)
1237 {
1238         struct rte_pci_device *pdev;
1239         struct rte_pci_addr *addr;
1240         struct enic *enic = pmd_priv(eth_dev);
1241         int err;
1242
1243         ENICPMD_FUNC_TRACE();
1244
1245         eth_dev->dev_ops = &enicpmd_eth_dev_ops;
1246         eth_dev->rx_pkt_burst = &enic_recv_pkts;
1247         eth_dev->tx_pkt_burst = &enic_xmit_pkts;
1248         eth_dev->tx_pkt_prepare = &enic_prep_pkts;
1249         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1250                 enic_pick_tx_handler(eth_dev);
1251                 enic_pick_rx_handler(eth_dev);
1252                 return 0;
1253         }
1254         /* Only the primary sets up adapter and other data in shared memory */
1255         enic->port_id = eth_dev->data->port_id;
1256         enic->rte_dev = eth_dev;
1257         enic->dev_data = eth_dev->data;
1258         /* Let rte_eth_dev_close() release the port resources */
1259         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1260
1261         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
1262         rte_eth_copy_pci_info(eth_dev, pdev);
1263         enic->pdev = pdev;
1264         addr = &pdev->addr;
1265
1266         snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x",
1267                 addr->domain, addr->bus, addr->devid, addr->function);
1268
1269         err = enic_check_devargs(eth_dev);
1270         if (err)
1271                 return err;
1272         return enic_probe(enic);
1273 }
1274
1275 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1276         struct rte_pci_device *pci_dev)
1277 {
1278         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic),
1279                 eth_enicpmd_dev_init);
1280 }
1281
1282 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev)
1283 {
1284         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1285 }
1286
1287 static struct rte_pci_driver rte_enic_pmd = {
1288         .id_table = pci_id_enic_map,
1289         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1290         .probe = eth_enic_pci_probe,
1291         .remove = eth_enic_pci_remove,
1292 };
1293
1294 int dev_is_enic(struct rte_eth_dev *dev)
1295 {
1296         return dev->device->driver == &rte_enic_pmd.driver;
1297 }
1298
1299 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd);
1300 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map);
1301 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci");
1302 RTE_PMD_REGISTER_PARAM_STRING(net_enic,
1303         ENIC_DEVARG_DISABLE_OVERLAY "=0|1 "
1304         ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 "
1305         ENIC_DEVARG_GENEVE_OPT "=0|1 "
1306         ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass");