drivers/net/enic/enic_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  */
   5
   6 #include <stdio.h>
   7 #include <stdint.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_pci.h>
  11 #include <rte_bus_pci.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_ethdev_pci.h>
  14 #include <rte_kvargs.h>
  15 #include <rte_string_fns.h>
  16
  17 #include "vnic_intr.h"
  18 #include "vnic_cq.h"
  19 #include "vnic_wq.h"
  20 #include "vnic_rq.h"
  21 #include "vnic_enet.h"
  22 #include "enic.h"
  23
  24 int enic_pmd_logtype;
  25
  26 /*
  27  * The set of PCI devices this driver supports
  28  */
  29 #define CISCO_PCI_VENDOR_ID 0x1137
  30 static const struct rte_pci_id pci_id_enic_map[] = {
  31         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)},
  32         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)},
  33         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)},
  34         {.vendor_id = 0, /* sentinel */},
  35 };
  36
  37 /* Supported link speeds of production VIC models */
  38 static const struct vic_speed_capa {
  39         uint16_t sub_devid;
  40         uint32_t capa;
  41 } vic_speed_capa_map[] = {
  42         { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */
  43         { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */
  44         { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */
  45         { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */
  46         { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */
  47         { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */
  48         { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */
  49         { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */
  50         { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */
  51         { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */
  52         { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */
  53         { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */
  54         { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */
  55         { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */
  56         { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  57                   ETH_LINK_SPEED_40G }, /* 1440 Mezz */
  58         { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  59                   ETH_LINK_SPEED_40G }, /* 1480 MLOM */
  60         { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */
  61         { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */
  62         { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */
  63         { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */
  64         { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */
  65         { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */
  66         { 0, 0 }, /* End marker */
  67 };
  68
  69 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
  70 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx"
  71 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt"
  72 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite"
  73
  74 RTE_INIT(enicpmd_init_log)
  75 {
  76         enic_pmd_logtype = rte_log_register("pmd.net.enic");
  77         if (enic_pmd_logtype >= 0)
  78                 rte_log_set_level(enic_pmd_logtype, RTE_LOG_INFO);
  79 }
  80
  81 static int
  82 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev,
  83                         enum rte_filter_op filter_op, void *arg)
  84 {
  85         struct enic *enic = pmd_priv(eth_dev);
  86         int ret = 0;
  87
  88         ENICPMD_FUNC_TRACE();
  89         if (filter_op == RTE_ETH_FILTER_NOP)
  90                 return 0;
  91
  92         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
  93                 return -EINVAL;
  94
  95         switch (filter_op) {
  96         case RTE_ETH_FILTER_ADD:
  97         case RTE_ETH_FILTER_UPDATE:
  98                 ret = enic_fdir_add_fltr(enic,
  99                         (struct rte_eth_fdir_filter *)arg);
 100                 break;
 101
 102         case RTE_ETH_FILTER_DELETE:
 103                 ret = enic_fdir_del_fltr(enic,
 104                         (struct rte_eth_fdir_filter *)arg);
 105                 break;
 106
 107         case RTE_ETH_FILTER_STATS:
 108                 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg);
 109                 break;
 110
 111         case RTE_ETH_FILTER_FLUSH:
 112                 dev_warning(enic, "unsupported operation %u", filter_op);
 113                 ret = -ENOTSUP;
 114                 break;
 115         case RTE_ETH_FILTER_INFO:
 116                 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg);
 117                 break;
 118         default:
 119                 dev_err(enic, "unknown operation %u", filter_op);
 120                 ret = -EINVAL;
 121                 break;
 122         }
 123         return ret;
 124 }
 125
 126 static int
 127 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev,
 128                      enum rte_filter_type filter_type,
 129                      enum rte_filter_op filter_op,
 130                      void *arg)
 131 {
 132         struct enic *enic = pmd_priv(dev);
 133         int ret = 0;
 134
 135         ENICPMD_FUNC_TRACE();
 136
 137         /*
 138          * Currently, when Geneve with options offload is enabled, host
 139          * cannot insert match-action rules.
 140          */
 141         if (enic->geneve_opt_enabled)
 142                 return -ENOTSUP;
 143         switch (filter_type) {
 144         case RTE_ETH_FILTER_GENERIC:
 145                 if (filter_op != RTE_ETH_FILTER_GET)
 146                         return -EINVAL;
 147                 if (enic->flow_filter_mode == FILTER_FLOWMAN)
 148                         *(const void **)arg = &enic_fm_flow_ops;
 149                 else
 150                         *(const void **)arg = &enic_flow_ops;
 151                 break;
 152         case RTE_ETH_FILTER_FDIR:
 153                 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg);
 154                 break;
 155         default:
 156                 dev_warning(enic, "Filter type (%d) not supported",
 157                         filter_type);
 158                 ret = -EINVAL;
 159                 break;
 160         }
 161
 162         return ret;
 163 }
 164
 165 static void enicpmd_dev_tx_queue_release(void *txq)
 166 {
 167         ENICPMD_FUNC_TRACE();
 168
 169         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 170                 return;
 171
 172         enic_free_wq(txq);
 173 }
 174
 175 static int enicpmd_dev_setup_intr(struct enic *enic)
 176 {
 177         int ret;
 178         unsigned int index;
 179
 180         ENICPMD_FUNC_TRACE();
 181
 182         /* Are we done with the init of all the queues? */
 183         for (index = 0; index < enic->cq_count; index++) {
 184                 if (!enic->cq[index].ctrl)
 185                         break;
 186         }
 187         if (enic->cq_count != index)
 188                 return 0;
 189         for (index = 0; index < enic->wq_count; index++) {
 190                 if (!enic->wq[index].ctrl)
 191                         break;
 192         }
 193         if (enic->wq_count != index)
 194                 return 0;
 195         /* check start of packet (SOP) RQs only in case scatter is disabled. */
 196         for (index = 0; index < enic->rq_count; index++) {
 197                 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl)
 198                         break;
 199         }
 200         if (enic->rq_count != index)
 201                 return 0;
 202
 203         ret = enic_alloc_intr_resources(enic);
 204         if (ret) {
 205                 dev_err(enic, "alloc intr failed\n");
 206                 return ret;
 207         }
 208         enic_init_vnic_resources(enic);
 209
 210         ret = enic_setup_finish(enic);
 211         if (ret)
 212                 dev_err(enic, "setup could not be finished\n");
 213
 214         return ret;
 215 }
 216
 217 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 218         uint16_t queue_idx,
 219         uint16_t nb_desc,
 220         unsigned int socket_id,
 221         const struct rte_eth_txconf *tx_conf)
 222 {
 223         int ret;
 224         struct enic *enic = pmd_priv(eth_dev);
 225         struct vnic_wq *wq;
 226
 227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 228                 return -E_RTE_SECONDARY;
 229
 230         ENICPMD_FUNC_TRACE();
 231         RTE_ASSERT(queue_idx < enic->conf_wq_count);
 232         wq = &enic->wq[queue_idx];
 233         wq->offloads = tx_conf->offloads |
 234                 eth_dev->data->dev_conf.txmode.offloads;
 235         eth_dev->data->tx_queues[queue_idx] = (void *)wq;
 236
 237         ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc);
 238         if (ret) {
 239                 dev_err(enic, "error in allocating wq\n");
 240                 return ret;
 241         }
 242
 243         return enicpmd_dev_setup_intr(enic);
 244 }
 245
 246 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
 247         uint16_t queue_idx)
 248 {
 249         struct enic *enic = pmd_priv(eth_dev);
 250
 251         ENICPMD_FUNC_TRACE();
 252
 253         enic_start_wq(enic, queue_idx);
 254
 255         return 0;
 256 }
 257
 258 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
 259         uint16_t queue_idx)
 260 {
 261         int ret;
 262         struct enic *enic = pmd_priv(eth_dev);
 263
 264         ENICPMD_FUNC_TRACE();
 265
 266         ret = enic_stop_wq(enic, queue_idx);
 267         if (ret)
 268                 dev_err(enic, "error in stopping wq %d\n", queue_idx);
 269
 270         return ret;
 271 }
 272
 273 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
 274         uint16_t queue_idx)
 275 {
 276         struct enic *enic = pmd_priv(eth_dev);
 277
 278         ENICPMD_FUNC_TRACE();
 279
 280         enic_start_rq(enic, queue_idx);
 281
 282         return 0;
 283 }
 284
 285 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
 286         uint16_t queue_idx)
 287 {
 288         int ret;
 289         struct enic *enic = pmd_priv(eth_dev);
 290
 291         ENICPMD_FUNC_TRACE();
 292
 293         ret = enic_stop_rq(enic, queue_idx);
 294         if (ret)
 295                 dev_err(enic, "error in stopping rq %d\n", queue_idx);
 296
 297         return ret;
 298 }
 299
 300 static void enicpmd_dev_rx_queue_release(void *rxq)
 301 {
 302         ENICPMD_FUNC_TRACE();
 303
 304         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 305                 return;
 306
 307         enic_free_rq(rxq);
 308 }
 309
 310 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev,
 311                                            uint16_t rx_queue_id)
 312 {
 313         struct enic *enic = pmd_priv(dev);
 314         uint32_t queue_count = 0;
 315         struct vnic_cq *cq;
 316         uint32_t cq_tail;
 317         uint16_t cq_idx;
 318         int rq_num;
 319
 320         rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 321         cq = &enic->cq[enic_cq_rq(enic, rq_num)];
 322         cq_idx = cq->to_clean;
 323
 324         cq_tail = ioread32(&cq->ctrl->cq_tail);
 325
 326         if (cq_tail < cq_idx)
 327                 cq_tail += cq->ring.desc_count;
 328
 329         queue_count = cq_tail - cq_idx;
 330
 331         return queue_count;
 332 }
 333
 334 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 335         uint16_t queue_idx,
 336         uint16_t nb_desc,
 337         unsigned int socket_id,
 338         const struct rte_eth_rxconf *rx_conf,
 339         struct rte_mempool *mp)
 340 {
 341         int ret;
 342         struct enic *enic = pmd_priv(eth_dev);
 343
 344         ENICPMD_FUNC_TRACE();
 345
 346         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 347                 return -E_RTE_SECONDARY;
 348         RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count);
 349         eth_dev->data->rx_queues[queue_idx] =
 350                 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)];
 351
 352         ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc,
 353                             rx_conf->rx_free_thresh);
 354         if (ret) {
 355                 dev_err(enic, "error in allocating rq\n");
 356                 return ret;
 357         }
 358
 359         return enicpmd_dev_setup_intr(enic);
 360 }
 361
 362 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 363 {
 364         struct enic *enic = pmd_priv(eth_dev);
 365         uint64_t offloads;
 366
 367         ENICPMD_FUNC_TRACE();
 368
 369         offloads = eth_dev->data->dev_conf.rxmode.offloads;
 370         if (mask & ETH_VLAN_STRIP_MASK) {
 371                 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 372                         enic->ig_vlan_strip_en = 1;
 373                 else
 374                         enic->ig_vlan_strip_en = 0;
 375         }
 376
 377         if ((mask & ETH_VLAN_FILTER_MASK) &&
 378             (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
 379                 dev_warning(enic,
 380                         "Configuration of VLAN filter is not supported\n");
 381         }
 382
 383         if ((mask & ETH_VLAN_EXTEND_MASK) &&
 384             (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) {
 385                 dev_warning(enic,
 386                         "Configuration of extended VLAN is not supported\n");
 387         }
 388
 389         return enic_set_vlan_strip(enic);
 390 }
 391
 392 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev)
 393 {
 394         int ret;
 395         int mask;
 396         struct enic *enic = pmd_priv(eth_dev);
 397
 398         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 399                 return -E_RTE_SECONDARY;
 400
 401         ENICPMD_FUNC_TRACE();
 402         ret = enic_set_vnic_res(enic);
 403         if (ret) {
 404                 dev_err(enic, "Set vNIC resource num  failed, aborting\n");
 405                 return ret;
 406         }
 407
 408         enic->mc_count = 0;
 409         enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads &
 410                                   DEV_RX_OFFLOAD_CHECKSUM);
 411         /* All vlan offload masks to apply the current settings */
 412         mask = ETH_VLAN_STRIP_MASK |
 413                 ETH_VLAN_FILTER_MASK |
 414                 ETH_VLAN_EXTEND_MASK;
 415         ret = enicpmd_vlan_offload_set(eth_dev, mask);
 416         if (ret) {
 417                 dev_err(enic, "Failed to configure VLAN offloads\n");
 418                 return ret;
 419         }
 420         /*
 421          * Initialize RSS with the default reta and key. If the user key is
 422          * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the
 423          * default key.
 424          */
 425         return enic_init_rss_nic_cfg(enic);
 426 }
 427
 428 /* Start the device.
 429  * It returns 0 on success.
 430  */
 431 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev)
 432 {
 433         struct enic *enic = pmd_priv(eth_dev);
 434
 435         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 436                 return -E_RTE_SECONDARY;
 437
 438         ENICPMD_FUNC_TRACE();
 439         return enic_enable(enic);
 440 }
 441
 442 /*
 443  * Stop device: disable rx and tx functions to allow for reconfiguring.
 444  */
 445 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev)
 446 {
 447         struct rte_eth_link link;
 448         struct enic *enic = pmd_priv(eth_dev);
 449
 450         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 451                 return;
 452
 453         ENICPMD_FUNC_TRACE();
 454         enic_disable(enic);
 455
 456         memset(&link, 0, sizeof(link));
 457         rte_eth_linkstatus_set(eth_dev, &link);
 458 }
 459
 460 /*
 461  * Stop device.
 462  */
 463 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev)
 464 {
 465         struct enic *enic = pmd_priv(eth_dev);
 466
 467         ENICPMD_FUNC_TRACE();
 468         enic_remove(enic);
 469 }
 470
 471 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,
 472         __rte_unused int wait_to_complete)
 473 {
 474         ENICPMD_FUNC_TRACE();
 475         return enic_link_update(eth_dev);
 476 }
 477
 478 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,
 479         struct rte_eth_stats *stats)
 480 {
 481         struct enic *enic = pmd_priv(eth_dev);
 482
 483         ENICPMD_FUNC_TRACE();
 484         return enic_dev_stats_get(enic, stats);
 485 }
 486
 487 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)
 488 {
 489         struct enic *enic = pmd_priv(eth_dev);
 490
 491         ENICPMD_FUNC_TRACE();
 492         return enic_dev_stats_clear(enic);
 493 }
 494
 495 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev)
 496 {
 497         const struct vic_speed_capa *m;
 498         struct rte_pci_device *pdev;
 499         uint16_t id;
 500
 501         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
 502         id = pdev->id.subsystem_device_id;
 503         for (m = vic_speed_capa_map; m->sub_devid != 0; m++) {
 504                 if (m->sub_devid == id)
 505                         return m->capa;
 506         }
 507         /* 1300 and later models are at least 40G */
 508         if (id >= 0x0100)
 509                 return ETH_LINK_SPEED_40G;
 510         /* VFs have subsystem id 0, check device id */
 511         if (id == 0) {
 512                 /* Newer VF implies at least 40G model */
 513                 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN)
 514                         return ETH_LINK_SPEED_40G;
 515         }
 516         return ETH_LINK_SPEED_10G;
 517 }
 518
 519 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
 520         struct rte_eth_dev_info *device_info)
 521 {
 522         struct enic *enic = pmd_priv(eth_dev);
 523
 524         ENICPMD_FUNC_TRACE();
 525         /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */
 526         device_info->max_rx_queues = enic->conf_rq_count / 2;
 527         device_info->max_tx_queues = enic->conf_wq_count;
 528         device_info->min_rx_bufsize = ENIC_MIN_MTU;
 529         /* "Max" mtu is not a typo. HW receives packet sizes up to the
 530          * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is
 531          * a hint to the driver to size receive buffers accordingly so that
 532          * larger-than-vnic-mtu packets get truncated.. For DPDK, we let
 533          * the user decide the buffer size via rxmode.max_rx_pkt_len, basically
 534          * ignoring vNIC mtu.
 535          */
 536         device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu);
 537         device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS;
 538         device_info->min_mtu = ENIC_MIN_MTU;
 539         device_info->max_mtu = enic->max_mtu;
 540         device_info->rx_offload_capa = enic->rx_offload_capa;
 541         device_info->tx_offload_capa = enic->tx_offload_capa;
 542         device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa;
 543         device_info->default_rxconf = (struct rte_eth_rxconf) {
 544                 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH
 545         };
 546         device_info->reta_size = enic->reta_size;
 547         device_info->hash_key_size = enic->hash_key_size;
 548         device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads;
 549         device_info->rx_desc_lim = (struct rte_eth_desc_lim) {
 550                 .nb_max = enic->config.rq_desc_count,
 551                 .nb_min = ENIC_MIN_RQ_DESCS,
 552                 .nb_align = ENIC_ALIGN_DESCS,
 553         };
 554         device_info->tx_desc_lim = (struct rte_eth_desc_lim) {
 555                 .nb_max = enic->config.wq_desc_count,
 556                 .nb_min = ENIC_MIN_WQ_DESCS,
 557                 .nb_align = ENIC_ALIGN_DESCS,
 558                 .nb_seg_max = ENIC_TX_XMIT_MAX,
 559                 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC,
 560         };
 561         device_info->default_rxportconf = (struct rte_eth_dev_portconf) {
 562                 .burst_size = ENIC_DEFAULT_RX_BURST,
 563                 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max,
 564                         ENIC_DEFAULT_RX_RING_SIZE),
 565                 .nb_queues = ENIC_DEFAULT_RX_RINGS,
 566         };
 567         device_info->default_txportconf = (struct rte_eth_dev_portconf) {
 568                 .burst_size = ENIC_DEFAULT_TX_BURST,
 569                 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max,
 570                         ENIC_DEFAULT_TX_RING_SIZE),
 571                 .nb_queues = ENIC_DEFAULT_TX_RINGS,
 572         };
 573         device_info->speed_capa = speed_capa_from_pci_id(eth_dev);
 574
 575         return 0;
 576 }
 577
 578 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 579 {
 580         static const uint32_t ptypes[] = {
 581                 RTE_PTYPE_L2_ETHER,
 582                 RTE_PTYPE_L2_ETHER_VLAN,
 583                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 584                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 585                 RTE_PTYPE_L4_TCP,
 586                 RTE_PTYPE_L4_UDP,
 587                 RTE_PTYPE_L4_FRAG,
 588                 RTE_PTYPE_L4_NONFRAG,
 589                 RTE_PTYPE_UNKNOWN
 590         };
 591         static const uint32_t ptypes_overlay[] = {
 592                 RTE_PTYPE_L2_ETHER,
 593                 RTE_PTYPE_L2_ETHER_VLAN,
 594                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 595                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 596                 RTE_PTYPE_L4_TCP,
 597                 RTE_PTYPE_L4_UDP,
 598                 RTE_PTYPE_L4_FRAG,
 599                 RTE_PTYPE_L4_NONFRAG,
 600                 RTE_PTYPE_TUNNEL_GRENAT,
 601                 RTE_PTYPE_INNER_L2_ETHER,
 602                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 603                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 604                 RTE_PTYPE_INNER_L4_TCP,
 605                 RTE_PTYPE_INNER_L4_UDP,
 606                 RTE_PTYPE_INNER_L4_FRAG,
 607                 RTE_PTYPE_INNER_L4_NONFRAG,
 608                 RTE_PTYPE_UNKNOWN
 609         };
 610
 611         if (dev->rx_pkt_burst != enic_dummy_recv_pkts &&
 612             dev->rx_pkt_burst != NULL) {
 613                 struct enic *enic = pmd_priv(dev);
 614                 if (enic->overlay_offload)
 615                         return ptypes_overlay;
 616                 else
 617                         return ptypes;
 618         }
 619         return NULL;
 620 }
 621
 622 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 623 {
 624         struct enic *enic = pmd_priv(eth_dev);
 625         int ret;
 626
 627         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 628                 return -E_RTE_SECONDARY;
 629
 630         ENICPMD_FUNC_TRACE();
 631
 632         enic->promisc = 1;
 633         ret = enic_add_packet_filter(enic);
 634         if (ret != 0)
 635                 enic->promisc = 0;
 636
 637         return ret;
 638 }
 639
 640 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 641 {
 642         struct enic *enic = pmd_priv(eth_dev);
 643         int ret;
 644
 645         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 646                 return -E_RTE_SECONDARY;
 647
 648         ENICPMD_FUNC_TRACE();
 649         enic->promisc = 0;
 650         ret = enic_add_packet_filter(enic);
 651         if (ret != 0)
 652                 enic->promisc = 1;
 653
 654         return ret;
 655 }
 656
 657 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 658 {
 659         struct enic *enic = pmd_priv(eth_dev);
 660         int ret;
 661
 662         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 663                 return -E_RTE_SECONDARY;
 664
 665         ENICPMD_FUNC_TRACE();
 666         enic->allmulti = 1;
 667         ret = enic_add_packet_filter(enic);
 668         if (ret != 0)
 669                 enic->allmulti = 0;
 670
 671         return ret;
 672 }
 673
 674 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 675 {
 676         struct enic *enic = pmd_priv(eth_dev);
 677         int ret;
 678
 679         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 680                 return -E_RTE_SECONDARY;
 681
 682         ENICPMD_FUNC_TRACE();
 683         enic->allmulti = 0;
 684         ret = enic_add_packet_filter(enic);
 685         if (ret != 0)
 686                 enic->allmulti = 1;
 687
 688         return ret;
 689 }
 690
 691 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev,
 692         struct rte_ether_addr *mac_addr,
 693         __rte_unused uint32_t index, __rte_unused uint32_t pool)
 694 {
 695         struct enic *enic = pmd_priv(eth_dev);
 696
 697         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 698                 return -E_RTE_SECONDARY;
 699
 700         ENICPMD_FUNC_TRACE();
 701         return enic_set_mac_address(enic, mac_addr->addr_bytes);
 702 }
 703
 704 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index)
 705 {
 706         struct enic *enic = pmd_priv(eth_dev);
 707
 708         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 709                 return;
 710
 711         ENICPMD_FUNC_TRACE();
 712         if (enic_del_mac_address(enic, index))
 713                 dev_err(enic, "del mac addr failed\n");
 714 }
 715
 716 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev,
 717                                 struct rte_ether_addr *addr)
 718 {
 719         struct enic *enic = pmd_priv(eth_dev);
 720         int ret;
 721
 722         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 723                 return -E_RTE_SECONDARY;
 724
 725         ENICPMD_FUNC_TRACE();
 726         ret = enic_del_mac_address(enic, 0);
 727         if (ret)
 728                 return ret;
 729         return enic_set_mac_address(enic, addr->addr_bytes);
 730 }
 731
 732 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add)
 733 {
 734         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 735
 736         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 737         ENICPMD_LOG(DEBUG, " %s address %s\n",
 738                      add ? "add" : "remove", mac_str);
 739 }
 740
 741 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev,
 742                                     struct rte_ether_addr *mc_addr_set,
 743                                     uint32_t nb_mc_addr)
 744 {
 745         struct enic *enic = pmd_priv(eth_dev);
 746         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 747         struct rte_ether_addr *addr;
 748         uint32_t i, j;
 749         int ret;
 750
 751         ENICPMD_FUNC_TRACE();
 752
 753         /* Validate the given addresses first */
 754         for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) {
 755                 addr = &mc_addr_set[i];
 756                 if (!rte_is_multicast_ether_addr(addr) ||
 757                     rte_is_broadcast_ether_addr(addr)) {
 758                         rte_ether_format_addr(mac_str,
 759                                         RTE_ETHER_ADDR_FMT_SIZE, addr);
 760                         ENICPMD_LOG(ERR, " invalid multicast address %s\n",
 761                                      mac_str);
 762                         return -EINVAL;
 763                 }
 764         }
 765
 766         /* Flush all if requested */
 767         if (nb_mc_addr == 0 || mc_addr_set == NULL) {
 768                 ENICPMD_LOG(DEBUG, " flush multicast addresses\n");
 769                 for (i = 0; i < enic->mc_count; i++) {
 770                         addr = &enic->mc_addrs[i];
 771                         debug_log_add_del_addr(addr, false);
 772                         ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 773                         if (ret)
 774                                 return ret;
 775                 }
 776                 enic->mc_count = 0;
 777                 return 0;
 778         }
 779
 780         if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) {
 781                 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n",
 782                              ENIC_MULTICAST_PERFECT_FILTERS);
 783                 return -ENOSPC;
 784         }
 785         /*
 786          * devcmd is slow, so apply the difference instead of flushing and
 787          * adding everything.
 788          * 1. Delete addresses on the NIC but not on the host
 789          */
 790         for (i = 0; i < enic->mc_count; i++) {
 791                 addr = &enic->mc_addrs[i];
 792                 for (j = 0; j < nb_mc_addr; j++) {
 793                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j]))
 794                                 break;
 795                 }
 796                 if (j < nb_mc_addr)
 797                         continue;
 798                 debug_log_add_del_addr(addr, false);
 799                 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 800                 if (ret)
 801                         return ret;
 802         }
 803         /* 2. Add addresses on the host but not on the NIC */
 804         for (i = 0; i < nb_mc_addr; i++) {
 805                 addr = &mc_addr_set[i];
 806                 for (j = 0; j < enic->mc_count; j++) {
 807                         if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j]))
 808                                 break;
 809                 }
 810                 if (j < enic->mc_count)
 811                         continue;
 812                 debug_log_add_del_addr(addr, true);
 813                 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes);
 814                 if (ret)
 815                         return ret;
 816         }
 817         /* Keep a copy so we can flush/apply later on.. */
 818         memcpy(enic->mc_addrs, mc_addr_set,
 819                nb_mc_addr * sizeof(struct rte_ether_addr));
 820         enic->mc_count = nb_mc_addr;
 821         return 0;
 822 }
 823
 824 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 825 {
 826         struct enic *enic = pmd_priv(eth_dev);
 827
 828         ENICPMD_FUNC_TRACE();
 829         return enic_set_mtu(enic, mtu);
 830 }
 831
 832 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev,
 833                                       struct rte_eth_rss_reta_entry64
 834                                       *reta_conf,
 835                                       uint16_t reta_size)
 836 {
 837         struct enic *enic = pmd_priv(dev);
 838         uint16_t i, idx, shift;
 839
 840         ENICPMD_FUNC_TRACE();
 841         if (reta_size != ENIC_RSS_RETA_SIZE) {
 842                 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n",
 843                         reta_size, ENIC_RSS_RETA_SIZE);
 844                 return -EINVAL;
 845         }
 846
 847         for (i = 0; i < reta_size; i++) {
 848                 idx = i / RTE_RETA_GROUP_SIZE;
 849                 shift = i % RTE_RETA_GROUP_SIZE;
 850                 if (reta_conf[idx].mask & (1ULL << shift))
 851                         reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx(
 852                                 enic->rss_cpu.cpu[i / 4].b[i % 4]);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev,
 859                                        struct rte_eth_rss_reta_entry64
 860                                        *reta_conf,
 861                                        uint16_t reta_size)
 862 {
 863         struct enic *enic = pmd_priv(dev);
 864         union vnic_rss_cpu rss_cpu;
 865         uint16_t i, idx, shift;
 866
 867         ENICPMD_FUNC_TRACE();
 868         if (reta_size != ENIC_RSS_RETA_SIZE) {
 869                 dev_err(enic, "reta_update: wrong reta_size. given=%u"
 870                         " expected=%u\n",
 871                         reta_size, ENIC_RSS_RETA_SIZE);
 872                 return -EINVAL;
 873         }
 874         /*
 875          * Start with the current reta and modify it per reta_conf, as we
 876          * need to push the entire reta even if we only modify one entry.
 877          */
 878         rss_cpu = enic->rss_cpu;
 879         for (i = 0; i < reta_size; i++) {
 880                 idx = i / RTE_RETA_GROUP_SIZE;
 881                 shift = i % RTE_RETA_GROUP_SIZE;
 882                 if (reta_conf[idx].mask & (1ULL << shift))
 883                         rss_cpu.cpu[i / 4].b[i % 4] =
 884                                 enic_rte_rq_idx_to_sop_idx(
 885                                         reta_conf[idx].reta[shift]);
 886         }
 887         return enic_set_rss_reta(enic, &rss_cpu);
 888 }
 889
 890 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev,
 891                                        struct rte_eth_rss_conf *rss_conf)
 892 {
 893         struct enic *enic = pmd_priv(dev);
 894
 895         ENICPMD_FUNC_TRACE();
 896         return enic_set_rss_conf(enic, rss_conf);
 897 }
 898
 899 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 900                                          struct rte_eth_rss_conf *rss_conf)
 901 {
 902         struct enic *enic = pmd_priv(dev);
 903
 904         ENICPMD_FUNC_TRACE();
 905         if (rss_conf == NULL)
 906                 return -EINVAL;
 907         if (rss_conf->rss_key != NULL &&
 908             rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) {
 909                 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u"
 910                         " expected=%u+\n",
 911                         rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE);
 912                 return -EINVAL;
 913         }
 914         rss_conf->rss_hf = enic->rss_hf;
 915         if (rss_conf->rss_key != NULL) {
 916                 int i;
 917                 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) {
 918                         rss_conf->rss_key[i] =
 919                                 enic->rss_key.key[i / 10].b[i % 10];
 920                 }
 921                 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE;
 922         }
 923         return 0;
 924 }
 925
 926 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev,
 927                                      uint16_t rx_queue_id,
 928                                      struct rte_eth_rxq_info *qinfo)
 929 {
 930         struct enic *enic = pmd_priv(dev);
 931         struct vnic_rq *rq_sop;
 932         struct vnic_rq *rq_data;
 933         struct rte_eth_rxconf *conf;
 934         uint16_t sop_queue_idx;
 935         uint16_t data_queue_idx;
 936
 937         ENICPMD_FUNC_TRACE();
 938         sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 939         data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id);
 940         rq_sop = &enic->rq[sop_queue_idx];
 941         rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */
 942         qinfo->mp = rq_sop->mp;
 943         qinfo->scattered_rx = rq_sop->data_queue_enable;
 944         qinfo->nb_desc = rq_sop->ring.desc_count;
 945         if (qinfo->scattered_rx)
 946                 qinfo->nb_desc += rq_data->ring.desc_count;
 947         conf = &qinfo->conf;
 948         memset(conf, 0, sizeof(*conf));
 949         conf->rx_free_thresh = rq_sop->rx_free_thresh;
 950         conf->rx_drop_en = 1;
 951         /*
 952          * Except VLAN stripping (port setting), all the checksum offloads
 953          * are always enabled.
 954          */
 955         conf->offloads = enic->rx_offload_capa;
 956         if (!enic->ig_vlan_strip_en)
 957                 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
 958         /* rx_thresh and other fields are not applicable for enic */
 959 }
 960
 961 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev,
 962                                      uint16_t tx_queue_id,
 963                                      struct rte_eth_txq_info *qinfo)
 964 {
 965         struct enic *enic = pmd_priv(dev);
 966         struct vnic_wq *wq = &enic->wq[tx_queue_id];
 967
 968         ENICPMD_FUNC_TRACE();
 969         qinfo->nb_desc = wq->ring.desc_count;
 970         memset(&qinfo->conf, 0, sizeof(qinfo->conf));
 971         qinfo->conf.offloads = wq->offloads;
 972         /* tx_thresh, and all the other fields are not applicable for enic */
 973 }
 974
 975 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 976                                             uint16_t rx_queue_id)
 977 {
 978         struct enic *enic = pmd_priv(eth_dev);
 979
 980         ENICPMD_FUNC_TRACE();
 981         vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 982         return 0;
 983 }
 984
 985 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 986                                              uint16_t rx_queue_id)
 987 {
 988         struct enic *enic = pmd_priv(eth_dev);
 989
 990         ENICPMD_FUNC_TRACE();
 991         vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 992         return 0;
 993 }
 994
 995 static int udp_tunnel_common_check(struct enic *enic,
 996                                    struct rte_eth_udp_tunnel *tnl)
 997 {
 998         if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN)
 999                 return -ENOTSUP;
1000         if (!enic->overlay_offload) {
1001                 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not "
1002                              "supported\n");
1003                 return -ENOTSUP;
1004         }
1005         return 0;
1006 }
1007
1008 static int update_vxlan_port(struct enic *enic, uint16_t port)
1009 {
1010         if (vnic_dev_overlay_offload_cfg(enic->vdev,
1011                                          OVERLAY_CFG_VXLAN_PORT_UPDATE,
1012                                          port)) {
1013                 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n");
1014                 return -EINVAL;
1015         }
1016         ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port);
1017         enic->vxlan_port = port;
1018         return 0;
1019 }
1020
1021 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev,
1022                                            struct rte_eth_udp_tunnel *tnl)
1023 {
1024         struct enic *enic = pmd_priv(eth_dev);
1025         int ret;
1026
1027         ENICPMD_FUNC_TRACE();
1028         ret = udp_tunnel_common_check(enic, tnl);
1029         if (ret)
1030                 return ret;
1031         /*
1032          * The NIC has 1 configurable VXLAN port number. "Adding" a new port
1033          * number replaces it.
1034          */
1035         if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) {
1036                 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n",
1037                              tnl->udp_port);
1038                 return -EINVAL;
1039         }
1040         return update_vxlan_port(enic, tnl->udp_port);
1041 }
1042
1043 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev,
1044                                            struct rte_eth_udp_tunnel *tnl)
1045 {
1046         struct enic *enic = pmd_priv(eth_dev);
1047         int ret;
1048
1049         ENICPMD_FUNC_TRACE();
1050         ret = udp_tunnel_common_check(enic, tnl);
1051         if (ret)
1052                 return ret;
1053         /*
1054          * Clear the previously set port number and restore the
1055          * hardware default port number. Some drivers disable VXLAN
1056          * offloads when there are no configured port numbers. But
1057          * enic does not do that as VXLAN is part of overlay offload,
1058          * which is tied to inner RSS and TSO.
1059          */
1060         if (tnl->udp_port != enic->vxlan_port) {
1061                 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n",
1062                              tnl->udp_port);
1063                 return -EINVAL;
1064         }
1065         return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT);
1066 }
1067
1068 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev,
1069                                       char *fw_version, size_t fw_size)
1070 {
1071         struct vnic_devcmd_fw_info *info;
1072         struct enic *enic;
1073         int ret;
1074
1075         ENICPMD_FUNC_TRACE();
1076         if (fw_version == NULL || fw_size <= 0)
1077                 return -EINVAL;
1078         enic = pmd_priv(eth_dev);
1079         ret = vnic_dev_fw_info(enic->vdev, &info);
1080         if (ret)
1081                 return ret;
1082         snprintf(fw_version, fw_size, "%s %s",
1083                  info->fw_version, info->fw_build);
1084         fw_version[fw_size - 1] = '\0';
1085         return 0;
1086 }
1087
1088 static const struct eth_dev_ops enicpmd_eth_dev_ops = {
1089         .dev_configure        = enicpmd_dev_configure,
1090         .dev_start            = enicpmd_dev_start,
1091         .dev_stop             = enicpmd_dev_stop,
1092         .dev_set_link_up      = NULL,
1093         .dev_set_link_down    = NULL,
1094         .dev_close            = enicpmd_dev_close,
1095         .promiscuous_enable   = enicpmd_dev_promiscuous_enable,
1096         .promiscuous_disable  = enicpmd_dev_promiscuous_disable,
1097         .allmulticast_enable  = enicpmd_dev_allmulticast_enable,
1098         .allmulticast_disable = enicpmd_dev_allmulticast_disable,
1099         .link_update          = enicpmd_dev_link_update,
1100         .stats_get            = enicpmd_dev_stats_get,
1101         .stats_reset          = enicpmd_dev_stats_reset,
1102         .queue_stats_mapping_set = NULL,
1103         .dev_infos_get        = enicpmd_dev_info_get,
1104         .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get,
1105         .mtu_set              = enicpmd_mtu_set,
1106         .vlan_filter_set      = NULL,
1107         .vlan_tpid_set        = NULL,
1108         .vlan_offload_set     = enicpmd_vlan_offload_set,
1109         .vlan_strip_queue_set = NULL,
1110         .rx_queue_start       = enicpmd_dev_rx_queue_start,
1111         .rx_queue_stop        = enicpmd_dev_rx_queue_stop,
1112         .tx_queue_start       = enicpmd_dev_tx_queue_start,
1113         .tx_queue_stop        = enicpmd_dev_tx_queue_stop,
1114         .rx_queue_setup       = enicpmd_dev_rx_queue_setup,
1115         .rx_queue_release     = enicpmd_dev_rx_queue_release,
1116         .rx_queue_count       = enicpmd_dev_rx_queue_count,
1117         .rx_descriptor_done   = NULL,
1118         .tx_queue_setup       = enicpmd_dev_tx_queue_setup,
1119         .tx_queue_release     = enicpmd_dev_tx_queue_release,
1120         .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable,
1121         .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable,
1122         .rxq_info_get         = enicpmd_dev_rxq_info_get,
1123         .txq_info_get         = enicpmd_dev_txq_info_get,
1124         .dev_led_on           = NULL,
1125         .dev_led_off          = NULL,
1126         .flow_ctrl_get        = NULL,
1127         .flow_ctrl_set        = NULL,
1128         .priority_flow_ctrl_set = NULL,
1129         .mac_addr_add         = enicpmd_add_mac_addr,
1130         .mac_addr_remove      = enicpmd_remove_mac_addr,
1131         .mac_addr_set         = enicpmd_set_mac_addr,
1132         .set_mc_addr_list     = enicpmd_set_mc_addr_list,
1133         .filter_ctrl          = enicpmd_dev_filter_ctrl,
1134         .reta_query           = enicpmd_dev_rss_reta_query,
1135         .reta_update          = enicpmd_dev_rss_reta_update,
1136         .rss_hash_conf_get    = enicpmd_dev_rss_hash_conf_get,
1137         .rss_hash_update      = enicpmd_dev_rss_hash_update,
1138         .udp_tunnel_port_add  = enicpmd_dev_udp_tunnel_port_add,
1139         .udp_tunnel_port_del  = enicpmd_dev_udp_tunnel_port_del,
1140         .fw_version_get       = enicpmd_dev_fw_version_get,
1141 };
1142
1143 static int enic_parse_zero_one(const char *key,
1144                                const char *value,
1145                                void *opaque)
1146 {
1147         struct enic *enic;
1148         bool b;
1149
1150         enic = (struct enic *)opaque;
1151         if (strcmp(value, "0") == 0) {
1152                 b = false;
1153         } else if (strcmp(value, "1") == 0) {
1154                 b = true;
1155         } else {
1156                 dev_err(enic, "Invalid value for %s"
1157                         ": expected=0|1 given=%s\n", key, value);
1158                 return -EINVAL;
1159         }
1160         if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0)
1161                 enic->disable_overlay = b;
1162         if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0)
1163                 enic->enable_avx2_rx = b;
1164         if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0)
1165                 enic->geneve_opt_request = b;
1166         return 0;
1167 }
1168
1169 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key,
1170                                       const char *value,
1171                                       void *opaque)
1172 {
1173         struct enic *enic;
1174
1175         enic = (struct enic *)opaque;
1176         if (strcmp(value, "trunk") == 0) {
1177                 /* Trunk mode: always tag */
1178                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK;
1179         } else if (strcmp(value, "untag") == 0) {
1180                 /* Untag default VLAN mode: untag if VLAN = default VLAN */
1181                 enic->ig_vlan_rewrite_mode =
1182                         IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN;
1183         } else if (strcmp(value, "priority") == 0) {
1184                 /*
1185                  * Priority-tag default VLAN mode: priority tag (VLAN header
1186                  * with ID=0) if VLAN = default
1187                  */
1188                 enic->ig_vlan_rewrite_mode =
1189                         IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN;
1190         } else if (strcmp(value, "pass") == 0) {
1191                 /* Pass through mode: do not touch tags */
1192                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1193         } else {
1194                 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE
1195                         ": expected=trunk|untag|priority|pass given=%s\n",
1196                         value);
1197                 return -EINVAL;
1198         }
1199         return 0;
1200 }
1201
1202 static int enic_check_devargs(struct rte_eth_dev *dev)
1203 {
1204         static const char *const valid_keys[] = {
1205                 ENIC_DEVARG_DISABLE_OVERLAY,
1206                 ENIC_DEVARG_ENABLE_AVX2_RX,
1207                 ENIC_DEVARG_GENEVE_OPT,
1208                 ENIC_DEVARG_IG_VLAN_REWRITE,
1209                 NULL};
1210         struct enic *enic = pmd_priv(dev);
1211         struct rte_kvargs *kvlist;
1212
1213         ENICPMD_FUNC_TRACE();
1214
1215         enic->disable_overlay = false;
1216         enic->enable_avx2_rx = false;
1217         enic->geneve_opt_request = false;
1218         enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1219         if (!dev->device->devargs)
1220                 return 0;
1221         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1222         if (!kvlist)
1223                 return -EINVAL;
1224         if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY,
1225                                enic_parse_zero_one, enic) < 0 ||
1226             rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX,
1227                                enic_parse_zero_one, enic) < 0 ||
1228             rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT,
1229                                enic_parse_zero_one, enic) < 0 ||
1230             rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE,
1231                                enic_parse_ig_vlan_rewrite, enic) < 0) {
1232                 rte_kvargs_free(kvlist);
1233                 return -EINVAL;
1234         }
1235         rte_kvargs_free(kvlist);
1236         return 0;
1237 }
1238
1239 /* Initialize the driver
1240  * It returns 0 on success.
1241  */
1242 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev)
1243 {
1244         struct rte_pci_device *pdev;
1245         struct rte_pci_addr *addr;
1246         struct enic *enic = pmd_priv(eth_dev);
1247         int err;
1248
1249         ENICPMD_FUNC_TRACE();
1250
1251         eth_dev->dev_ops = &enicpmd_eth_dev_ops;
1252         eth_dev->rx_pkt_burst = &enic_recv_pkts;
1253         eth_dev->tx_pkt_burst = &enic_xmit_pkts;
1254         eth_dev->tx_pkt_prepare = &enic_prep_pkts;
1255         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1256                 enic_pick_tx_handler(eth_dev);
1257                 enic_pick_rx_handler(eth_dev);
1258                 return 0;
1259         }
1260         /* Only the primary sets up adapter and other data in shared memory */
1261         enic->port_id = eth_dev->data->port_id;
1262         enic->rte_dev = eth_dev;
1263         enic->dev_data = eth_dev->data;
1264         /* Let rte_eth_dev_close() release the port resources */
1265         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1266
1267         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
1268         rte_eth_copy_pci_info(eth_dev, pdev);
1269         enic->pdev = pdev;
1270         addr = &pdev->addr;
1271
1272         snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x",
1273                 addr->domain, addr->bus, addr->devid, addr->function);
1274
1275         err = enic_check_devargs(eth_dev);
1276         if (err)
1277                 return err;
1278         return enic_probe(enic);
1279 }
1280
1281 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1282         struct rte_pci_device *pci_dev)
1283 {
1284         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic),
1285                 eth_enicpmd_dev_init);
1286 }
1287
1288 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev)
1289 {
1290         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1291 }
1292
1293 static struct rte_pci_driver rte_enic_pmd = {
1294         .id_table = pci_id_enic_map,
1295         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1296         .probe = eth_enic_pci_probe,
1297         .remove = eth_enic_pci_remove,
1298 };
1299
1300 int dev_is_enic(struct rte_eth_dev *dev)
1301 {
1302         return dev->device->driver == &rte_enic_pmd.driver;
1303 }
1304
1305 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd);
1306 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map);
1307 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci");
1308 RTE_PMD_REGISTER_PARAM_STRING(net_enic,
1309         ENIC_DEVARG_DISABLE_OVERLAY "=0|1 "
1310         ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 "
1311         ENIC_DEVARG_GENEVE_OPT "=0|1 "
1312         ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass");