1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
11 #include <rte_bus_pci.h>
12 #include <ethdev_driver.h>
13 #include <ethdev_pci.h>
14 #include <rte_geneve.h>
15 #include <rte_kvargs.h>
16 #include <rte_string_fns.h>
18 #include "vnic_intr.h"
22 #include "vnic_enet.h"
26 * The set of PCI devices this driver supports
28 #define CISCO_PCI_VENDOR_ID 0x1137
29 static const struct rte_pci_id pci_id_enic_map[] = {
30 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)},
31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)},
32 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)},
33 {.vendor_id = 0, /* sentinel */},
36 /* Supported link speeds of production VIC models */
37 static const struct vic_speed_capa {
40 } vic_speed_capa_map[] = {
41 { 0x0043, RTE_ETH_LINK_SPEED_10G }, /* VIC */
42 { 0x0047, RTE_ETH_LINK_SPEED_10G }, /* P81E PCIe */
43 { 0x0048, RTE_ETH_LINK_SPEED_10G }, /* M81KR Mezz */
44 { 0x004f, RTE_ETH_LINK_SPEED_10G }, /* 1280 Mezz */
45 { 0x0084, RTE_ETH_LINK_SPEED_10G }, /* 1240 MLOM */
46 { 0x0085, RTE_ETH_LINK_SPEED_10G }, /* 1225 PCIe */
47 { 0x00cd, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1285 PCIe */
48 { 0x00ce, RTE_ETH_LINK_SPEED_10G }, /* 1225T PCIe */
49 { 0x012a, RTE_ETH_LINK_SPEED_40G }, /* M4308 */
50 { 0x012c, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1340 MLOM */
51 { 0x012e, RTE_ETH_LINK_SPEED_10G }, /* 1227 PCIe */
52 { 0x0137, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1380 Mezz */
53 { 0x014d, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1385 PCIe */
54 { 0x015d, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1387 MLOM */
55 { 0x0215, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G |
56 RTE_ETH_LINK_SPEED_40G }, /* 1440 Mezz */
57 { 0x0216, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G |
58 RTE_ETH_LINK_SPEED_40G }, /* 1480 MLOM */
59 { 0x0217, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1455 PCIe */
60 { 0x0218, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1457 MLOM */
61 { 0x0219, RTE_ETH_LINK_SPEED_40G }, /* 1485 PCIe */
62 { 0x021a, RTE_ETH_LINK_SPEED_40G }, /* 1487 MLOM */
63 { 0x024a, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1495 PCIe */
64 { 0x024b, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1497 MLOM */
65 { 0, 0 }, /* End marker */
68 #define ENIC_DEVARG_CQ64 "cq64"
69 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
70 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx"
71 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite"
72 #define ENIC_DEVARG_REPRESENTOR "representor"
74 RTE_LOG_REGISTER_DEFAULT(enic_pmd_logtype, INFO);
77 enicpmd_dev_flow_ops_get(struct rte_eth_dev *dev,
78 const struct rte_flow_ops **ops)
80 struct enic *enic = pmd_priv(dev);
84 if (enic->flow_filter_mode == FILTER_FLOWMAN)
85 *ops = &enic_fm_flow_ops;
87 *ops = &enic_flow_ops;
91 static void enicpmd_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
93 void *txq = dev->data->tx_queues[qid];
97 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
103 static int enicpmd_dev_setup_intr(struct enic *enic)
108 ENICPMD_FUNC_TRACE();
110 /* Are we done with the init of all the queues? */
111 for (index = 0; index < enic->cq_count; index++) {
112 if (!enic->cq[index].ctrl)
115 if (enic->cq_count != index)
117 for (index = 0; index < enic->wq_count; index++) {
118 if (!enic->wq[index].ctrl)
121 if (enic->wq_count != index)
123 /* check start of packet (SOP) RQs only in case scatter is disabled. */
124 for (index = 0; index < enic->rq_count; index++) {
125 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl)
128 if (enic->rq_count != index)
131 ret = enic_alloc_intr_resources(enic);
133 dev_err(enic, "alloc intr failed\n");
136 enic_init_vnic_resources(enic);
138 ret = enic_setup_finish(enic);
140 dev_err(enic, "setup could not be finished\n");
145 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
148 unsigned int socket_id,
149 const struct rte_eth_txconf *tx_conf)
152 struct enic *enic = pmd_priv(eth_dev);
155 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
156 return -E_RTE_SECONDARY;
158 ENICPMD_FUNC_TRACE();
159 RTE_ASSERT(queue_idx < enic->conf_wq_count);
160 wq = &enic->wq[queue_idx];
161 wq->offloads = tx_conf->offloads |
162 eth_dev->data->dev_conf.txmode.offloads;
163 eth_dev->data->tx_queues[queue_idx] = (void *)wq;
165 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc);
167 dev_err(enic, "error in allocating wq\n");
171 return enicpmd_dev_setup_intr(enic);
174 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
177 struct enic *enic = pmd_priv(eth_dev);
179 ENICPMD_FUNC_TRACE();
181 enic_start_wq(enic, queue_idx);
186 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
190 struct enic *enic = pmd_priv(eth_dev);
192 ENICPMD_FUNC_TRACE();
194 ret = enic_stop_wq(enic, queue_idx);
196 dev_err(enic, "error in stopping wq %d\n", queue_idx);
201 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
204 struct enic *enic = pmd_priv(eth_dev);
206 ENICPMD_FUNC_TRACE();
208 enic_start_rq(enic, queue_idx);
213 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
217 struct enic *enic = pmd_priv(eth_dev);
219 ENICPMD_FUNC_TRACE();
221 ret = enic_stop_rq(enic, queue_idx);
223 dev_err(enic, "error in stopping rq %d\n", queue_idx);
228 static void enicpmd_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
230 void *rxq = dev->data->rx_queues[qid];
232 ENICPMD_FUNC_TRACE();
234 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
240 static uint32_t enicpmd_dev_rx_queue_count(void *rx_queue)
243 struct vnic_rq *sop_rq;
244 uint32_t queue_count = 0;
250 enic = vnic_dev_priv(sop_rq->vdev);
251 cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
252 cq_idx = cq->to_clean;
254 cq_tail = ioread32(&cq->ctrl->cq_tail);
256 if (cq_tail < cq_idx)
257 cq_tail += cq->ring.desc_count;
259 queue_count = cq_tail - cq_idx;
264 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
267 unsigned int socket_id,
268 const struct rte_eth_rxconf *rx_conf,
269 struct rte_mempool *mp)
272 struct enic *enic = pmd_priv(eth_dev);
274 ENICPMD_FUNC_TRACE();
276 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
277 return -E_RTE_SECONDARY;
278 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count);
279 eth_dev->data->rx_queues[queue_idx] =
280 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)];
282 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc,
283 rx_conf->rx_free_thresh);
285 dev_err(enic, "error in allocating rq\n");
289 return enicpmd_dev_setup_intr(enic);
292 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
294 struct enic *enic = pmd_priv(eth_dev);
297 ENICPMD_FUNC_TRACE();
299 offloads = eth_dev->data->dev_conf.rxmode.offloads;
300 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
301 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
302 enic->ig_vlan_strip_en = 1;
304 enic->ig_vlan_strip_en = 0;
307 return enic_set_vlan_strip(enic);
310 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev)
314 struct enic *enic = pmd_priv(eth_dev);
316 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
317 return -E_RTE_SECONDARY;
319 ENICPMD_FUNC_TRACE();
320 ret = enic_set_vnic_res(enic);
322 dev_err(enic, "Set vNIC resource num failed, aborting\n");
326 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
327 eth_dev->data->dev_conf.rxmode.offloads |=
328 RTE_ETH_RX_OFFLOAD_RSS_HASH;
331 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads &
332 RTE_ETH_RX_OFFLOAD_CHECKSUM);
333 /* All vlan offload masks to apply the current settings */
334 mask = RTE_ETH_VLAN_STRIP_MASK |
335 RTE_ETH_VLAN_FILTER_MASK |
336 RTE_ETH_VLAN_EXTEND_MASK;
337 ret = enicpmd_vlan_offload_set(eth_dev, mask);
339 dev_err(enic, "Failed to configure VLAN offloads\n");
343 * Initialize RSS with the default reta and key. If the user key is
344 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the
347 return enic_init_rss_nic_cfg(enic);
351 * It returns 0 on success.
353 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev)
355 struct enic *enic = pmd_priv(eth_dev);
357 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
358 return -E_RTE_SECONDARY;
360 ENICPMD_FUNC_TRACE();
361 return enic_enable(enic);
365 * Stop device: disable rx and tx functions to allow for reconfiguring.
367 static int enicpmd_dev_stop(struct rte_eth_dev *eth_dev)
369 struct rte_eth_link link;
370 struct enic *enic = pmd_priv(eth_dev);
372 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
375 ENICPMD_FUNC_TRACE();
378 memset(&link, 0, sizeof(link));
379 rte_eth_linkstatus_set(eth_dev, &link);
387 static int enicpmd_dev_close(struct rte_eth_dev *eth_dev)
389 struct enic *enic = pmd_priv(eth_dev);
391 ENICPMD_FUNC_TRACE();
392 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
400 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,
401 __rte_unused int wait_to_complete)
403 ENICPMD_FUNC_TRACE();
404 return enic_link_update(eth_dev);
407 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,
408 struct rte_eth_stats *stats)
410 struct enic *enic = pmd_priv(eth_dev);
412 ENICPMD_FUNC_TRACE();
413 return enic_dev_stats_get(enic, stats);
416 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)
418 struct enic *enic = pmd_priv(eth_dev);
420 ENICPMD_FUNC_TRACE();
421 return enic_dev_stats_clear(enic);
424 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev)
426 const struct vic_speed_capa *m;
427 struct rte_pci_device *pdev;
430 pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
431 id = pdev->id.subsystem_device_id;
432 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) {
433 if (m->sub_devid == id)
436 /* 1300 and later models are at least 40G */
438 return RTE_ETH_LINK_SPEED_40G;
439 /* VFs have subsystem id 0, check device id */
441 /* Newer VF implies at least 40G model */
442 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN)
443 return RTE_ETH_LINK_SPEED_40G;
445 return RTE_ETH_LINK_SPEED_10G;
448 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
449 struct rte_eth_dev_info *device_info)
451 struct enic *enic = pmd_priv(eth_dev);
453 ENICPMD_FUNC_TRACE();
454 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */
455 device_info->max_rx_queues = enic->conf_rq_count / 2;
456 device_info->max_tx_queues = enic->conf_wq_count;
457 device_info->min_rx_bufsize = ENIC_MIN_MTU;
458 /* "Max" mtu is not a typo. HW receives packet sizes up to the
459 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is
460 * a hint to the driver to size receive buffers accordingly so that
461 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let
462 * the user decide the buffer size via rxmode.mtu, basically
465 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu);
466 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS;
467 device_info->min_mtu = ENIC_MIN_MTU;
468 device_info->max_mtu = enic->max_mtu;
469 device_info->rx_offload_capa = enic->rx_offload_capa;
470 device_info->tx_offload_capa = enic->tx_offload_capa;
471 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa;
472 device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
473 device_info->default_rxconf = (struct rte_eth_rxconf) {
474 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH
476 device_info->reta_size = enic->reta_size;
477 device_info->hash_key_size = enic->hash_key_size;
478 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads;
479 device_info->rx_desc_lim = (struct rte_eth_desc_lim) {
480 .nb_max = enic->config.rq_desc_count,
481 .nb_min = ENIC_MIN_RQ_DESCS,
482 .nb_align = ENIC_ALIGN_DESCS,
484 device_info->tx_desc_lim = (struct rte_eth_desc_lim) {
485 .nb_max = enic->config.wq_desc_count,
486 .nb_min = ENIC_MIN_WQ_DESCS,
487 .nb_align = ENIC_ALIGN_DESCS,
488 .nb_seg_max = ENIC_TX_XMIT_MAX,
489 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC,
491 device_info->default_rxportconf = (struct rte_eth_dev_portconf) {
492 .burst_size = ENIC_DEFAULT_RX_BURST,
493 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max,
494 ENIC_DEFAULT_RX_RING_SIZE),
495 .nb_queues = ENIC_DEFAULT_RX_RINGS,
497 device_info->default_txportconf = (struct rte_eth_dev_portconf) {
498 .burst_size = ENIC_DEFAULT_TX_BURST,
499 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max,
500 ENIC_DEFAULT_TX_RING_SIZE),
501 .nb_queues = ENIC_DEFAULT_TX_RINGS,
503 device_info->speed_capa = speed_capa_from_pci_id(eth_dev);
508 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev)
510 static const uint32_t ptypes[] = {
512 RTE_PTYPE_L2_ETHER_VLAN,
513 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
514 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
518 RTE_PTYPE_L4_NONFRAG,
521 static const uint32_t ptypes_overlay[] = {
523 RTE_PTYPE_L2_ETHER_VLAN,
524 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
525 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
529 RTE_PTYPE_L4_NONFRAG,
530 RTE_PTYPE_TUNNEL_GRENAT,
531 RTE_PTYPE_INNER_L2_ETHER,
532 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
533 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
534 RTE_PTYPE_INNER_L4_TCP,
535 RTE_PTYPE_INNER_L4_UDP,
536 RTE_PTYPE_INNER_L4_FRAG,
537 RTE_PTYPE_INNER_L4_NONFRAG,
541 if (dev->rx_pkt_burst != rte_eth_pkt_burst_dummy &&
542 dev->rx_pkt_burst != NULL) {
543 struct enic *enic = pmd_priv(dev);
544 if (enic->overlay_offload)
545 return ptypes_overlay;
552 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
554 struct enic *enic = pmd_priv(eth_dev);
557 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
558 return -E_RTE_SECONDARY;
560 ENICPMD_FUNC_TRACE();
563 ret = enic_add_packet_filter(enic);
570 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
572 struct enic *enic = pmd_priv(eth_dev);
575 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
576 return -E_RTE_SECONDARY;
578 ENICPMD_FUNC_TRACE();
580 ret = enic_add_packet_filter(enic);
587 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
589 struct enic *enic = pmd_priv(eth_dev);
592 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
593 return -E_RTE_SECONDARY;
595 ENICPMD_FUNC_TRACE();
597 ret = enic_add_packet_filter(enic);
604 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
606 struct enic *enic = pmd_priv(eth_dev);
609 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
610 return -E_RTE_SECONDARY;
612 ENICPMD_FUNC_TRACE();
614 ret = enic_add_packet_filter(enic);
621 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev,
622 struct rte_ether_addr *mac_addr,
623 __rte_unused uint32_t index, __rte_unused uint32_t pool)
625 struct enic *enic = pmd_priv(eth_dev);
627 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
628 return -E_RTE_SECONDARY;
630 ENICPMD_FUNC_TRACE();
631 return enic_set_mac_address(enic, mac_addr->addr_bytes);
634 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index)
636 struct enic *enic = pmd_priv(eth_dev);
638 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
641 ENICPMD_FUNC_TRACE();
642 if (enic_del_mac_address(enic, index))
643 dev_err(enic, "del mac addr failed\n");
646 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev,
647 struct rte_ether_addr *addr)
649 struct enic *enic = pmd_priv(eth_dev);
652 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
653 return -E_RTE_SECONDARY;
655 ENICPMD_FUNC_TRACE();
656 ret = enic_del_mac_address(enic, 0);
659 return enic_set_mac_address(enic, addr->addr_bytes);
662 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add)
664 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
666 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
667 ENICPMD_LOG(DEBUG, " %s address %s\n",
668 add ? "add" : "remove", mac_str);
671 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev,
672 struct rte_ether_addr *mc_addr_set,
675 struct enic *enic = pmd_priv(eth_dev);
676 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
677 struct rte_ether_addr *addr;
681 ENICPMD_FUNC_TRACE();
683 /* Validate the given addresses first */
684 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) {
685 addr = &mc_addr_set[i];
686 if (!rte_is_multicast_ether_addr(addr) ||
687 rte_is_broadcast_ether_addr(addr)) {
688 rte_ether_format_addr(mac_str,
689 RTE_ETHER_ADDR_FMT_SIZE, addr);
690 ENICPMD_LOG(ERR, " invalid multicast address %s\n",
696 /* Flush all if requested */
697 if (nb_mc_addr == 0 || mc_addr_set == NULL) {
698 ENICPMD_LOG(DEBUG, " flush multicast addresses\n");
699 for (i = 0; i < enic->mc_count; i++) {
700 addr = &enic->mc_addrs[i];
701 debug_log_add_del_addr(addr, false);
702 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
710 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) {
711 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n",
712 ENIC_MULTICAST_PERFECT_FILTERS);
716 * devcmd is slow, so apply the difference instead of flushing and
718 * 1. Delete addresses on the NIC but not on the host
720 for (i = 0; i < enic->mc_count; i++) {
721 addr = &enic->mc_addrs[i];
722 for (j = 0; j < nb_mc_addr; j++) {
723 if (rte_is_same_ether_addr(addr, &mc_addr_set[j]))
728 debug_log_add_del_addr(addr, false);
729 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
733 /* 2. Add addresses on the host but not on the NIC */
734 for (i = 0; i < nb_mc_addr; i++) {
735 addr = &mc_addr_set[i];
736 for (j = 0; j < enic->mc_count; j++) {
737 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j]))
740 if (j < enic->mc_count)
742 debug_log_add_del_addr(addr, true);
743 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes);
747 /* Keep a copy so we can flush/apply later on.. */
748 memcpy(enic->mc_addrs, mc_addr_set,
749 nb_mc_addr * sizeof(struct rte_ether_addr));
750 enic->mc_count = nb_mc_addr;
754 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
756 struct enic *enic = pmd_priv(eth_dev);
758 ENICPMD_FUNC_TRACE();
759 return enic_set_mtu(enic, mtu);
762 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev,
763 struct rte_eth_rss_reta_entry64
767 struct enic *enic = pmd_priv(dev);
768 uint16_t i, idx, shift;
770 ENICPMD_FUNC_TRACE();
771 if (reta_size != ENIC_RSS_RETA_SIZE) {
772 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n",
773 reta_size, ENIC_RSS_RETA_SIZE);
777 for (i = 0; i < reta_size; i++) {
778 idx = i / RTE_ETH_RETA_GROUP_SIZE;
779 shift = i % RTE_ETH_RETA_GROUP_SIZE;
780 if (reta_conf[idx].mask & (1ULL << shift))
781 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx(
782 enic->rss_cpu.cpu[i / 4].b[i % 4]);
788 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev,
789 struct rte_eth_rss_reta_entry64
793 struct enic *enic = pmd_priv(dev);
794 union vnic_rss_cpu rss_cpu;
795 uint16_t i, idx, shift;
797 ENICPMD_FUNC_TRACE();
798 if (reta_size != ENIC_RSS_RETA_SIZE) {
799 dev_err(enic, "reta_update: wrong reta_size. given=%u"
801 reta_size, ENIC_RSS_RETA_SIZE);
805 * Start with the current reta and modify it per reta_conf, as we
806 * need to push the entire reta even if we only modify one entry.
808 rss_cpu = enic->rss_cpu;
809 for (i = 0; i < reta_size; i++) {
810 idx = i / RTE_ETH_RETA_GROUP_SIZE;
811 shift = i % RTE_ETH_RETA_GROUP_SIZE;
812 if (reta_conf[idx].mask & (1ULL << shift))
813 rss_cpu.cpu[i / 4].b[i % 4] =
814 enic_rte_rq_idx_to_sop_idx(
815 reta_conf[idx].reta[shift]);
817 return enic_set_rss_reta(enic, &rss_cpu);
820 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev,
821 struct rte_eth_rss_conf *rss_conf)
823 struct enic *enic = pmd_priv(dev);
825 ENICPMD_FUNC_TRACE();
826 return enic_set_rss_conf(enic, rss_conf);
829 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
830 struct rte_eth_rss_conf *rss_conf)
832 struct enic *enic = pmd_priv(dev);
834 ENICPMD_FUNC_TRACE();
835 if (rss_conf == NULL)
837 if (rss_conf->rss_key != NULL &&
838 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) {
839 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u"
841 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE);
844 rss_conf->rss_hf = enic->rss_hf;
845 if (rss_conf->rss_key != NULL) {
847 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) {
848 rss_conf->rss_key[i] =
849 enic->rss_key.key[i / 10].b[i % 10];
851 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE;
856 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev,
857 uint16_t rx_queue_id,
858 struct rte_eth_rxq_info *qinfo)
860 struct enic *enic = pmd_priv(dev);
861 struct vnic_rq *rq_sop;
862 struct vnic_rq *rq_data;
863 struct rte_eth_rxconf *conf;
864 uint16_t sop_queue_idx;
865 uint16_t data_queue_idx;
867 ENICPMD_FUNC_TRACE();
868 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
869 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic);
870 rq_sop = &enic->rq[sop_queue_idx];
871 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */
872 qinfo->mp = rq_sop->mp;
873 qinfo->scattered_rx = rq_sop->data_queue_enable;
874 qinfo->nb_desc = rq_sop->ring.desc_count;
875 if (qinfo->scattered_rx)
876 qinfo->nb_desc += rq_data->ring.desc_count;
878 memset(conf, 0, sizeof(*conf));
879 conf->rx_free_thresh = rq_sop->rx_free_thresh;
880 conf->rx_drop_en = 1;
882 * Except VLAN stripping (port setting), all the checksum offloads
883 * are always enabled.
885 conf->offloads = enic->rx_offload_capa;
886 if (!enic->ig_vlan_strip_en)
887 conf->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
888 /* rx_thresh and other fields are not applicable for enic */
891 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev,
892 uint16_t tx_queue_id,
893 struct rte_eth_txq_info *qinfo)
895 struct enic *enic = pmd_priv(dev);
896 struct vnic_wq *wq = &enic->wq[tx_queue_id];
898 ENICPMD_FUNC_TRACE();
899 qinfo->nb_desc = wq->ring.desc_count;
900 memset(&qinfo->conf, 0, sizeof(qinfo->conf));
901 qinfo->conf.offloads = wq->offloads;
902 /* tx_thresh, and all the other fields are not applicable for enic */
905 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
906 __rte_unused uint16_t queue_id,
907 struct rte_eth_burst_mode *mode)
909 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
910 struct enic *enic = pmd_priv(dev);
911 const char *info_str = NULL;
914 ENICPMD_FUNC_TRACE();
915 if (enic->use_noscatter_vec_rx_handler)
916 info_str = "Vector AVX2 No Scatter";
917 else if (pkt_burst == enic_noscatter_recv_pkts)
918 info_str = "Scalar No Scatter";
919 else if (pkt_burst == enic_recv_pkts)
921 else if (pkt_burst == enic_recv_pkts_64)
922 info_str = "Scalar 64B Completion";
924 strlcpy(mode->info, info_str, sizeof(mode->info));
930 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
931 __rte_unused uint16_t queue_id,
932 struct rte_eth_burst_mode *mode)
934 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
935 const char *info_str = NULL;
938 ENICPMD_FUNC_TRACE();
939 if (pkt_burst == enic_simple_xmit_pkts)
940 info_str = "Scalar Simplified";
941 else if (pkt_burst == enic_xmit_pkts)
944 strlcpy(mode->info, info_str, sizeof(mode->info));
950 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
951 uint16_t rx_queue_id)
953 struct enic *enic = pmd_priv(eth_dev);
955 ENICPMD_FUNC_TRACE();
956 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
960 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
961 uint16_t rx_queue_id)
963 struct enic *enic = pmd_priv(eth_dev);
965 ENICPMD_FUNC_TRACE();
966 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
970 static int udp_tunnel_common_check(struct enic *enic,
971 struct rte_eth_udp_tunnel *tnl)
973 if (tnl->prot_type != RTE_ETH_TUNNEL_TYPE_VXLAN &&
974 tnl->prot_type != RTE_ETH_TUNNEL_TYPE_GENEVE)
976 if (!enic->overlay_offload) {
977 ENICPMD_LOG(DEBUG, " overlay offload is not supported\n");
983 static int update_tunnel_port(struct enic *enic, uint16_t port, bool vxlan)
987 cfg = vxlan ? OVERLAY_CFG_VXLAN_PORT_UPDATE :
988 OVERLAY_CFG_GENEVE_PORT_UPDATE;
989 if (vnic_dev_overlay_offload_cfg(enic->vdev, cfg, port)) {
990 ENICPMD_LOG(DEBUG, " failed to update tunnel port\n");
993 ENICPMD_LOG(DEBUG, " updated %s port to %u\n",
994 vxlan ? "vxlan" : "geneve", port);
996 enic->vxlan_port = port;
998 enic->geneve_port = port;
1002 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev,
1003 struct rte_eth_udp_tunnel *tnl)
1005 struct enic *enic = pmd_priv(eth_dev);
1010 ENICPMD_FUNC_TRACE();
1011 ret = udp_tunnel_common_check(enic, tnl);
1014 vxlan = (tnl->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN);
1016 port = enic->vxlan_port;
1018 port = enic->geneve_port;
1020 * The NIC has 1 configurable port number per tunnel type.
1021 * "Adding" a new port number replaces it.
1023 if (tnl->udp_port == port || tnl->udp_port == 0) {
1024 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n",
1028 return update_tunnel_port(enic, tnl->udp_port, vxlan);
1031 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev,
1032 struct rte_eth_udp_tunnel *tnl)
1034 struct enic *enic = pmd_priv(eth_dev);
1039 ENICPMD_FUNC_TRACE();
1040 ret = udp_tunnel_common_check(enic, tnl);
1043 vxlan = (tnl->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN);
1045 port = enic->vxlan_port;
1047 port = enic->geneve_port;
1049 * Clear the previously set port number and restore the
1050 * hardware default port number. Some drivers disable VXLAN
1051 * offloads when there are no configured port numbers. But
1052 * enic does not do that as VXLAN is part of overlay offload,
1053 * which is tied to inner RSS and TSO.
1055 if (tnl->udp_port != port) {
1056 ENICPMD_LOG(DEBUG, " %u is not a configured tunnel port\n",
1060 port = vxlan ? RTE_VXLAN_DEFAULT_PORT : RTE_GENEVE_DEFAULT_PORT;
1061 return update_tunnel_port(enic, port, vxlan);
1064 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev,
1065 char *fw_version, size_t fw_size)
1067 struct vnic_devcmd_fw_info *info;
1071 ENICPMD_FUNC_TRACE();
1073 enic = pmd_priv(eth_dev);
1074 ret = vnic_dev_fw_info(enic->vdev, &info);
1077 ret = snprintf(fw_version, fw_size, "%s %s",
1078 info->fw_version, info->fw_build);
1082 ret += 1; /* add the size of '\0' */
1083 if (fw_size < (size_t)ret)
1089 static const struct eth_dev_ops enicpmd_eth_dev_ops = {
1090 .dev_configure = enicpmd_dev_configure,
1091 .dev_start = enicpmd_dev_start,
1092 .dev_stop = enicpmd_dev_stop,
1093 .dev_set_link_up = NULL,
1094 .dev_set_link_down = NULL,
1095 .dev_close = enicpmd_dev_close,
1096 .promiscuous_enable = enicpmd_dev_promiscuous_enable,
1097 .promiscuous_disable = enicpmd_dev_promiscuous_disable,
1098 .allmulticast_enable = enicpmd_dev_allmulticast_enable,
1099 .allmulticast_disable = enicpmd_dev_allmulticast_disable,
1100 .link_update = enicpmd_dev_link_update,
1101 .stats_get = enicpmd_dev_stats_get,
1102 .stats_reset = enicpmd_dev_stats_reset,
1103 .queue_stats_mapping_set = NULL,
1104 .dev_infos_get = enicpmd_dev_info_get,
1105 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get,
1106 .mtu_set = enicpmd_mtu_set,
1107 .vlan_filter_set = NULL,
1108 .vlan_tpid_set = NULL,
1109 .vlan_offload_set = enicpmd_vlan_offload_set,
1110 .vlan_strip_queue_set = NULL,
1111 .rx_queue_start = enicpmd_dev_rx_queue_start,
1112 .rx_queue_stop = enicpmd_dev_rx_queue_stop,
1113 .tx_queue_start = enicpmd_dev_tx_queue_start,
1114 .tx_queue_stop = enicpmd_dev_tx_queue_stop,
1115 .rx_queue_setup = enicpmd_dev_rx_queue_setup,
1116 .rx_queue_release = enicpmd_dev_rx_queue_release,
1117 .tx_queue_setup = enicpmd_dev_tx_queue_setup,
1118 .tx_queue_release = enicpmd_dev_tx_queue_release,
1119 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable,
1120 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable,
1121 .rxq_info_get = enicpmd_dev_rxq_info_get,
1122 .txq_info_get = enicpmd_dev_txq_info_get,
1123 .rx_burst_mode_get = enicpmd_dev_rx_burst_mode_get,
1124 .tx_burst_mode_get = enicpmd_dev_tx_burst_mode_get,
1126 .dev_led_off = NULL,
1127 .flow_ctrl_get = NULL,
1128 .flow_ctrl_set = NULL,
1129 .priority_flow_ctrl_set = NULL,
1130 .mac_addr_add = enicpmd_add_mac_addr,
1131 .mac_addr_remove = enicpmd_remove_mac_addr,
1132 .mac_addr_set = enicpmd_set_mac_addr,
1133 .set_mc_addr_list = enicpmd_set_mc_addr_list,
1134 .flow_ops_get = enicpmd_dev_flow_ops_get,
1135 .reta_query = enicpmd_dev_rss_reta_query,
1136 .reta_update = enicpmd_dev_rss_reta_update,
1137 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get,
1138 .rss_hash_update = enicpmd_dev_rss_hash_update,
1139 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add,
1140 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del,
1141 .fw_version_get = enicpmd_dev_fw_version_get,
1144 static int enic_parse_zero_one(const char *key,
1151 enic = (struct enic *)opaque;
1152 if (strcmp(value, "0") == 0) {
1154 } else if (strcmp(value, "1") == 0) {
1157 dev_err(enic, "Invalid value for %s"
1158 ": expected=0|1 given=%s\n", key, value);
1161 if (strcmp(key, ENIC_DEVARG_CQ64) == 0)
1162 enic->cq64_request = b;
1163 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0)
1164 enic->disable_overlay = b;
1165 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0)
1166 enic->enable_avx2_rx = b;
1170 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key,
1176 enic = (struct enic *)opaque;
1177 if (strcmp(value, "trunk") == 0) {
1178 /* Trunk mode: always tag */
1179 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK;
1180 } else if (strcmp(value, "untag") == 0) {
1181 /* Untag default VLAN mode: untag if VLAN = default VLAN */
1182 enic->ig_vlan_rewrite_mode =
1183 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN;
1184 } else if (strcmp(value, "priority") == 0) {
1186 * Priority-tag default VLAN mode: priority tag (VLAN header
1187 * with ID=0) if VLAN = default
1189 enic->ig_vlan_rewrite_mode =
1190 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN;
1191 } else if (strcmp(value, "pass") == 0) {
1192 /* Pass through mode: do not touch tags */
1193 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1195 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE
1196 ": expected=trunk|untag|priority|pass given=%s\n",
1203 static int enic_check_devargs(struct rte_eth_dev *dev)
1205 static const char *const valid_keys[] = {
1207 ENIC_DEVARG_DISABLE_OVERLAY,
1208 ENIC_DEVARG_ENABLE_AVX2_RX,
1209 ENIC_DEVARG_IG_VLAN_REWRITE,
1210 ENIC_DEVARG_REPRESENTOR,
1212 struct enic *enic = pmd_priv(dev);
1213 struct rte_kvargs *kvlist;
1215 ENICPMD_FUNC_TRACE();
1217 enic->cq64_request = true; /* Use 64B entry if available */
1218 enic->disable_overlay = false;
1219 enic->enable_avx2_rx = false;
1220 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1221 if (!dev->device->devargs)
1223 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1226 if (rte_kvargs_process(kvlist, ENIC_DEVARG_CQ64,
1227 enic_parse_zero_one, enic) < 0 ||
1228 rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY,
1229 enic_parse_zero_one, enic) < 0 ||
1230 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX,
1231 enic_parse_zero_one, enic) < 0 ||
1232 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE,
1233 enic_parse_ig_vlan_rewrite, enic) < 0) {
1234 rte_kvargs_free(kvlist);
1237 rte_kvargs_free(kvlist);
1241 /* Initialize the driver for PF */
1242 static int eth_enic_dev_init(struct rte_eth_dev *eth_dev,
1243 void *init_params __rte_unused)
1245 struct rte_pci_device *pdev;
1246 struct rte_pci_addr *addr;
1247 struct enic *enic = pmd_priv(eth_dev);
1250 ENICPMD_FUNC_TRACE();
1251 eth_dev->dev_ops = &enicpmd_eth_dev_ops;
1252 eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count;
1253 eth_dev->rx_pkt_burst = &enic_recv_pkts;
1254 eth_dev->tx_pkt_burst = &enic_xmit_pkts;
1255 eth_dev->tx_pkt_prepare = &enic_prep_pkts;
1256 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1257 enic_pick_tx_handler(eth_dev);
1258 enic_pick_rx_handler(eth_dev);
1261 /* Only the primary sets up adapter and other data in shared memory */
1262 enic->port_id = eth_dev->data->port_id;
1263 enic->rte_dev = eth_dev;
1264 enic->dev_data = eth_dev->data;
1266 pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
1267 rte_eth_copy_pci_info(eth_dev, pdev);
1271 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x",
1272 addr->domain, addr->bus, addr->devid, addr->function);
1274 err = enic_check_devargs(eth_dev);
1277 err = enic_probe(enic);
1278 if (!err && enic->fm) {
1279 err = enic_fm_allocate_switch_domain(enic);
1281 ENICPMD_LOG(ERR, "failed to allocate switch domain id");
1286 static int eth_enic_dev_uninit(struct rte_eth_dev *eth_dev)
1288 struct enic *enic = pmd_priv(eth_dev);
1291 ENICPMD_FUNC_TRACE();
1292 eth_dev->device = NULL;
1293 eth_dev->intr_handle = NULL;
1294 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1296 err = rte_eth_switch_domain_free(enic->switch_domain_id);
1298 ENICPMD_LOG(WARNING, "failed to free switch domain: %d", err);
1302 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1303 struct rte_pci_device *pci_dev)
1305 char name[RTE_ETH_NAME_MAX_LEN];
1306 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
1307 struct rte_eth_dev *pf_ethdev;
1308 struct enic *pf_enic;
1311 ENICPMD_FUNC_TRACE();
1312 if (pci_dev->device.devargs) {
1313 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1318 if (eth_da.nb_representor_ports > 0 &&
1319 eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1320 ENICPMD_LOG(ERR, "unsupported representor type: %s\n",
1321 pci_dev->device.devargs->args);
1324 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1325 sizeof(struct enic),
1326 eth_dev_pci_specific_init, pci_dev,
1327 eth_enic_dev_init, NULL);
1328 if (retval || eth_da.nb_representor_ports < 1)
1331 /* Probe VF representor */
1332 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1333 if (pf_ethdev == NULL)
1335 /* Representors require flowman */
1336 pf_enic = pmd_priv(pf_ethdev);
1337 if (pf_enic->fm == NULL) {
1338 ENICPMD_LOG(ERR, "VF representors require flowman");
1342 * For now representors imply switchdev, as firmware does not support
1343 * legacy mode SR-IOV
1345 pf_enic->switchdev_mode = 1;
1346 /* Calculate max VF ID before initializing representor*/
1347 pf_enic->max_vf_id = 0;
1348 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1349 pf_enic->max_vf_id = RTE_MAX(pf_enic->max_vf_id,
1350 eth_da.representor_ports[i]);
1352 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1353 struct enic_vf_representor representor;
1355 representor.vf_id = eth_da.representor_ports[i];
1356 representor.switch_domain_id =
1357 pmd_priv(pf_ethdev)->switch_domain_id;
1358 representor.pf = pmd_priv(pf_ethdev);
1359 snprintf(name, sizeof(name), "net_%s_representor_%d",
1360 pci_dev->device.name, eth_da.representor_ports[i]);
1361 retval = rte_eth_dev_create(&pci_dev->device, name,
1362 sizeof(struct enic_vf_representor), NULL, NULL,
1363 enic_vf_representor_init, &representor);
1365 ENICPMD_LOG(ERR, "failed to create enic vf representor %s",
1373 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev)
1375 struct rte_eth_dev *ethdev;
1377 ENICPMD_FUNC_TRACE();
1378 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1381 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1382 return rte_eth_dev_destroy(ethdev, enic_vf_representor_uninit);
1384 return rte_eth_dev_destroy(ethdev, eth_enic_dev_uninit);
1387 static struct rte_pci_driver rte_enic_pmd = {
1388 .id_table = pci_id_enic_map,
1389 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1390 .probe = eth_enic_pci_probe,
1391 .remove = eth_enic_pci_remove,
1394 int dev_is_enic(struct rte_eth_dev *dev)
1396 return dev->device->driver == &rte_enic_pmd.driver;
1399 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd);
1400 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map);
1401 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci");
1402 RTE_PMD_REGISTER_PARAM_STRING(net_enic,
1403 ENIC_DEVARG_CQ64 "=0|1"
1404 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 "
1405 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 "
1406 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass");