drivers/net/enic/enic_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  */
   5
   6 #include <stdio.h>
   7 #include <stdint.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_pci.h>
  11 #include <rte_bus_pci.h>
  12 #include <ethdev_driver.h>
  13 #include <ethdev_pci.h>
  14 #include <rte_kvargs.h>
  15 #include <rte_string_fns.h>
  16
  17 #include "vnic_intr.h"
  18 #include "vnic_cq.h"
  19 #include "vnic_wq.h"
  20 #include "vnic_rq.h"
  21 #include "vnic_enet.h"
  22 #include "enic.h"
  23
  24 /*
  25  * The set of PCI devices this driver supports
  26  */
  27 #define CISCO_PCI_VENDOR_ID 0x1137
  28 static const struct rte_pci_id pci_id_enic_map[] = {
  29         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)},
  30         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)},
  31         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)},
  32         {.vendor_id = 0, /* sentinel */},
  33 };
  34
  35 /* Supported link speeds of production VIC models */
  36 static const struct vic_speed_capa {
  37         uint16_t sub_devid;
  38         uint32_t capa;
  39 } vic_speed_capa_map[] = {
  40         { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */
  41         { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */
  42         { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */
  43         { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */
  44         { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */
  45         { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */
  46         { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */
  47         { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */
  48         { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */
  49         { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */
  50         { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */
  51         { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */
  52         { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */
  53         { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */
  54         { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  55                   ETH_LINK_SPEED_40G }, /* 1440 Mezz */
  56         { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  57                   ETH_LINK_SPEED_40G }, /* 1480 MLOM */
  58         { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */
  59         { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */
  60         { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */
  61         { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */
  62         { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */
  63         { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */
  64         { 0, 0 }, /* End marker */
  65 };
  66
  67 #define ENIC_DEVARG_CQ64 "cq64"
  68 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
  69 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx"
  70 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt"
  71 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite"
  72 #define ENIC_DEVARG_REPRESENTOR "representor"
  73
  74 RTE_LOG_REGISTER(enic_pmd_logtype, pmd.net.enic, INFO);
  75
  76 static int
  77 enicpmd_dev_flow_ops_get(struct rte_eth_dev *dev,
  78                          const struct rte_flow_ops **ops)
  79 {
  80         struct enic *enic = pmd_priv(dev);
  81
  82         ENICPMD_FUNC_TRACE();
  83
  84         /*
  85          * Currently, when Geneve with options offload is enabled, host
  86          * cannot insert match-action rules.
  87          */
  88         if (enic->geneve_opt_enabled)
  89                 return -ENOTSUP;
  90
  91         if (enic->flow_filter_mode == FILTER_FLOWMAN)
  92                 *ops = &enic_fm_flow_ops;
  93         else
  94                 *ops = &enic_flow_ops;
  95         return 0;
  96 }
  97
  98 static void enicpmd_dev_tx_queue_release(void *txq)
  99 {
 100         ENICPMD_FUNC_TRACE();
 101
 102         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 103                 return;
 104
 105         enic_free_wq(txq);
 106 }
 107
 108 static int enicpmd_dev_setup_intr(struct enic *enic)
 109 {
 110         int ret;
 111         unsigned int index;
 112
 113         ENICPMD_FUNC_TRACE();
 114
 115         /* Are we done with the init of all the queues? */
 116         for (index = 0; index < enic->cq_count; index++) {
 117                 if (!enic->cq[index].ctrl)
 118                         break;
 119         }
 120         if (enic->cq_count != index)
 121                 return 0;
 122         for (index = 0; index < enic->wq_count; index++) {
 123                 if (!enic->wq[index].ctrl)
 124                         break;
 125         }
 126         if (enic->wq_count != index)
 127                 return 0;
 128         /* check start of packet (SOP) RQs only in case scatter is disabled. */
 129         for (index = 0; index < enic->rq_count; index++) {
 130                 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl)
 131                         break;
 132         }
 133         if (enic->rq_count != index)
 134                 return 0;
 135
 136         ret = enic_alloc_intr_resources(enic);
 137         if (ret) {
 138                 dev_err(enic, "alloc intr failed\n");
 139                 return ret;
 140         }
 141         enic_init_vnic_resources(enic);
 142
 143         ret = enic_setup_finish(enic);
 144         if (ret)
 145                 dev_err(enic, "setup could not be finished\n");
 146
 147         return ret;
 148 }
 149
 150 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 151         uint16_t queue_idx,
 152         uint16_t nb_desc,
 153         unsigned int socket_id,
 154         const struct rte_eth_txconf *tx_conf)
 155 {
 156         int ret;
 157         struct enic *enic = pmd_priv(eth_dev);
 158         struct vnic_wq *wq;
 159
 160         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 161                 return -E_RTE_SECONDARY;
 162
 163         ENICPMD_FUNC_TRACE();
 164         RTE_ASSERT(queue_idx < enic->conf_wq_count);
 165         wq = &enic->wq[queue_idx];
 166         wq->offloads = tx_conf->offloads |
 167                 eth_dev->data->dev_conf.txmode.offloads;
 168         eth_dev->data->tx_queues[queue_idx] = (void *)wq;
 169
 170         ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc);
 171         if (ret) {
 172                 dev_err(enic, "error in allocating wq\n");
 173                 return ret;
 174         }
 175
 176         return enicpmd_dev_setup_intr(enic);
 177 }
 178
 179 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
 180         uint16_t queue_idx)
 181 {
 182         struct enic *enic = pmd_priv(eth_dev);
 183
 184         ENICPMD_FUNC_TRACE();
 185
 186         enic_start_wq(enic, queue_idx);
 187
 188         return 0;
 189 }
 190
 191 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
 192         uint16_t queue_idx)
 193 {
 194         int ret;
 195         struct enic *enic = pmd_priv(eth_dev);
 196
 197         ENICPMD_FUNC_TRACE();
 198
 199         ret = enic_stop_wq(enic, queue_idx);
 200         if (ret)
 201                 dev_err(enic, "error in stopping wq %d\n", queue_idx);
 202
 203         return ret;
 204 }
 205
 206 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
 207         uint16_t queue_idx)
 208 {
 209         struct enic *enic = pmd_priv(eth_dev);
 210
 211         ENICPMD_FUNC_TRACE();
 212
 213         enic_start_rq(enic, queue_idx);
 214
 215         return 0;
 216 }
 217
 218 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
 219         uint16_t queue_idx)
 220 {
 221         int ret;
 222         struct enic *enic = pmd_priv(eth_dev);
 223
 224         ENICPMD_FUNC_TRACE();
 225
 226         ret = enic_stop_rq(enic, queue_idx);
 227         if (ret)
 228                 dev_err(enic, "error in stopping rq %d\n", queue_idx);
 229
 230         return ret;
 231 }
 232
 233 static void enicpmd_dev_rx_queue_release(void *rxq)
 234 {
 235         ENICPMD_FUNC_TRACE();
 236
 237         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 238                 return;
 239
 240         enic_free_rq(rxq);
 241 }
 242
 243 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev,
 244                                            uint16_t rx_queue_id)
 245 {
 246         struct enic *enic = pmd_priv(dev);
 247         uint32_t queue_count = 0;
 248         struct vnic_cq *cq;
 249         uint32_t cq_tail;
 250         uint16_t cq_idx;
 251         int rq_num;
 252
 253         rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 254         cq = &enic->cq[enic_cq_rq(enic, rq_num)];
 255         cq_idx = cq->to_clean;
 256
 257         cq_tail = ioread32(&cq->ctrl->cq_tail);
 258
 259         if (cq_tail < cq_idx)
 260                 cq_tail += cq->ring.desc_count;
 261
 262         queue_count = cq_tail - cq_idx;
 263
 264         return queue_count;
 265 }
 266
 267 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 268         uint16_t queue_idx,
 269         uint16_t nb_desc,
 270         unsigned int socket_id,
 271         const struct rte_eth_rxconf *rx_conf,
 272         struct rte_mempool *mp)
 273 {
 274         int ret;
 275         struct enic *enic = pmd_priv(eth_dev);
 276
 277         ENICPMD_FUNC_TRACE();
 278
 279         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 280                 return -E_RTE_SECONDARY;
 281         RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count);
 282         eth_dev->data->rx_queues[queue_idx] =
 283                 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)];
 284
 285         ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc,
 286                             rx_conf->rx_free_thresh);
 287         if (ret) {
 288                 dev_err(enic, "error in allocating rq\n");
 289                 return ret;
 290         }
 291
 292         return enicpmd_dev_setup_intr(enic);
 293 }
 294
 295 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 296 {
 297         struct enic *enic = pmd_priv(eth_dev);
 298         uint64_t offloads;
 299
 300         ENICPMD_FUNC_TRACE();
 301
 302         offloads = eth_dev->data->dev_conf.rxmode.offloads;
 303         if (mask & ETH_VLAN_STRIP_MASK) {
 304                 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 305                         enic->ig_vlan_strip_en = 1;
 306                 else
 307                         enic->ig_vlan_strip_en = 0;
 308         }
 309
 310         return enic_set_vlan_strip(enic);
 311 }
 312
 313 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev)
 314 {
 315         int ret;
 316         int mask;
 317         struct enic *enic = pmd_priv(eth_dev);
 318
 319         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 320                 return -E_RTE_SECONDARY;
 321
 322         ENICPMD_FUNC_TRACE();
 323         ret = enic_set_vnic_res(enic);
 324         if (ret) {
 325                 dev_err(enic, "Set vNIC resource num  failed, aborting\n");
 326                 return ret;
 327         }
 328
 329         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 330                 eth_dev->data->dev_conf.rxmode.offloads |=
 331                         DEV_RX_OFFLOAD_RSS_HASH;
 332
 333         enic->mc_count = 0;
 334         enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads &
 335                                   DEV_RX_OFFLOAD_CHECKSUM);
 336         /* All vlan offload masks to apply the current settings */
 337         mask = ETH_VLAN_STRIP_MASK |
 338                 ETH_VLAN_FILTER_MASK |
 339                 ETH_VLAN_EXTEND_MASK;
 340         ret = enicpmd_vlan_offload_set(eth_dev, mask);
 341         if (ret) {
 342                 dev_err(enic, "Failed to configure VLAN offloads\n");
 343                 return ret;
 344         }
 345         /*
 346          * Initialize RSS with the default reta and key. If the user key is
 347          * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the
 348          * default key.
 349          */
 350         return enic_init_rss_nic_cfg(enic);
 351 }
 352
 353 /* Start the device.
 354  * It returns 0 on success.
 355  */
 356 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev)
 357 {
 358         struct enic *enic = pmd_priv(eth_dev);
 359
 360         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 361                 return -E_RTE_SECONDARY;
 362
 363         ENICPMD_FUNC_TRACE();
 364         return enic_enable(enic);
 365 }
 366
 367 /*
 368  * Stop device: disable rx and tx functions to allow for reconfiguring.
 369  */
 370 static int enicpmd_dev_stop(struct rte_eth_dev *eth_dev)
 371 {
 372         struct rte_eth_link link;
 373         struct enic *enic = pmd_priv(eth_dev);
 374
 375         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 376                 return 0;
 377
 378         ENICPMD_FUNC_TRACE();
 379         enic_disable(enic);
 380
 381         memset(&link, 0, sizeof(link));
 382         rte_eth_linkstatus_set(eth_dev, &link);
 383
 384         return 0;
 385 }
 386
 387 /*
 388  * Stop device.
 389  */
 390 static int enicpmd_dev_close(struct rte_eth_dev *eth_dev)
 391 {
 392         struct enic *enic = pmd_priv(eth_dev);
 393
 394         ENICPMD_FUNC_TRACE();
 395         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 396                 return 0;
 397
 398         enic_remove(enic);
 399
 400         return 0;
 401 }
 402
 403 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,
 404         __rte_unused int wait_to_complete)
 405 {
 406         ENICPMD_FUNC_TRACE();
 407         return enic_link_update(eth_dev);
 408 }
 409
 410 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,
 411         struct rte_eth_stats *stats)
 412 {
 413         struct enic *enic = pmd_priv(eth_dev);
 414
 415         ENICPMD_FUNC_TRACE();
 416         return enic_dev_stats_get(enic, stats);
 417 }
 418
 419 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)
 420 {
 421         struct enic *enic = pmd_priv(eth_dev);
 422
 423         ENICPMD_FUNC_TRACE();
 424         return enic_dev_stats_clear(enic);
 425 }
 426
 427 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev)
 428 {
 429         const struct vic_speed_capa *m;
 430         struct rte_pci_device *pdev;
 431         uint16_t id;
 432
 433         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
 434         id = pdev->id.subsystem_device_id;
 435         for (m = vic_speed_capa_map; m->sub_devid != 0; m++) {
 436                 if (m->sub_devid == id)
 437                         return m->capa;
 438         }
 439         /* 1300 and later models are at least 40G */
 440         if (id >= 0x0100)
 441                 return ETH_LINK_SPEED_40G;
 442         /* VFs have subsystem id 0, check device id */
 443         if (id == 0) {
 444                 /* Newer VF implies at least 40G model */
 445                 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN)
 446                         return ETH_LINK_SPEED_40G;
 447         }
 448         return ETH_LINK_SPEED_10G;
 449 }
 450
 451 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
 452         struct rte_eth_dev_info *device_info)
 453 {
 454         struct enic *enic = pmd_priv(eth_dev);
 455
 456         ENICPMD_FUNC_TRACE();
 457         /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */
 458         device_info->max_rx_queues = enic->conf_rq_count / 2;
 459         device_info->max_tx_queues = enic->conf_wq_count;
 460         device_info->min_rx_bufsize = ENIC_MIN_MTU;
 461         /* "Max" mtu is not a typo. HW receives packet sizes up to the
 462          * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is
 463          * a hint to the driver to size receive buffers accordingly so that
 464          * larger-than-vnic-mtu packets get truncated.. For DPDK, we let
 465          * the user decide the buffer size via rxmode.max_rx_pkt_len, basically
 466          * ignoring vNIC mtu.
 467          */
 468         device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu);
 469         device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS;
 470         device_info->min_mtu = ENIC_MIN_MTU;
 471         device_info->max_mtu = enic->max_mtu;
 472         device_info->rx_offload_capa = enic->rx_offload_capa;
 473         device_info->tx_offload_capa = enic->tx_offload_capa;
 474         device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa;
 475         device_info->default_rxconf = (struct rte_eth_rxconf) {
 476                 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH
 477         };
 478         device_info->reta_size = enic->reta_size;
 479         device_info->hash_key_size = enic->hash_key_size;
 480         device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads;
 481         device_info->rx_desc_lim = (struct rte_eth_desc_lim) {
 482                 .nb_max = enic->config.rq_desc_count,
 483                 .nb_min = ENIC_MIN_RQ_DESCS,
 484                 .nb_align = ENIC_ALIGN_DESCS,
 485         };
 486         device_info->tx_desc_lim = (struct rte_eth_desc_lim) {
 487                 .nb_max = enic->config.wq_desc_count,
 488                 .nb_min = ENIC_MIN_WQ_DESCS,
 489                 .nb_align = ENIC_ALIGN_DESCS,
 490                 .nb_seg_max = ENIC_TX_XMIT_MAX,
 491                 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC,
 492         };
 493         device_info->default_rxportconf = (struct rte_eth_dev_portconf) {
 494                 .burst_size = ENIC_DEFAULT_RX_BURST,
 495                 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max,
 496                         ENIC_DEFAULT_RX_RING_SIZE),
 497                 .nb_queues = ENIC_DEFAULT_RX_RINGS,
 498         };
 499         device_info->default_txportconf = (struct rte_eth_dev_portconf) {
 500                 .burst_size = ENIC_DEFAULT_TX_BURST,
 501                 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max,
 502                         ENIC_DEFAULT_TX_RING_SIZE),
 503                 .nb_queues = ENIC_DEFAULT_TX_RINGS,
 504         };
 505         device_info->speed_capa = speed_capa_from_pci_id(eth_dev);
 506
 507         return 0;
 508 }
 509
 510 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 511 {
 512         static const uint32_t ptypes[] = {
 513                 RTE_PTYPE_L2_ETHER,
 514                 RTE_PTYPE_L2_ETHER_VLAN,
 515                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 516                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 517                 RTE_PTYPE_L4_TCP,
 518                 RTE_PTYPE_L4_UDP,
 519                 RTE_PTYPE_L4_FRAG,
 520                 RTE_PTYPE_L4_NONFRAG,
 521                 RTE_PTYPE_UNKNOWN
 522         };
 523         static const uint32_t ptypes_overlay[] = {
 524                 RTE_PTYPE_L2_ETHER,
 525                 RTE_PTYPE_L2_ETHER_VLAN,
 526                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 527                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 528                 RTE_PTYPE_L4_TCP,
 529                 RTE_PTYPE_L4_UDP,
 530                 RTE_PTYPE_L4_FRAG,
 531                 RTE_PTYPE_L4_NONFRAG,
 532                 RTE_PTYPE_TUNNEL_GRENAT,
 533                 RTE_PTYPE_INNER_L2_ETHER,
 534                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 535                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 536                 RTE_PTYPE_INNER_L4_TCP,
 537                 RTE_PTYPE_INNER_L4_UDP,
 538                 RTE_PTYPE_INNER_L4_FRAG,
 539                 RTE_PTYPE_INNER_L4_NONFRAG,
 540                 RTE_PTYPE_UNKNOWN
 541         };
 542
 543         if (dev->rx_pkt_burst != enic_dummy_recv_pkts &&
 544             dev->rx_pkt_burst != NULL) {
 545                 struct enic *enic = pmd_priv(dev);
 546                 if (enic->overlay_offload)
 547                         return ptypes_overlay;
 548                 else
 549                         return ptypes;
 550         }
 551         return NULL;
 552 }
 553
 554 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 555 {
 556         struct enic *enic = pmd_priv(eth_dev);
 557         int ret;
 558
 559         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 560                 return -E_RTE_SECONDARY;
 561
 562         ENICPMD_FUNC_TRACE();
 563
 564         enic->promisc = 1;
 565         ret = enic_add_packet_filter(enic);
 566         if (ret != 0)
 567                 enic->promisc = 0;
 568
 569         return ret;
 570 }
 571
 572 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 573 {
 574         struct enic *enic = pmd_priv(eth_dev);
 575         int ret;
 576
 577         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 578                 return -E_RTE_SECONDARY;
 579
 580         ENICPMD_FUNC_TRACE();
 581         enic->promisc = 0;
 582         ret = enic_add_packet_filter(enic);
 583         if (ret != 0)
 584                 enic->promisc = 1;
 585
 586         return ret;
 587 }
 588
 589 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 590 {
 591         struct enic *enic = pmd_priv(eth_dev);
 592         int ret;
 593
 594         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 595                 return -E_RTE_SECONDARY;
 596
 597         ENICPMD_FUNC_TRACE();
 598         enic->allmulti = 1;
 599         ret = enic_add_packet_filter(enic);
 600         if (ret != 0)
 601                 enic->allmulti = 0;
 602
 603         return ret;
 604 }
 605
 606 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 607 {
 608         struct enic *enic = pmd_priv(eth_dev);
 609         int ret;
 610
 611         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 612                 return -E_RTE_SECONDARY;
 613
 614         ENICPMD_FUNC_TRACE();
 615         enic->allmulti = 0;
 616         ret = enic_add_packet_filter(enic);
 617         if (ret != 0)
 618                 enic->allmulti = 1;
 619
 620         return ret;
 621 }
 622
 623 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev,
 624         struct rte_ether_addr *mac_addr,
 625         __rte_unused uint32_t index, __rte_unused uint32_t pool)
 626 {
 627         struct enic *enic = pmd_priv(eth_dev);
 628
 629         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 630                 return -E_RTE_SECONDARY;
 631
 632         ENICPMD_FUNC_TRACE();
 633         return enic_set_mac_address(enic, mac_addr->addr_bytes);
 634 }
 635
 636 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index)
 637 {
 638         struct enic *enic = pmd_priv(eth_dev);
 639
 640         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 641                 return;
 642
 643         ENICPMD_FUNC_TRACE();
 644         if (enic_del_mac_address(enic, index))
 645                 dev_err(enic, "del mac addr failed\n");
 646 }
 647
 648 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev,
 649                                 struct rte_ether_addr *addr)
 650 {
 651         struct enic *enic = pmd_priv(eth_dev);
 652         int ret;
 653
 654         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 655                 return -E_RTE_SECONDARY;
 656
 657         ENICPMD_FUNC_TRACE();
 658         ret = enic_del_mac_address(enic, 0);
 659         if (ret)
 660                 return ret;
 661         return enic_set_mac_address(enic, addr->addr_bytes);
 662 }
 663
 664 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add)
 665 {
 666         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 667
 668         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 669         ENICPMD_LOG(DEBUG, " %s address %s\n",
 670                      add ? "add" : "remove", mac_str);
 671 }
 672
 673 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev,
 674                                     struct rte_ether_addr *mc_addr_set,
 675                                     uint32_t nb_mc_addr)
 676 {
 677         struct enic *enic = pmd_priv(eth_dev);
 678         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 679         struct rte_ether_addr *addr;
 680         uint32_t i, j;
 681         int ret;
 682
 683         ENICPMD_FUNC_TRACE();
 684
 685         /* Validate the given addresses first */
 686         for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) {
 687                 addr = &mc_addr_set[i];
 688                 if (!rte_is_multicast_ether_addr(addr) ||
 689                     rte_is_broadcast_ether_addr(addr)) {
 690                         rte_ether_format_addr(mac_str,
 691                                         RTE_ETHER_ADDR_FMT_SIZE, addr);
 692                         ENICPMD_LOG(ERR, " invalid multicast address %s\n",
 693                                      mac_str);
 694                         return -EINVAL;
 695                 }
 696         }
 697
 698         /* Flush all if requested */
 699         if (nb_mc_addr == 0 || mc_addr_set == NULL) {
 700                 ENICPMD_LOG(DEBUG, " flush multicast addresses\n");
 701                 for (i = 0; i < enic->mc_count; i++) {
 702                         addr = &enic->mc_addrs[i];
 703                         debug_log_add_del_addr(addr, false);
 704                         ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 705                         if (ret)
 706                                 return ret;
 707                 }
 708                 enic->mc_count = 0;
 709                 return 0;
 710         }
 711
 712         if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) {
 713                 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n",
 714                              ENIC_MULTICAST_PERFECT_FILTERS);
 715                 return -ENOSPC;
 716         }
 717         /*
 718          * devcmd is slow, so apply the difference instead of flushing and
 719          * adding everything.
 720          * 1. Delete addresses on the NIC but not on the host
 721          */
 722         for (i = 0; i < enic->mc_count; i++) {
 723                 addr = &enic->mc_addrs[i];
 724                 for (j = 0; j < nb_mc_addr; j++) {
 725                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j]))
 726                                 break;
 727                 }
 728                 if (j < nb_mc_addr)
 729                         continue;
 730                 debug_log_add_del_addr(addr, false);
 731                 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 732                 if (ret)
 733                         return ret;
 734         }
 735         /* 2. Add addresses on the host but not on the NIC */
 736         for (i = 0; i < nb_mc_addr; i++) {
 737                 addr = &mc_addr_set[i];
 738                 for (j = 0; j < enic->mc_count; j++) {
 739                         if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j]))
 740                                 break;
 741                 }
 742                 if (j < enic->mc_count)
 743                         continue;
 744                 debug_log_add_del_addr(addr, true);
 745                 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes);
 746                 if (ret)
 747                         return ret;
 748         }
 749         /* Keep a copy so we can flush/apply later on.. */
 750         memcpy(enic->mc_addrs, mc_addr_set,
 751                nb_mc_addr * sizeof(struct rte_ether_addr));
 752         enic->mc_count = nb_mc_addr;
 753         return 0;
 754 }
 755
 756 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 757 {
 758         struct enic *enic = pmd_priv(eth_dev);
 759
 760         ENICPMD_FUNC_TRACE();
 761         return enic_set_mtu(enic, mtu);
 762 }
 763
 764 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev,
 765                                       struct rte_eth_rss_reta_entry64
 766                                       *reta_conf,
 767                                       uint16_t reta_size)
 768 {
 769         struct enic *enic = pmd_priv(dev);
 770         uint16_t i, idx, shift;
 771
 772         ENICPMD_FUNC_TRACE();
 773         if (reta_size != ENIC_RSS_RETA_SIZE) {
 774                 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n",
 775                         reta_size, ENIC_RSS_RETA_SIZE);
 776                 return -EINVAL;
 777         }
 778
 779         for (i = 0; i < reta_size; i++) {
 780                 idx = i / RTE_RETA_GROUP_SIZE;
 781                 shift = i % RTE_RETA_GROUP_SIZE;
 782                 if (reta_conf[idx].mask & (1ULL << shift))
 783                         reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx(
 784                                 enic->rss_cpu.cpu[i / 4].b[i % 4]);
 785         }
 786
 787         return 0;
 788 }
 789
 790 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev,
 791                                        struct rte_eth_rss_reta_entry64
 792                                        *reta_conf,
 793                                        uint16_t reta_size)
 794 {
 795         struct enic *enic = pmd_priv(dev);
 796         union vnic_rss_cpu rss_cpu;
 797         uint16_t i, idx, shift;
 798
 799         ENICPMD_FUNC_TRACE();
 800         if (reta_size != ENIC_RSS_RETA_SIZE) {
 801                 dev_err(enic, "reta_update: wrong reta_size. given=%u"
 802                         " expected=%u\n",
 803                         reta_size, ENIC_RSS_RETA_SIZE);
 804                 return -EINVAL;
 805         }
 806         /*
 807          * Start with the current reta and modify it per reta_conf, as we
 808          * need to push the entire reta even if we only modify one entry.
 809          */
 810         rss_cpu = enic->rss_cpu;
 811         for (i = 0; i < reta_size; i++) {
 812                 idx = i / RTE_RETA_GROUP_SIZE;
 813                 shift = i % RTE_RETA_GROUP_SIZE;
 814                 if (reta_conf[idx].mask & (1ULL << shift))
 815                         rss_cpu.cpu[i / 4].b[i % 4] =
 816                                 enic_rte_rq_idx_to_sop_idx(
 817                                         reta_conf[idx].reta[shift]);
 818         }
 819         return enic_set_rss_reta(enic, &rss_cpu);
 820 }
 821
 822 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev,
 823                                        struct rte_eth_rss_conf *rss_conf)
 824 {
 825         struct enic *enic = pmd_priv(dev);
 826
 827         ENICPMD_FUNC_TRACE();
 828         return enic_set_rss_conf(enic, rss_conf);
 829 }
 830
 831 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 832                                          struct rte_eth_rss_conf *rss_conf)
 833 {
 834         struct enic *enic = pmd_priv(dev);
 835
 836         ENICPMD_FUNC_TRACE();
 837         if (rss_conf == NULL)
 838                 return -EINVAL;
 839         if (rss_conf->rss_key != NULL &&
 840             rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) {
 841                 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u"
 842                         " expected=%u+\n",
 843                         rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE);
 844                 return -EINVAL;
 845         }
 846         rss_conf->rss_hf = enic->rss_hf;
 847         if (rss_conf->rss_key != NULL) {
 848                 int i;
 849                 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) {
 850                         rss_conf->rss_key[i] =
 851                                 enic->rss_key.key[i / 10].b[i % 10];
 852                 }
 853                 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE;
 854         }
 855         return 0;
 856 }
 857
 858 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev,
 859                                      uint16_t rx_queue_id,
 860                                      struct rte_eth_rxq_info *qinfo)
 861 {
 862         struct enic *enic = pmd_priv(dev);
 863         struct vnic_rq *rq_sop;
 864         struct vnic_rq *rq_data;
 865         struct rte_eth_rxconf *conf;
 866         uint16_t sop_queue_idx;
 867         uint16_t data_queue_idx;
 868
 869         ENICPMD_FUNC_TRACE();
 870         sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 871         data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic);
 872         rq_sop = &enic->rq[sop_queue_idx];
 873         rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */
 874         qinfo->mp = rq_sop->mp;
 875         qinfo->scattered_rx = rq_sop->data_queue_enable;
 876         qinfo->nb_desc = rq_sop->ring.desc_count;
 877         if (qinfo->scattered_rx)
 878                 qinfo->nb_desc += rq_data->ring.desc_count;
 879         conf = &qinfo->conf;
 880         memset(conf, 0, sizeof(*conf));
 881         conf->rx_free_thresh = rq_sop->rx_free_thresh;
 882         conf->rx_drop_en = 1;
 883         /*
 884          * Except VLAN stripping (port setting), all the checksum offloads
 885          * are always enabled.
 886          */
 887         conf->offloads = enic->rx_offload_capa;
 888         if (!enic->ig_vlan_strip_en)
 889                 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
 890         /* rx_thresh and other fields are not applicable for enic */
 891 }
 892
 893 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev,
 894                                      uint16_t tx_queue_id,
 895                                      struct rte_eth_txq_info *qinfo)
 896 {
 897         struct enic *enic = pmd_priv(dev);
 898         struct vnic_wq *wq = &enic->wq[tx_queue_id];
 899
 900         ENICPMD_FUNC_TRACE();
 901         qinfo->nb_desc = wq->ring.desc_count;
 902         memset(&qinfo->conf, 0, sizeof(qinfo->conf));
 903         qinfo->conf.offloads = wq->offloads;
 904         /* tx_thresh, and all the other fields are not applicable for enic */
 905 }
 906
 907 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 908                                          __rte_unused uint16_t queue_id,
 909                                          struct rte_eth_burst_mode *mode)
 910 {
 911         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
 912         struct enic *enic = pmd_priv(dev);
 913         const char *info_str = NULL;
 914         int ret = -EINVAL;
 915
 916         ENICPMD_FUNC_TRACE();
 917         if (enic->use_noscatter_vec_rx_handler)
 918                 info_str = "Vector AVX2 No Scatter";
 919         else if (pkt_burst == enic_noscatter_recv_pkts)
 920                 info_str = "Scalar No Scatter";
 921         else if (pkt_burst == enic_recv_pkts)
 922                 info_str = "Scalar";
 923         else if (pkt_burst == enic_recv_pkts_64)
 924                 info_str = "Scalar 64B Completion";
 925         if (info_str) {
 926                 strlcpy(mode->info, info_str, sizeof(mode->info));
 927                 ret = 0;
 928         }
 929         return ret;
 930 }
 931
 932 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 933                                          __rte_unused uint16_t queue_id,
 934                                          struct rte_eth_burst_mode *mode)
 935 {
 936         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
 937         const char *info_str = NULL;
 938         int ret = -EINVAL;
 939
 940         ENICPMD_FUNC_TRACE();
 941         if (pkt_burst == enic_simple_xmit_pkts)
 942                 info_str = "Scalar Simplified";
 943         else if (pkt_burst == enic_xmit_pkts)
 944                 info_str = "Scalar";
 945         if (info_str) {
 946                 strlcpy(mode->info, info_str, sizeof(mode->info));
 947                 ret = 0;
 948         }
 949         return ret;
 950 }
 951
 952 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 953                                             uint16_t rx_queue_id)
 954 {
 955         struct enic *enic = pmd_priv(eth_dev);
 956
 957         ENICPMD_FUNC_TRACE();
 958         vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 959         return 0;
 960 }
 961
 962 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 963                                              uint16_t rx_queue_id)
 964 {
 965         struct enic *enic = pmd_priv(eth_dev);
 966
 967         ENICPMD_FUNC_TRACE();
 968         vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 969         return 0;
 970 }
 971
 972 static int udp_tunnel_common_check(struct enic *enic,
 973                                    struct rte_eth_udp_tunnel *tnl)
 974 {
 975         if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN)
 976                 return -ENOTSUP;
 977         if (!enic->overlay_offload) {
 978                 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not "
 979                              "supported\n");
 980                 return -ENOTSUP;
 981         }
 982         return 0;
 983 }
 984
 985 static int update_vxlan_port(struct enic *enic, uint16_t port)
 986 {
 987         if (vnic_dev_overlay_offload_cfg(enic->vdev,
 988                                          OVERLAY_CFG_VXLAN_PORT_UPDATE,
 989                                          port)) {
 990                 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n");
 991                 return -EINVAL;
 992         }
 993         ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port);
 994         enic->vxlan_port = port;
 995         return 0;
 996 }
 997
 998 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev,
 999                                            struct rte_eth_udp_tunnel *tnl)
1000 {
1001         struct enic *enic = pmd_priv(eth_dev);
1002         int ret;
1003
1004         ENICPMD_FUNC_TRACE();
1005         ret = udp_tunnel_common_check(enic, tnl);
1006         if (ret)
1007                 return ret;
1008         /*
1009          * The NIC has 1 configurable VXLAN port number. "Adding" a new port
1010          * number replaces it.
1011          */
1012         if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) {
1013                 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n",
1014                              tnl->udp_port);
1015                 return -EINVAL;
1016         }
1017         return update_vxlan_port(enic, tnl->udp_port);
1018 }
1019
1020 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev,
1021                                            struct rte_eth_udp_tunnel *tnl)
1022 {
1023         struct enic *enic = pmd_priv(eth_dev);
1024         int ret;
1025
1026         ENICPMD_FUNC_TRACE();
1027         ret = udp_tunnel_common_check(enic, tnl);
1028         if (ret)
1029                 return ret;
1030         /*
1031          * Clear the previously set port number and restore the
1032          * hardware default port number. Some drivers disable VXLAN
1033          * offloads when there are no configured port numbers. But
1034          * enic does not do that as VXLAN is part of overlay offload,
1035          * which is tied to inner RSS and TSO.
1036          */
1037         if (tnl->udp_port != enic->vxlan_port) {
1038                 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n",
1039                              tnl->udp_port);
1040                 return -EINVAL;
1041         }
1042         return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT);
1043 }
1044
1045 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev,
1046                                       char *fw_version, size_t fw_size)
1047 {
1048         struct vnic_devcmd_fw_info *info;
1049         struct enic *enic;
1050         int ret;
1051
1052         ENICPMD_FUNC_TRACE();
1053         if (fw_version == NULL || fw_size <= 0)
1054                 return -EINVAL;
1055         enic = pmd_priv(eth_dev);
1056         ret = vnic_dev_fw_info(enic->vdev, &info);
1057         if (ret)
1058                 return ret;
1059         snprintf(fw_version, fw_size, "%s %s",
1060                  info->fw_version, info->fw_build);
1061         fw_version[fw_size - 1] = '\0';
1062         return 0;
1063 }
1064
1065 static const struct eth_dev_ops enicpmd_eth_dev_ops = {
1066         .dev_configure        = enicpmd_dev_configure,
1067         .dev_start            = enicpmd_dev_start,
1068         .dev_stop             = enicpmd_dev_stop,
1069         .dev_set_link_up      = NULL,
1070         .dev_set_link_down    = NULL,
1071         .dev_close            = enicpmd_dev_close,
1072         .promiscuous_enable   = enicpmd_dev_promiscuous_enable,
1073         .promiscuous_disable  = enicpmd_dev_promiscuous_disable,
1074         .allmulticast_enable  = enicpmd_dev_allmulticast_enable,
1075         .allmulticast_disable = enicpmd_dev_allmulticast_disable,
1076         .link_update          = enicpmd_dev_link_update,
1077         .stats_get            = enicpmd_dev_stats_get,
1078         .stats_reset          = enicpmd_dev_stats_reset,
1079         .queue_stats_mapping_set = NULL,
1080         .dev_infos_get        = enicpmd_dev_info_get,
1081         .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get,
1082         .mtu_set              = enicpmd_mtu_set,
1083         .vlan_filter_set      = NULL,
1084         .vlan_tpid_set        = NULL,
1085         .vlan_offload_set     = enicpmd_vlan_offload_set,
1086         .vlan_strip_queue_set = NULL,
1087         .rx_queue_start       = enicpmd_dev_rx_queue_start,
1088         .rx_queue_stop        = enicpmd_dev_rx_queue_stop,
1089         .tx_queue_start       = enicpmd_dev_tx_queue_start,
1090         .tx_queue_stop        = enicpmd_dev_tx_queue_stop,
1091         .rx_queue_setup       = enicpmd_dev_rx_queue_setup,
1092         .rx_queue_release     = enicpmd_dev_rx_queue_release,
1093         .tx_queue_setup       = enicpmd_dev_tx_queue_setup,
1094         .tx_queue_release     = enicpmd_dev_tx_queue_release,
1095         .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable,
1096         .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable,
1097         .rxq_info_get         = enicpmd_dev_rxq_info_get,
1098         .txq_info_get         = enicpmd_dev_txq_info_get,
1099         .rx_burst_mode_get    = enicpmd_dev_rx_burst_mode_get,
1100         .tx_burst_mode_get    = enicpmd_dev_tx_burst_mode_get,
1101         .dev_led_on           = NULL,
1102         .dev_led_off          = NULL,
1103         .flow_ctrl_get        = NULL,
1104         .flow_ctrl_set        = NULL,
1105         .priority_flow_ctrl_set = NULL,
1106         .mac_addr_add         = enicpmd_add_mac_addr,
1107         .mac_addr_remove      = enicpmd_remove_mac_addr,
1108         .mac_addr_set         = enicpmd_set_mac_addr,
1109         .set_mc_addr_list     = enicpmd_set_mc_addr_list,
1110         .flow_ops_get         = enicpmd_dev_flow_ops_get,
1111         .reta_query           = enicpmd_dev_rss_reta_query,
1112         .reta_update          = enicpmd_dev_rss_reta_update,
1113         .rss_hash_conf_get    = enicpmd_dev_rss_hash_conf_get,
1114         .rss_hash_update      = enicpmd_dev_rss_hash_update,
1115         .udp_tunnel_port_add  = enicpmd_dev_udp_tunnel_port_add,
1116         .udp_tunnel_port_del  = enicpmd_dev_udp_tunnel_port_del,
1117         .fw_version_get       = enicpmd_dev_fw_version_get,
1118 };
1119
1120 static int enic_parse_zero_one(const char *key,
1121                                const char *value,
1122                                void *opaque)
1123 {
1124         struct enic *enic;
1125         bool b;
1126
1127         enic = (struct enic *)opaque;
1128         if (strcmp(value, "0") == 0) {
1129                 b = false;
1130         } else if (strcmp(value, "1") == 0) {
1131                 b = true;
1132         } else {
1133                 dev_err(enic, "Invalid value for %s"
1134                         ": expected=0|1 given=%s\n", key, value);
1135                 return -EINVAL;
1136         }
1137         if (strcmp(key, ENIC_DEVARG_CQ64) == 0)
1138                 enic->cq64_request = b;
1139         if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0)
1140                 enic->disable_overlay = b;
1141         if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0)
1142                 enic->enable_avx2_rx = b;
1143         if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0)
1144                 enic->geneve_opt_request = b;
1145         return 0;
1146 }
1147
1148 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key,
1149                                       const char *value,
1150                                       void *opaque)
1151 {
1152         struct enic *enic;
1153
1154         enic = (struct enic *)opaque;
1155         if (strcmp(value, "trunk") == 0) {
1156                 /* Trunk mode: always tag */
1157                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK;
1158         } else if (strcmp(value, "untag") == 0) {
1159                 /* Untag default VLAN mode: untag if VLAN = default VLAN */
1160                 enic->ig_vlan_rewrite_mode =
1161                         IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN;
1162         } else if (strcmp(value, "priority") == 0) {
1163                 /*
1164                  * Priority-tag default VLAN mode: priority tag (VLAN header
1165                  * with ID=0) if VLAN = default
1166                  */
1167                 enic->ig_vlan_rewrite_mode =
1168                         IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN;
1169         } else if (strcmp(value, "pass") == 0) {
1170                 /* Pass through mode: do not touch tags */
1171                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1172         } else {
1173                 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE
1174                         ": expected=trunk|untag|priority|pass given=%s\n",
1175                         value);
1176                 return -EINVAL;
1177         }
1178         return 0;
1179 }
1180
1181 static int enic_check_devargs(struct rte_eth_dev *dev)
1182 {
1183         static const char *const valid_keys[] = {
1184                 ENIC_DEVARG_CQ64,
1185                 ENIC_DEVARG_DISABLE_OVERLAY,
1186                 ENIC_DEVARG_ENABLE_AVX2_RX,
1187                 ENIC_DEVARG_GENEVE_OPT,
1188                 ENIC_DEVARG_IG_VLAN_REWRITE,
1189                 ENIC_DEVARG_REPRESENTOR,
1190                 NULL};
1191         struct enic *enic = pmd_priv(dev);
1192         struct rte_kvargs *kvlist;
1193
1194         ENICPMD_FUNC_TRACE();
1195
1196         enic->cq64_request = true; /* Use 64B entry if available */
1197         enic->disable_overlay = false;
1198         enic->enable_avx2_rx = false;
1199         enic->geneve_opt_request = false;
1200         enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1201         if (!dev->device->devargs)
1202                 return 0;
1203         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1204         if (!kvlist)
1205                 return -EINVAL;
1206         if (rte_kvargs_process(kvlist, ENIC_DEVARG_CQ64,
1207                                enic_parse_zero_one, enic) < 0 ||
1208             rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY,
1209                                enic_parse_zero_one, enic) < 0 ||
1210             rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX,
1211                                enic_parse_zero_one, enic) < 0 ||
1212             rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT,
1213                                enic_parse_zero_one, enic) < 0 ||
1214             rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE,
1215                                enic_parse_ig_vlan_rewrite, enic) < 0) {
1216                 rte_kvargs_free(kvlist);
1217                 return -EINVAL;
1218         }
1219         rte_kvargs_free(kvlist);
1220         return 0;
1221 }
1222
1223 /* Initialize the driver for PF */
1224 static int eth_enic_dev_init(struct rte_eth_dev *eth_dev,
1225                              void *init_params __rte_unused)
1226 {
1227         struct rte_pci_device *pdev;
1228         struct rte_pci_addr *addr;
1229         struct enic *enic = pmd_priv(eth_dev);
1230         int err;
1231
1232         ENICPMD_FUNC_TRACE();
1233         eth_dev->dev_ops = &enicpmd_eth_dev_ops;
1234         eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count;
1235         eth_dev->rx_pkt_burst = &enic_recv_pkts;
1236         eth_dev->tx_pkt_burst = &enic_xmit_pkts;
1237         eth_dev->tx_pkt_prepare = &enic_prep_pkts;
1238         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1239                 enic_pick_tx_handler(eth_dev);
1240                 enic_pick_rx_handler(eth_dev);
1241                 return 0;
1242         }
1243         /* Only the primary sets up adapter and other data in shared memory */
1244         enic->port_id = eth_dev->data->port_id;
1245         enic->rte_dev = eth_dev;
1246         enic->dev_data = eth_dev->data;
1247
1248         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
1249         rte_eth_copy_pci_info(eth_dev, pdev);
1250         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1251         enic->pdev = pdev;
1252         addr = &pdev->addr;
1253
1254         snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x",
1255                 addr->domain, addr->bus, addr->devid, addr->function);
1256
1257         err = enic_check_devargs(eth_dev);
1258         if (err)
1259                 return err;
1260         err = enic_probe(enic);
1261         if (!err && enic->fm) {
1262                 err = enic_fm_allocate_switch_domain(enic);
1263                 if (err)
1264                         ENICPMD_LOG(ERR, "failed to allocate switch domain id");
1265         }
1266         return err;
1267 }
1268
1269 static int eth_enic_dev_uninit(struct rte_eth_dev *eth_dev)
1270 {
1271         struct enic *enic = pmd_priv(eth_dev);
1272         int err;
1273
1274         ENICPMD_FUNC_TRACE();
1275         eth_dev->device = NULL;
1276         eth_dev->intr_handle = NULL;
1277         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1278                 return 0;
1279         err = rte_eth_switch_domain_free(enic->switch_domain_id);
1280         if (err)
1281                 ENICPMD_LOG(WARNING, "failed to free switch domain: %d", err);
1282         return 0;
1283 }
1284
1285 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1286         struct rte_pci_device *pci_dev)
1287 {
1288         char name[RTE_ETH_NAME_MAX_LEN];
1289         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
1290         struct rte_eth_dev *pf_ethdev;
1291         struct enic *pf_enic;
1292         int i, retval;
1293
1294         ENICPMD_FUNC_TRACE();
1295         if (pci_dev->device.devargs) {
1296                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1297                                 &eth_da);
1298                 if (retval)
1299                         return retval;
1300         }
1301         if (eth_da.nb_representor_ports > 0 &&
1302             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1303                 ENICPMD_LOG(ERR, "unsupported representor type: %s\n",
1304                             pci_dev->device.devargs->args);
1305                 return -ENOTSUP;
1306         }
1307         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1308                 sizeof(struct enic),
1309                 eth_dev_pci_specific_init, pci_dev,
1310                 eth_enic_dev_init, NULL);
1311         if (retval || eth_da.nb_representor_ports < 1)
1312                 return retval;
1313
1314         /* Probe VF representor */
1315         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1316         if (pf_ethdev == NULL)
1317                 return -ENODEV;
1318         /* Representors require flowman */
1319         pf_enic = pmd_priv(pf_ethdev);
1320         if (pf_enic->fm == NULL) {
1321                 ENICPMD_LOG(ERR, "VF representors require flowman");
1322                 return -ENOTSUP;
1323         }
1324         /*
1325          * For now representors imply switchdev, as firmware does not support
1326          * legacy mode SR-IOV
1327          */
1328         pf_enic->switchdev_mode = 1;
1329         /* Calculate max VF ID before initializing representor*/
1330         pf_enic->max_vf_id = 0;
1331         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1332                 pf_enic->max_vf_id = RTE_MAX(pf_enic->max_vf_id,
1333                                              eth_da.representor_ports[i]);
1334         }
1335         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1336                 struct enic_vf_representor representor;
1337
1338                 representor.vf_id = eth_da.representor_ports[i];
1339                                 representor.switch_domain_id =
1340                         pmd_priv(pf_ethdev)->switch_domain_id;
1341                 representor.pf = pmd_priv(pf_ethdev);
1342                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1343                         pci_dev->device.name, eth_da.representor_ports[i]);
1344                 retval = rte_eth_dev_create(&pci_dev->device, name,
1345                         sizeof(struct enic_vf_representor), NULL, NULL,
1346                         enic_vf_representor_init, &representor);
1347                 if (retval) {
1348                         ENICPMD_LOG(ERR, "failed to create enic vf representor %s",
1349                                     name);
1350                         return retval;
1351                 }
1352         }
1353         return 0;
1354 }
1355
1356 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev)
1357 {
1358         struct rte_eth_dev *ethdev;
1359
1360         ENICPMD_FUNC_TRACE();
1361         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1362         if (!ethdev)
1363                 return -ENODEV;
1364         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1365                 return rte_eth_dev_destroy(ethdev, enic_vf_representor_uninit);
1366         else
1367                 return rte_eth_dev_destroy(ethdev, eth_enic_dev_uninit);
1368 }
1369
1370 static struct rte_pci_driver rte_enic_pmd = {
1371         .id_table = pci_id_enic_map,
1372         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1373         .probe = eth_enic_pci_probe,
1374         .remove = eth_enic_pci_remove,
1375 };
1376
1377 int dev_is_enic(struct rte_eth_dev *dev)
1378 {
1379         return dev->device->driver == &rte_enic_pmd.driver;
1380 }
1381
1382 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd);
1383 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map);
1384 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci");
1385 RTE_PMD_REGISTER_PARAM_STRING(net_enic,
1386         ENIC_DEVARG_CQ64 "=0|1"
1387         ENIC_DEVARG_DISABLE_OVERLAY "=0|1 "
1388         ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 "
1389         ENIC_DEVARG_GENEVE_OPT "=0|1 "
1390         ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass");