drivers/net/enic/enic_res.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  */
   5
   6 #include "enic_compat.h"
   7 #include "ethdev_driver.h"
   8 #include "wq_enet_desc.h"
   9 #include "rq_enet_desc.h"
  10 #include "cq_enet_desc.h"
  11 #include "vnic_resource.h"
  12 #include "vnic_enet.h"
  13 #include "vnic_dev.h"
  14 #include "vnic_wq.h"
  15 #include "vnic_rq.h"
  16 #include "vnic_cq.h"
  17 #include "vnic_intr.h"
  18 #include "vnic_stats.h"
  19 #include "vnic_nic.h"
  20 #include "vnic_rss.h"
  21 #include "enic_res.h"
  22 #include "enic.h"
  23
  24 int enic_get_vnic_config(struct enic *enic)
  25 {
  26         struct vnic_enet_config *c = &enic->config;
  27         int err;
  28         uint64_t sizes;
  29         uint32_t max_rq_descs, max_wq_descs;
  30
  31         err = vnic_dev_get_mac_addr(enic->vdev, enic->mac_addr);
  32         if (err) {
  33                 dev_err(enic_get_dev(enic),
  34                         "Error getting MAC addr, %d\n", err);
  35                 return err;
  36         }
  37
  38
  39 #define GET_CONFIG(m) \
  40         do { \
  41                 err = vnic_dev_spec(enic->vdev, \
  42                         offsetof(struct vnic_enet_config, m), \
  43                         sizeof(c->m), &c->m); \
  44                 if (err) { \
  45                         dev_err(enic_get_dev(enic), \
  46                                 "Error getting %s, %d\n", #m, err); \
  47                         return err; \
  48                 } \
  49         } while (0)
  50
  51         GET_CONFIG(flags);
  52         GET_CONFIG(wq_desc_count);
  53         GET_CONFIG(rq_desc_count);
  54         GET_CONFIG(mtu);
  55         GET_CONFIG(intr_timer_type);
  56         GET_CONFIG(intr_mode);
  57         GET_CONFIG(intr_timer_usec);
  58         GET_CONFIG(loop_tag);
  59         GET_CONFIG(num_arfs);
  60         GET_CONFIG(max_pkt_size);
  61         GET_CONFIG(max_rq_ring);
  62         GET_CONFIG(max_wq_ring);
  63
  64         /* max packet size is only defined in newer VIC firmware
  65          * and will be 0 for legacy firmware and VICs
  66          */
  67         if (c->max_pkt_size > ENIC_DEFAULT_RX_MAX_PKT_SIZE)
  68                 enic->max_mtu = c->max_pkt_size - RTE_ETHER_HDR_LEN;
  69         else
  70                 enic->max_mtu = ENIC_DEFAULT_RX_MAX_PKT_SIZE -
  71                         RTE_ETHER_HDR_LEN;
  72         if (c->mtu == 0)
  73                 c->mtu = 1500;
  74
  75         enic->rte_dev->data->mtu = RTE_MIN(enic->max_mtu,
  76                                 RTE_MAX((uint16_t)ENIC_MIN_MTU, c->mtu));
  77
  78         enic->adv_filters = vnic_dev_capable_adv_filters(enic->vdev);
  79         dev_info(enic, "Advanced Filters %savailable\n", ((enic->adv_filters)
  80                  ? "" : "not "));
  81
  82         err = vnic_dev_capable_filter_mode(enic->vdev, &enic->flow_filter_mode,
  83                                            &enic->filter_actions);
  84         if (err) {
  85                 dev_err(enic_get_dev(enic),
  86                         "Error getting filter modes, %d\n", err);
  87                 return err;
  88         }
  89         vnic_dev_capable_udp_rss_weak(enic->vdev, &enic->nic_cfg_chk,
  90                                       &enic->udp_rss_weak);
  91
  92         dev_info(enic, "Flow api filter mode: %s Actions: %s%s%s%s\n",
  93                 ((enic->flow_filter_mode == FILTER_FLOWMAN) ? "FLOWMAN" :
  94                 ((enic->flow_filter_mode == FILTER_DPDK_1) ? "DPDK" :
  95                 ((enic->flow_filter_mode == FILTER_USNIC_IP) ? "USNIC" :
  96                 ((enic->flow_filter_mode == FILTER_IPV4_5TUPLE) ? "5TUPLE" :
  97                 "NONE")))),
  98                 ((enic->filter_actions & FILTER_ACTION_RQ_STEERING_FLAG) ?
  99                  "steer " : ""),
 100                 ((enic->filter_actions & FILTER_ACTION_FILTER_ID_FLAG) ?
 101                  "tag " : ""),
 102                 ((enic->filter_actions & FILTER_ACTION_DROP_FLAG) ?
 103                  "drop " : ""),
 104                 ((enic->filter_actions & FILTER_ACTION_COUNTER_FLAG) ?
 105                  "count " : ""));
 106
 107         /* The max size of RQ and WQ rings are specified in 1500 series VICs and
 108          * beyond. If they are not specified by the VIC or if 64B CQ descriptors
 109          * are not being used, the max number of descriptors is 4096.
 110          */
 111         max_wq_descs = (enic->cq64_request && c->max_wq_ring) ? c->max_wq_ring :
 112                        ENIC_LEGACY_MAX_WQ_DESCS;
 113         c->wq_desc_count = RTE_MIN(max_wq_descs,
 114                         RTE_MAX((uint32_t)ENIC_MIN_WQ_DESCS, c->wq_desc_count));
 115         c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
 116         max_rq_descs = (enic->cq64_request && c->max_rq_ring) ? c->max_rq_ring
 117                        : ENIC_LEGACY_MAX_WQ_DESCS;
 118         c->rq_desc_count = RTE_MIN(max_rq_descs,
 119                         RTE_MAX((uint32_t)ENIC_MIN_RQ_DESCS, c->rq_desc_count));
 120         c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
 121         dev_debug(NULL, "Max supported VIC descriptors: WQ:%u, RQ:%u\n",
 122                   max_wq_descs, max_rq_descs);
 123
 124         c->intr_timer_usec = RTE_MIN(c->intr_timer_usec,
 125                                   vnic_dev_get_intr_coal_timer_max(enic->vdev));
 126
 127         dev_info(enic_get_dev(enic),
 128                 "vNIC MAC addr " RTE_ETHER_ADDR_PRT_FMT
 129                 " wq/rq %d/%d mtu %d, max mtu:%d\n",
 130                 enic->mac_addr[0], enic->mac_addr[1], enic->mac_addr[2],
 131                 enic->mac_addr[3], enic->mac_addr[4], enic->mac_addr[5],
 132                 c->wq_desc_count, c->rq_desc_count,
 133                 enic->rte_dev->data->mtu, enic->max_mtu);
 134         dev_info(enic_get_dev(enic), "vNIC csum tx/rx %s/%s "
 135                 "rss %s intr mode %s type %s timer %d usec "
 136                 "loopback tag 0x%04x\n",
 137                 ENIC_SETTING(enic, TXCSUM) ? "yes" : "no",
 138                 ENIC_SETTING(enic, RXCSUM) ? "yes" : "no",
 139                 ENIC_SETTING(enic, RSS) ?
 140                         (ENIC_SETTING(enic, RSSHASH_UDPIPV4) ? "+UDP" :
 141                         ((enic->udp_rss_weak ? "+udp" :
 142                         "yes"))) : "no",
 143                 c->intr_mode == VENET_INTR_MODE_INTX ? "INTx" :
 144                 c->intr_mode == VENET_INTR_MODE_MSI ? "MSI" :
 145                 c->intr_mode == VENET_INTR_MODE_ANY ? "any" :
 146                 "unknown",
 147                 c->intr_timer_type == VENET_INTR_TYPE_MIN ? "min" :
 148                 c->intr_timer_type == VENET_INTR_TYPE_IDLE ? "idle" :
 149                 "unknown",
 150                 c->intr_timer_usec,
 151                 c->loop_tag);
 152
 153         /* RSS settings from vNIC */
 154         enic->reta_size = ENIC_RSS_RETA_SIZE;
 155         enic->hash_key_size = ENIC_RSS_HASH_KEY_SIZE;
 156         enic->flow_type_rss_offloads = 0;
 157         if (ENIC_SETTING(enic, RSSHASH_IPV4))
 158                 /*
 159                  * IPV4 hash type handles both non-frag and frag packet types.
 160                  * TCP/UDP is controlled via a separate flag below.
 161                  */
 162                 enic->flow_type_rss_offloads |= RTE_ETH_RSS_IPV4 |
 163                         RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER;
 164         if (ENIC_SETTING(enic, RSSHASH_TCPIPV4))
 165                 enic->flow_type_rss_offloads |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
 166         if (ENIC_SETTING(enic, RSSHASH_IPV6))
 167                 /*
 168                  * The VIC adapter can perform RSS on IPv6 packets with and
 169                  * without extension headers. An IPv6 "fragment" is an IPv6
 170                  * packet with the fragment extension header.
 171                  */
 172                 enic->flow_type_rss_offloads |= RTE_ETH_RSS_IPV6 |
 173                         RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_FRAG_IPV6 |
 174                         RTE_ETH_RSS_NONFRAG_IPV6_OTHER;
 175         if (ENIC_SETTING(enic, RSSHASH_TCPIPV6))
 176                 enic->flow_type_rss_offloads |= RTE_ETH_RSS_NONFRAG_IPV6_TCP |
 177                         RTE_ETH_RSS_IPV6_TCP_EX;
 178         if (enic->udp_rss_weak)
 179                 enic->flow_type_rss_offloads |=
 180                         RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP |
 181                         RTE_ETH_RSS_IPV6_UDP_EX;
 182         if (ENIC_SETTING(enic, RSSHASH_UDPIPV4))
 183                 enic->flow_type_rss_offloads |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
 184         if (ENIC_SETTING(enic, RSSHASH_UDPIPV6))
 185                 enic->flow_type_rss_offloads |= RTE_ETH_RSS_NONFRAG_IPV6_UDP |
 186                         RTE_ETH_RSS_IPV6_UDP_EX;
 187
 188         /* Zero offloads if RSS is not enabled */
 189         if (!ENIC_SETTING(enic, RSS))
 190                 enic->flow_type_rss_offloads = 0;
 191
 192         enic->vxlan = ENIC_SETTING(enic, VXLAN) &&
 193                 vnic_dev_capable_vxlan(enic->vdev);
 194         enic->geneve = ENIC_SETTING(enic, GENEVE) &&
 195                 vnic_dev_capable_geneve(enic->vdev);
 196
 197         /* Supported CQ entry sizes */
 198         enic->cq_entry_sizes = vnic_dev_capable_cq_entry_size(enic->vdev);
 199         sizes = enic->cq_entry_sizes;
 200         dev_debug(NULL, "Supported CQ entry sizes:%s%s%s\n",
 201                   (sizes & VNIC_RQ_CQ_ENTRY_SIZE_16_CAPABLE) ? " 16" : "",
 202                   (sizes & VNIC_RQ_CQ_ENTRY_SIZE_32_CAPABLE) ? " 32" : "",
 203                   (sizes & VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE) ? " 64" : "");
 204         /* Use 64B entry if requested and available */
 205         enic->cq64 = enic->cq64_request &&
 206                 (sizes & VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE);
 207         dev_debug(NULL, "Using %sB CQ entry size\n", enic->cq64 ? "64" : "16");
 208
 209         /*
 210          * Default hardware capabilities. enic_dev_init() may add additional
 211          * flags if it enables overlay offloads.
 212          */
 213         enic->tx_queue_offload_capa = 0;
 214         enic->tx_offload_capa =
 215                 enic->tx_queue_offload_capa |
 216                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 217                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
 218                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 219                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 220                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 221                 RTE_ETH_TX_OFFLOAD_TCP_TSO;
 222         enic->rx_offload_capa =
 223                 RTE_ETH_RX_OFFLOAD_SCATTER |
 224                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 225                 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 226                 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 227                 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 228                 RTE_ETH_RX_OFFLOAD_RSS_HASH;
 229         enic->tx_offload_mask =
 230                 RTE_MBUF_F_TX_IPV6 |
 231                 RTE_MBUF_F_TX_IPV4 |
 232                 RTE_MBUF_F_TX_VLAN |
 233                 RTE_MBUF_F_TX_IP_CKSUM |
 234                 RTE_MBUF_F_TX_L4_MASK |
 235                 RTE_MBUF_F_TX_TCP_SEG;
 236
 237         return 0;
 238 }
 239
 240 int enic_set_nic_cfg(struct enic *enic, uint8_t rss_default_cpu,
 241                      uint8_t rss_hash_type, uint8_t rss_hash_bits,
 242                      uint8_t rss_base_cpu, uint8_t rss_enable,
 243                      uint8_t tso_ipid_split_en, uint8_t ig_vlan_strip_en)
 244 {
 245         enum vnic_devcmd_cmd cmd;
 246         uint64_t a0, a1;
 247         uint32_t nic_cfg;
 248         int wait = 1000;
 249
 250         vnic_set_nic_cfg(&nic_cfg, rss_default_cpu,
 251                 rss_hash_type, rss_hash_bits, rss_base_cpu,
 252                 rss_enable, tso_ipid_split_en, ig_vlan_strip_en);
 253
 254         a0 = nic_cfg;
 255         a1 = 0;
 256         cmd = enic->nic_cfg_chk ? CMD_NIC_CFG_CHK : CMD_NIC_CFG;
 257         return vnic_dev_cmd(enic->vdev, cmd, &a0, &a1, wait);
 258 }
 259
 260 int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, uint64_t len)
 261 {
 262         uint64_t a0 = (uint64_t)key_pa, a1 = len;
 263         int wait = 1000;
 264
 265         return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
 266 }
 267
 268 int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, uint64_t len)
 269 {
 270         uint64_t a0 = (uint64_t)cpu_pa, a1 = len;
 271         int wait = 1000;
 272
 273         return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
 274 }
 275
 276 void enic_free_vnic_resources(struct enic *enic)
 277 {
 278         unsigned int i;
 279
 280         for (i = 0; i < enic->wq_count; i++)
 281                 vnic_wq_free(&enic->wq[i]);
 282         for (i = 0; i < enic_vnic_rq_count(enic); i++)
 283                 if (enic->rq[i].in_use)
 284                         vnic_rq_free(&enic->rq[i]);
 285         for (i = 0; i < enic->cq_count; i++)
 286                 vnic_cq_free(&enic->cq[i]);
 287         for (i = 0; i < enic->intr_count; i++)
 288                 vnic_intr_free(&enic->intr[i]);
 289 }
 290
 291 void enic_get_res_counts(struct enic *enic)
 292 {
 293         enic->conf_wq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);
 294         enic->conf_rq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);
 295         enic->conf_cq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);
 296         enic->conf_intr_count = vnic_dev_get_res_count(enic->vdev,
 297                 RES_TYPE_INTR_CTRL);
 298
 299         dev_info(enic_get_dev(enic),
 300                 "vNIC resources avail: wq %d rq %d cq %d intr %d\n",
 301                 enic->conf_wq_count, enic->conf_rq_count,
 302                 enic->conf_cq_count, enic->conf_intr_count);
 303 }