drivers/net/enic/enic_rx.c

   1 /*
   2  * Copyright 2008-2014 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  *
   5  * Copyright (c) 2014, Cisco Systems, Inc.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  * notice, this list of conditions and the following disclaimer.
  14  *
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  * notice, this list of conditions and the following disclaimer in
  17  * the documentation and/or other materials provided with the
  18  * distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  23  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  24  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  26  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  30  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <rte_mbuf.h>
  36 #include <rte_ethdev.h>
  37 #include <rte_prefetch.h>
  38
  39 #include "enic_compat.h"
  40 #include "rq_enet_desc.h"
  41 #include "enic.h"
  42
  43 #define RTE_PMD_USE_PREFETCH
  44
  45 #ifdef RTE_PMD_USE_PREFETCH
  46 /*
  47  * Prefetch a cache line into all cache levels.
  48  */
  49 #define rte_enic_prefetch(p) rte_prefetch0(p)
  50 #else
  51 #define rte_enic_prefetch(p) do {} while (0)
  52 #endif
  53
  54 #ifdef RTE_PMD_PACKET_PREFETCH
  55 #define rte_packet_prefetch(p) rte_prefetch1(p)
  56 #else
  57 #define rte_packet_prefetch(p) do {} while (0)
  58 #endif
  59
  60 static inline uint16_t
  61 enic_cq_rx_desc_ciflags(struct cq_enet_rq_desc *crd)
  62 {
  63         return le16_to_cpu(crd->completed_index_flags) & ~CQ_DESC_COMP_NDX_MASK;
  64 }
  65
  66 static inline uint16_t
  67 enic_cq_rx_desc_bwflags(struct cq_enet_rq_desc *crd)
  68 {
  69         return(le16_to_cpu(crd->bytes_written_flags) &
  70                 ~CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK);
  71 }
  72
  73 static inline uint8_t
  74 enic_cq_rx_desc_packet_error(uint16_t bwflags)
  75 {
  76         return((bwflags & CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ==
  77                 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED);
  78 }
  79
  80 static inline uint8_t
  81 enic_cq_rx_desc_eop(uint16_t ciflags)
  82 {
  83         return (ciflags & CQ_ENET_RQ_DESC_FLAGS_EOP)
  84                 == CQ_ENET_RQ_DESC_FLAGS_EOP;
  85 }
  86
  87 static inline uint8_t
  88 enic_cq_rx_desc_csum_not_calc(struct cq_enet_rq_desc *cqrd)
  89 {
  90         return ((le16_to_cpu(cqrd->q_number_rss_type_flags) &
  91                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ==
  92                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC);
  93 }
  94
  95 static inline uint8_t
  96 enic_cq_rx_desc_ipv4_csum_ok(struct cq_enet_rq_desc *cqrd)
  97 {
  98         return ((cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ==
  99                 CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK);
 100 }
 101
 102 static inline uint8_t
 103 enic_cq_rx_desc_tcp_udp_csum_ok(struct cq_enet_rq_desc *cqrd)
 104 {
 105         return((cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ==
 106                 CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK);
 107 }
 108
 109 static inline uint8_t
 110 enic_cq_rx_desc_rss_type(struct cq_enet_rq_desc *cqrd)
 111 {
 112         return (uint8_t)((le16_to_cpu(cqrd->q_number_rss_type_flags) >>
 113                 CQ_DESC_Q_NUM_BITS) & CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
 114 }
 115
 116 static inline uint32_t
 117 enic_cq_rx_desc_rss_hash(struct cq_enet_rq_desc *cqrd)
 118 {
 119         return le32_to_cpu(cqrd->rss_hash);
 120 }
 121
 122 static inline uint16_t
 123 enic_cq_rx_desc_vlan(struct cq_enet_rq_desc *cqrd)
 124 {
 125         return le16_to_cpu(cqrd->vlan);
 126 }
 127
 128 static inline uint16_t
 129 enic_cq_rx_desc_n_bytes(struct cq_desc *cqd)
 130 {
 131         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 132         return le16_to_cpu(cqrd->bytes_written_flags) &
 133                 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
 134 }
 135
 136 static inline uint8_t
 137 enic_cq_rx_to_pkt_err_flags(struct cq_desc *cqd, uint64_t *pkt_err_flags_out)
 138 {
 139         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 140         uint16_t bwflags;
 141         int ret = 0;
 142         uint64_t pkt_err_flags = 0;
 143
 144         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 145         if (unlikely(enic_cq_rx_desc_packet_error(bwflags))) {
 146                 pkt_err_flags = PKT_RX_MAC_ERR;
 147                 ret = 1;
 148         }
 149         *pkt_err_flags_out = pkt_err_flags;
 150         return ret;
 151 }
 152
 153 /*
 154  * Lookup table to translate RX CQ flags to mbuf flags.
 155  */
 156 static inline uint32_t
 157 enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd)
 158 {
 159         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 160         uint8_t cqrd_flags = cqrd->flags;
 161         static const uint32_t cq_type_table[128] __rte_cache_aligned = {
 162                 [32] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4,
 163                 [34] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4
 164                         | RTE_PTYPE_L4_UDP,
 165                 [36] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4
 166                         | RTE_PTYPE_L4_TCP,
 167                 [96] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4
 168                         | RTE_PTYPE_L4_FRAG,
 169                 [16] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6,
 170                 [18] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6
 171                         | RTE_PTYPE_L4_UDP,
 172                 [20] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6
 173                         | RTE_PTYPE_L4_TCP,
 174                 [80] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6
 175                         | RTE_PTYPE_L4_FRAG,
 176                 /* All others reserved */
 177         };
 178         cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
 179                 | CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
 180                 | CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
 181         return cq_type_table[cqrd_flags];
 182 }
 183
 184 static inline void
 185 enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
 186 {
 187         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 188         uint16_t ciflags, bwflags, pkt_flags = 0;
 189         ciflags = enic_cq_rx_desc_ciflags(cqrd);
 190         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 191
 192         mbuf->ol_flags = 0;
 193
 194         /* flags are meaningless if !EOP */
 195         if (unlikely(!enic_cq_rx_desc_eop(ciflags)))
 196                 goto mbuf_flags_done;
 197
 198         /* VLAN stripping */
 199         if (bwflags & CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) {
 200                 pkt_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 201                 mbuf->vlan_tci = enic_cq_rx_desc_vlan(cqrd);
 202         } else {
 203                 mbuf->vlan_tci = 0;
 204         }
 205
 206         /* RSS flag */
 207         if (enic_cq_rx_desc_rss_type(cqrd)) {
 208                 pkt_flags |= PKT_RX_RSS_HASH;
 209                 mbuf->hash.rss = enic_cq_rx_desc_rss_hash(cqrd);
 210         }
 211
 212         /* checksum flags */
 213         if (!enic_cq_rx_desc_csum_not_calc(cqrd) &&
 214                 (mbuf->packet_type & RTE_PTYPE_L3_IPV4)) {
 215                 if (unlikely(!enic_cq_rx_desc_ipv4_csum_ok(cqrd)))
 216                         pkt_flags |= PKT_RX_IP_CKSUM_BAD;
 217                 if (mbuf->packet_type & (RTE_PTYPE_L4_UDP | RTE_PTYPE_L4_TCP)) {
 218                         if (unlikely(!enic_cq_rx_desc_tcp_udp_csum_ok(cqrd)))
 219                                 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
 220                 }
 221         }
 222
 223  mbuf_flags_done:
 224         mbuf->ol_flags = pkt_flags;
 225 }
 226
 227 static inline uint32_t
 228 enic_ring_add(uint32_t n_descriptors, uint32_t i0, uint32_t i1)
 229 {
 230         uint32_t d = i0 + i1;
 231         RTE_ASSERT(i0 < n_descriptors);
 232         RTE_ASSERT(i1 < n_descriptors);
 233         d -= (d >= n_descriptors) ? n_descriptors : 0;
 234         return d;
 235 }
 236
 237
 238 uint16_t
 239 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 240                uint16_t nb_pkts)
 241 {
 242         struct vnic_rq *rq = rx_queue;
 243         struct enic *enic = vnic_dev_priv(rq->vdev);
 244         unsigned int rx_id;
 245         struct rte_mbuf *nmb, *rxmb;
 246         uint16_t nb_rx = 0;
 247         uint16_t nb_hold;
 248         struct vnic_cq *cq;
 249         volatile struct cq_desc *cqd_ptr;
 250         uint8_t color;
 251
 252         cq = &enic->cq[enic_cq_rq(enic, rq->index)];
 253         rx_id = cq->to_clean;           /* index of cqd, rqd, mbuf_table */
 254         cqd_ptr = (struct cq_desc *)(cq->ring.descs) + rx_id;
 255
 256         nb_hold = rq->rx_nb_hold;       /* mbufs held by software */
 257
 258         while (nb_rx < nb_pkts) {
 259                 volatile struct rq_enet_desc *rqd_ptr;
 260                 dma_addr_t dma_addr;
 261                 struct cq_desc cqd;
 262                 uint64_t ol_err_flags;
 263                 uint8_t packet_error;
 264
 265                 /* Check for pkts available */
 266                 color = (cqd_ptr->type_color >> CQ_DESC_COLOR_SHIFT)
 267                         & CQ_DESC_COLOR_MASK;
 268                 if (color == cq->last_color)
 269                         break;
 270
 271                 /* Get the cq descriptor and rq pointer */
 272                 cqd = *cqd_ptr;
 273                 rqd_ptr = (struct rq_enet_desc *)(rq->ring.descs) + rx_id;
 274
 275                 /* allocate a new mbuf */
 276                 nmb = rte_mbuf_raw_alloc(rq->mp);
 277                 if (nmb == NULL) {
 278                         dev_err(enic, "RX mbuf alloc failed port=%u qid=%u",
 279                         enic->port_id, (unsigned)rq->index);
 280                         rte_eth_devices[enic->port_id].
 281                                         data->rx_mbuf_alloc_failed++;
 282                         break;
 283                 }
 284
 285                 /* A packet error means descriptor and data are untrusted */
 286                 packet_error = enic_cq_rx_to_pkt_err_flags(&cqd, &ol_err_flags);
 287
 288                 /* Get the mbuf to return and replace with one just allocated */
 289                 rxmb = rq->mbuf_ring[rx_id];
 290                 rq->mbuf_ring[rx_id] = nmb;
 291
 292                 /* Increment cqd, rqd, mbuf_table index */
 293                 rx_id++;
 294                 if (unlikely(rx_id == rq->ring.desc_count)) {
 295                         rx_id = 0;
 296                         cq->last_color = cq->last_color ? 0 : 1;
 297                 }
 298
 299                 /* Prefetch next mbuf & desc while processing current one */
 300                 cqd_ptr = (struct cq_desc *)(cq->ring.descs) + rx_id;
 301                 rte_enic_prefetch(cqd_ptr);
 302                 rte_enic_prefetch(rq->mbuf_ring[rx_id]);
 303                 rte_enic_prefetch((struct rq_enet_desc *)(rq->ring.descs)
 304                                  + rx_id);
 305
 306                 /* Push descriptor for newly allocated mbuf */
 307                 dma_addr = (dma_addr_t)(nmb->buf_physaddr
 308                            + RTE_PKTMBUF_HEADROOM);
 309                 rqd_ptr->address = rte_cpu_to_le_64(dma_addr);
 310                 rqd_ptr->length_type = cpu_to_le16(nmb->buf_len
 311                                        - RTE_PKTMBUF_HEADROOM);
 312
 313                 /* Fill in the rest of the mbuf */
 314                 rxmb->data_off = RTE_PKTMBUF_HEADROOM;
 315                 rxmb->nb_segs = 1;
 316                 rxmb->next = NULL;
 317                 rxmb->port = enic->port_id;
 318                 if (!packet_error) {
 319                         rxmb->pkt_len = enic_cq_rx_desc_n_bytes(&cqd);
 320                         rxmb->packet_type = enic_cq_rx_flags_to_pkt_type(&cqd);
 321                         enic_cq_rx_to_pkt_flags(&cqd, rxmb);
 322                 } else {
 323                         rxmb->pkt_len = 0;
 324                         rxmb->packet_type = 0;
 325                         rxmb->ol_flags = 0;
 326                 }
 327                 rxmb->data_len = rxmb->pkt_len;
 328
 329                 /* prefetch mbuf data for caller */
 330                 rte_packet_prefetch(RTE_PTR_ADD(rxmb->buf_addr,
 331                                     RTE_PKTMBUF_HEADROOM));
 332
 333                 /* store the mbuf address into the next entry of the array */
 334                 rx_pkts[nb_rx++] = rxmb;
 335         }
 336
 337         nb_hold += nb_rx;
 338         cq->to_clean = rx_id;
 339
 340         if (nb_hold > rq->rx_free_thresh) {
 341                 rq->posted_index = enic_ring_add(rq->ring.desc_count,
 342                                 rq->posted_index, nb_hold);
 343                 nb_hold = 0;
 344                 rte_mb();
 345                 iowrite32(rq->posted_index, &rq->ctrl->posted_index);
 346         }
 347
 348         rq->rx_nb_hold = nb_hold;
 349
 350         return nb_rx;
 351 }