drivers/net/enic/enic_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  */
   5
   6 #include <rte_mbuf.h>
   7 #include <rte_ethdev_driver.h>
   8 #include <rte_net.h>
   9 #include <rte_prefetch.h>
  10
  11 #include "enic_compat.h"
  12 #include "rq_enet_desc.h"
  13 #include "enic.h"
  14 #include <rte_ether.h>
  15 #include <rte_ip.h>
  16 #include <rte_tcp.h>
  17
  18 #define RTE_PMD_USE_PREFETCH
  19
  20 #ifdef RTE_PMD_USE_PREFETCH
  21 /*Prefetch a cache line into all cache levels. */
  22 #define rte_enic_prefetch(p) rte_prefetch0(p)
  23 #else
  24 #define rte_enic_prefetch(p) do {} while (0)
  25 #endif
  26
  27 #ifdef RTE_PMD_PACKET_PREFETCH
  28 #define rte_packet_prefetch(p) rte_prefetch1(p)
  29 #else
  30 #define rte_packet_prefetch(p) do {} while (0)
  31 #endif
  32
  33 static inline uint16_t
  34 enic_cq_rx_desc_ciflags(struct cq_enet_rq_desc *crd)
  35 {
  36         return le16_to_cpu(crd->completed_index_flags) & ~CQ_DESC_COMP_NDX_MASK;
  37 }
  38
  39 static inline uint16_t
  40 enic_cq_rx_desc_bwflags(struct cq_enet_rq_desc *crd)
  41 {
  42         return le16_to_cpu(crd->bytes_written_flags) &
  43                            ~CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
  44 }
  45
  46 static inline uint8_t
  47 enic_cq_rx_desc_packet_error(uint16_t bwflags)
  48 {
  49         return (bwflags & CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ==
  50                 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED;
  51 }
  52
  53 static inline uint8_t
  54 enic_cq_rx_desc_eop(uint16_t ciflags)
  55 {
  56         return (ciflags & CQ_ENET_RQ_DESC_FLAGS_EOP)
  57                 == CQ_ENET_RQ_DESC_FLAGS_EOP;
  58 }
  59
  60 static inline uint8_t
  61 enic_cq_rx_desc_csum_not_calc(struct cq_enet_rq_desc *cqrd)
  62 {
  63         return (le16_to_cpu(cqrd->q_number_rss_type_flags) &
  64                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ==
  65                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC;
  66 }
  67
  68 static inline uint8_t
  69 enic_cq_rx_desc_ipv4_csum_ok(struct cq_enet_rq_desc *cqrd)
  70 {
  71         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ==
  72                 CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK;
  73 }
  74
  75 static inline uint8_t
  76 enic_cq_rx_desc_tcp_udp_csum_ok(struct cq_enet_rq_desc *cqrd)
  77 {
  78         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ==
  79                 CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK;
  80 }
  81
  82 static inline uint8_t
  83 enic_cq_rx_desc_rss_type(struct cq_enet_rq_desc *cqrd)
  84 {
  85         return (uint8_t)((le16_to_cpu(cqrd->q_number_rss_type_flags) >>
  86                 CQ_DESC_Q_NUM_BITS) & CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
  87 }
  88
  89 static inline uint32_t
  90 enic_cq_rx_desc_rss_hash(struct cq_enet_rq_desc *cqrd)
  91 {
  92         return le32_to_cpu(cqrd->rss_hash);
  93 }
  94
  95 static inline uint16_t
  96 enic_cq_rx_desc_vlan(struct cq_enet_rq_desc *cqrd)
  97 {
  98         return le16_to_cpu(cqrd->vlan);
  99 }
 100
 101 static inline uint16_t
 102 enic_cq_rx_desc_n_bytes(struct cq_desc *cqd)
 103 {
 104         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 105         return le16_to_cpu(cqrd->bytes_written_flags) &
 106                 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
 107 }
 108
 109
 110 static inline uint8_t
 111 enic_cq_rx_check_err(struct cq_desc *cqd)
 112 {
 113         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 114         uint16_t bwflags;
 115
 116         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 117         if (unlikely(enic_cq_rx_desc_packet_error(bwflags)))
 118                 return 1;
 119         return 0;
 120 }
 121
 122 /* Lookup table to translate RX CQ flags to mbuf flags. */
 123 static inline uint32_t
 124 enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd, uint8_t tnl)
 125 {
 126         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 127         uint8_t cqrd_flags = cqrd->flags;
 128         /*
 129          * Odd-numbered entries are for tunnel packets. All packet type info
 130          * applies to the inner packet, and there is no info on the outer
 131          * packet. The outer flags in these entries exist only to avoid
 132          * changing enic_cq_rx_to_pkt_flags(). They are cleared from mbuf
 133          * afterwards.
 134          *
 135          * Also, as there is no tunnel type info (VXLAN, NVGRE, or GENEVE), set
 136          * RTE_PTYPE_TUNNEL_GRENAT..
 137          */
 138         static const uint32_t cq_type_table[128] __rte_cache_aligned = {
 139                 [0x00] = RTE_PTYPE_UNKNOWN,
 140                 [0x01] = RTE_PTYPE_UNKNOWN |
 141                          RTE_PTYPE_TUNNEL_GRENAT |
 142                          RTE_PTYPE_INNER_L2_ETHER,
 143                 [0x20] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
 144                 [0x21] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG |
 145                          RTE_PTYPE_TUNNEL_GRENAT |
 146                          RTE_PTYPE_INNER_L2_ETHER |
 147                          RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 148                          RTE_PTYPE_INNER_L4_NONFRAG,
 149                 [0x22] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 150                 [0x23] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
 151                          RTE_PTYPE_TUNNEL_GRENAT |
 152                          RTE_PTYPE_INNER_L2_ETHER |
 153                          RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 154                          RTE_PTYPE_INNER_L4_UDP,
 155                 [0x24] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 156                 [0x25] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP |
 157                          RTE_PTYPE_TUNNEL_GRENAT |
 158                          RTE_PTYPE_INNER_L2_ETHER |
 159                          RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 160                          RTE_PTYPE_INNER_L4_TCP,
 161                 [0x60] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 162                 [0x61] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG |
 163                          RTE_PTYPE_TUNNEL_GRENAT |
 164                          RTE_PTYPE_INNER_L2_ETHER |
 165                          RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 166                          RTE_PTYPE_INNER_L4_FRAG,
 167                 [0x62] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 168                 [0x63] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG |
 169                          RTE_PTYPE_TUNNEL_GRENAT |
 170                          RTE_PTYPE_INNER_L2_ETHER |
 171                          RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 172                          RTE_PTYPE_INNER_L4_FRAG,
 173                 [0x64] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 174                 [0x65] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG |
 175                          RTE_PTYPE_TUNNEL_GRENAT |
 176                          RTE_PTYPE_INNER_L2_ETHER |
 177                          RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 178                          RTE_PTYPE_INNER_L4_FRAG,
 179                 [0x10] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
 180                 [0x11] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG |
 181                          RTE_PTYPE_TUNNEL_GRENAT |
 182                          RTE_PTYPE_INNER_L2_ETHER |
 183                          RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 184                          RTE_PTYPE_INNER_L4_NONFRAG,
 185                 [0x12] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 186                 [0x13] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
 187                          RTE_PTYPE_TUNNEL_GRENAT |
 188                          RTE_PTYPE_INNER_L2_ETHER |
 189                          RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 190                          RTE_PTYPE_INNER_L4_UDP,
 191                 [0x14] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 192                 [0x15] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP |
 193                          RTE_PTYPE_TUNNEL_GRENAT |
 194                          RTE_PTYPE_INNER_L2_ETHER |
 195                          RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 196                          RTE_PTYPE_INNER_L4_TCP,
 197                 [0x50] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 198                 [0x51] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG |
 199                          RTE_PTYPE_TUNNEL_GRENAT |
 200                          RTE_PTYPE_INNER_L2_ETHER |
 201                          RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 202                          RTE_PTYPE_INNER_L4_FRAG,
 203                 [0x52] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 204                 [0x53] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG |
 205                          RTE_PTYPE_TUNNEL_GRENAT |
 206                          RTE_PTYPE_INNER_L2_ETHER |
 207                          RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 208                          RTE_PTYPE_INNER_L4_FRAG,
 209                 [0x54] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 210                 [0x55] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG |
 211                          RTE_PTYPE_TUNNEL_GRENAT |
 212                          RTE_PTYPE_INNER_L2_ETHER |
 213                          RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 214                          RTE_PTYPE_INNER_L4_FRAG,
 215                 /* All others reserved */
 216         };
 217         cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
 218                 | CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
 219                 | CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
 220         return cq_type_table[cqrd_flags + tnl];
 221 }
 222
 223 static inline void
 224 enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
 225 {
 226         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 227         uint16_t bwflags, pkt_flags = 0, vlan_tci;
 228         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 229         vlan_tci = enic_cq_rx_desc_vlan(cqrd);
 230
 231         /* VLAN STRIPPED flag. The L2 packet type updated here also */
 232         if (bwflags & CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) {
 233                 pkt_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 234                 mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
 235         } else {
 236                 if (vlan_tci != 0) {
 237                         pkt_flags |= PKT_RX_VLAN;
 238                         mbuf->packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
 239                 } else {
 240                         mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
 241                 }
 242         }
 243         mbuf->vlan_tci = vlan_tci;
 244
 245         if ((cqd->type_color & CQ_DESC_TYPE_MASK) == CQ_DESC_TYPE_CLASSIFIER) {
 246                 struct cq_enet_rq_clsf_desc *clsf_cqd;
 247                 uint16_t filter_id;
 248                 clsf_cqd = (struct cq_enet_rq_clsf_desc *)cqd;
 249                 filter_id = clsf_cqd->filter_id;
 250                 if (filter_id) {
 251                         pkt_flags |= PKT_RX_FDIR;
 252                         if (filter_id != ENIC_MAGIC_FILTER_ID) {
 253                                 mbuf->hash.fdir.hi = clsf_cqd->filter_id;
 254                                 pkt_flags |= PKT_RX_FDIR_ID;
 255                         }
 256                 }
 257         } else if (enic_cq_rx_desc_rss_type(cqrd)) {
 258                 /* RSS flag */
 259                 pkt_flags |= PKT_RX_RSS_HASH;
 260                 mbuf->hash.rss = enic_cq_rx_desc_rss_hash(cqrd);
 261         }
 262
 263         /* checksum flags */
 264         if (mbuf->packet_type & (RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L3_IPV6)) {
 265                 if (!enic_cq_rx_desc_csum_not_calc(cqrd)) {
 266                         uint32_t l4_flags;
 267                         l4_flags = mbuf->packet_type & RTE_PTYPE_L4_MASK;
 268
 269                         /*
 270                          * When overlay offload is enabled, the NIC may
 271                          * set ipv4_csum_ok=1 if the inner packet is IPv6..
 272                          * So, explicitly check for IPv4 before checking
 273                          * ipv4_csum_ok.
 274                          */
 275                         if (mbuf->packet_type & RTE_PTYPE_L3_IPV4) {
 276                                 if (enic_cq_rx_desc_ipv4_csum_ok(cqrd))
 277                                         pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
 278                                 else
 279                                         pkt_flags |= PKT_RX_IP_CKSUM_BAD;
 280                         }
 281
 282                         if (l4_flags == RTE_PTYPE_L4_UDP ||
 283                             l4_flags == RTE_PTYPE_L4_TCP) {
 284                                 if (enic_cq_rx_desc_tcp_udp_csum_ok(cqrd))
 285                                         pkt_flags |= PKT_RX_L4_CKSUM_GOOD;
 286                                 else
 287                                         pkt_flags |= PKT_RX_L4_CKSUM_BAD;
 288                         }
 289                 }
 290         }
 291
 292         mbuf->ol_flags = pkt_flags;
 293 }
 294
 295 /* dummy receive function to replace actual function in
 296  * order to do safe reconfiguration operations.
 297  */
 298 uint16_t
 299 enic_dummy_recv_pkts(__rte_unused void *rx_queue,
 300                      __rte_unused struct rte_mbuf **rx_pkts,
 301                      __rte_unused uint16_t nb_pkts)
 302 {
 303         return 0;
 304 }
 305
 306 uint16_t
 307 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 308                uint16_t nb_pkts)
 309 {
 310         struct vnic_rq *sop_rq = rx_queue;
 311         struct vnic_rq *data_rq;
 312         struct vnic_rq *rq;
 313         struct enic *enic = vnic_dev_priv(sop_rq->vdev);
 314         uint16_t cq_idx;
 315         uint16_t rq_idx, max_rx;
 316         uint16_t rq_num;
 317         struct rte_mbuf *nmb, *rxmb;
 318         uint16_t nb_rx = 0;
 319         struct vnic_cq *cq;
 320         volatile struct cq_desc *cqd_ptr;
 321         uint8_t color;
 322         uint8_t tnl;
 323         uint16_t seg_length;
 324         struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
 325         struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
 326
 327         cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
 328         cq_idx = cq->to_clean;          /* index of cqd, rqd, mbuf_table */
 329         cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
 330         color = cq->last_color;
 331
 332         data_rq = &enic->rq[sop_rq->data_queue_idx];
 333
 334         /* Receive until the end of the ring, at most. */
 335         max_rx = RTE_MIN(nb_pkts, cq->ring.desc_count - cq_idx);
 336
 337         while (max_rx) {
 338                 volatile struct rq_enet_desc *rqd_ptr;
 339                 struct cq_desc cqd;
 340                 uint8_t packet_error;
 341                 uint16_t ciflags;
 342
 343                 max_rx--;
 344
 345                 /* Check for pkts available */
 346                 if ((cqd_ptr->type_color & CQ_DESC_COLOR_MASK_NOSHIFT) == color)
 347                         break;
 348
 349                 /* Get the cq descriptor and extract rq info from it */
 350                 cqd = *cqd_ptr;
 351                 rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
 352                 rq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;
 353
 354                 rq = &enic->rq[rq_num];
 355                 rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
 356
 357                 /* allocate a new mbuf */
 358                 nmb = rte_mbuf_raw_alloc(rq->mp);
 359                 if (nmb == NULL) {
 360                         rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
 361                         break;
 362                 }
 363
 364                 /* A packet error means descriptor and data are untrusted */
 365                 packet_error = enic_cq_rx_check_err(&cqd);
 366
 367                 /* Get the mbuf to return and replace with one just allocated */
 368                 rxmb = rq->mbuf_ring[rq_idx];
 369                 rq->mbuf_ring[rq_idx] = nmb;
 370                 cq_idx++;
 371
 372                 /* Prefetch next mbuf & desc while processing current one */
 373                 cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
 374                 rte_enic_prefetch(cqd_ptr);
 375
 376                 ciflags = enic_cq_rx_desc_ciflags(
 377                         (struct cq_enet_rq_desc *)&cqd);
 378
 379                 /* Push descriptor for newly allocated mbuf */
 380                 nmb->data_off = RTE_PKTMBUF_HEADROOM;
 381                 /*
 382                  * Only the address needs to be refilled. length_type of the
 383                  * descriptor it set during initialization
 384                  * (enic_alloc_rx_queue_mbufs) and does not change.
 385                  */
 386                 rqd_ptr->address = rte_cpu_to_le_64(nmb->buf_iova +
 387                                                     RTE_PKTMBUF_HEADROOM);
 388
 389                 /* Fill in the rest of the mbuf */
 390                 seg_length = enic_cq_rx_desc_n_bytes(&cqd);
 391
 392                 if (rq->is_sop) {
 393                         first_seg = rxmb;
 394                         first_seg->pkt_len = seg_length;
 395                 } else {
 396                         first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
 397                                                         + seg_length);
 398                         first_seg->nb_segs++;
 399                         last_seg->next = rxmb;
 400                 }
 401
 402                 rxmb->port = enic->port_id;
 403                 rxmb->data_len = seg_length;
 404
 405                 rq->rx_nb_hold++;
 406
 407                 if (!(enic_cq_rx_desc_eop(ciflags))) {
 408                         last_seg = rxmb;
 409                         continue;
 410                 }
 411
 412                 /*
 413                  * When overlay offload is enabled, CQ.fcoe indicates the
 414                  * packet is tunnelled.
 415                  */
 416                 tnl = enic->overlay_offload &&
 417                         (ciflags & CQ_ENET_RQ_DESC_FLAGS_FCOE) != 0;
 418                 /* cq rx flags are only valid if eop bit is set */
 419                 first_seg->packet_type =
 420                         enic_cq_rx_flags_to_pkt_type(&cqd, tnl);
 421                 enic_cq_rx_to_pkt_flags(&cqd, first_seg);
 422
 423                 /* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */
 424                 if (tnl) {
 425                         first_seg->packet_type &= ~(RTE_PTYPE_L3_MASK |
 426                                                     RTE_PTYPE_L4_MASK);
 427                 }
 428                 if (unlikely(packet_error)) {
 429                         rte_pktmbuf_free(first_seg);
 430                         rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
 431                         continue;
 432                 }
 433
 434
 435                 /* prefetch mbuf data for caller */
 436                 rte_packet_prefetch(RTE_PTR_ADD(first_seg->buf_addr,
 437                                     RTE_PKTMBUF_HEADROOM));
 438
 439                 /* store the mbuf address into the next entry of the array */
 440                 rx_pkts[nb_rx++] = first_seg;
 441         }
 442         if (unlikely(cq_idx == cq->ring.desc_count)) {
 443                 cq_idx = 0;
 444                 cq->last_color ^= CQ_DESC_COLOR_MASK_NOSHIFT;
 445         }
 446
 447         sop_rq->pkt_first_seg = first_seg;
 448         sop_rq->pkt_last_seg = last_seg;
 449
 450         cq->to_clean = cq_idx;
 451
 452         if ((sop_rq->rx_nb_hold + data_rq->rx_nb_hold) >
 453             sop_rq->rx_free_thresh) {
 454                 if (data_rq->in_use) {
 455                         data_rq->posted_index =
 456                                 enic_ring_add(data_rq->ring.desc_count,
 457                                               data_rq->posted_index,
 458                                               data_rq->rx_nb_hold);
 459                         data_rq->rx_nb_hold = 0;
 460                 }
 461                 sop_rq->posted_index = enic_ring_add(sop_rq->ring.desc_count,
 462                                                      sop_rq->posted_index,
 463                                                      sop_rq->rx_nb_hold);
 464                 sop_rq->rx_nb_hold = 0;
 465
 466                 rte_mb();
 467                 if (data_rq->in_use)
 468                         iowrite32_relaxed(data_rq->posted_index,
 469                                           &data_rq->ctrl->posted_index);
 470                 rte_compiler_barrier();
 471                 iowrite32_relaxed(sop_rq->posted_index,
 472                                   &sop_rq->ctrl->posted_index);
 473         }
 474
 475
 476         return nb_rx;
 477 }
 478
 479 uint16_t
 480 enic_noscatter_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 481                          uint16_t nb_pkts)
 482 {
 483         struct rte_mbuf *mb, **rx, **rxmb;
 484         uint16_t cq_idx, nb_rx, max_rx;
 485         struct cq_enet_rq_desc *cqd;
 486         struct rq_enet_desc *rqd;
 487         unsigned int port_id;
 488         struct vnic_cq *cq;
 489         struct vnic_rq *rq;
 490         struct enic *enic;
 491         uint8_t color;
 492         bool overlay;
 493         bool tnl;
 494
 495         rq = rx_queue;
 496         enic = vnic_dev_priv(rq->vdev);
 497         cq = &enic->cq[enic_cq_rq(enic, rq->index)];
 498         cq_idx = cq->to_clean;
 499
 500         /*
 501          * Fill up the reserve of free mbufs. Below, we restock the receive
 502          * ring with these mbufs to avoid allocation failures.
 503          */
 504         if (rq->num_free_mbufs == 0) {
 505                 if (rte_mempool_get_bulk(rq->mp, (void **)rq->free_mbufs,
 506                                          ENIC_RX_BURST_MAX))
 507                         return 0;
 508                 rq->num_free_mbufs = ENIC_RX_BURST_MAX;
 509         }
 510
 511         /* Receive until the end of the ring, at most. */
 512         max_rx = RTE_MIN(nb_pkts, rq->num_free_mbufs);
 513         max_rx = RTE_MIN(max_rx, cq->ring.desc_count - cq_idx);
 514
 515         cqd = (struct cq_enet_rq_desc *)(cq->ring.descs) + cq_idx;
 516         color = cq->last_color;
 517         rxmb = rq->mbuf_ring + cq_idx;
 518         port_id = enic->port_id;
 519         overlay = enic->overlay_offload;
 520
 521         rx = rx_pkts;
 522         while (max_rx) {
 523                 max_rx--;
 524                 if ((cqd->type_color & CQ_DESC_COLOR_MASK_NOSHIFT) == color)
 525                         break;
 526                 if (unlikely(cqd->bytes_written_flags &
 527                              CQ_ENET_RQ_DESC_FLAGS_TRUNCATED)) {
 528                         rte_pktmbuf_free(*rxmb++);
 529                         rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
 530                         cqd++;
 531                         continue;
 532                 }
 533
 534                 mb = *rxmb++;
 535                 /* prefetch mbuf data for caller */
 536                 rte_packet_prefetch(RTE_PTR_ADD(mb->buf_addr,
 537                                     RTE_PKTMBUF_HEADROOM));
 538                 mb->data_len = cqd->bytes_written_flags &
 539                         CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
 540                 mb->pkt_len = mb->data_len;
 541                 mb->port = port_id;
 542                 tnl = overlay && (cqd->completed_index_flags &
 543                                   CQ_ENET_RQ_DESC_FLAGS_FCOE) != 0;
 544                 mb->packet_type =
 545                         enic_cq_rx_flags_to_pkt_type((struct cq_desc *)cqd,
 546                                                      tnl);
 547                 enic_cq_rx_to_pkt_flags((struct cq_desc *)cqd, mb);
 548                 /* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */
 549                 if (tnl) {
 550                         mb->packet_type &= ~(RTE_PTYPE_L3_MASK |
 551                                              RTE_PTYPE_L4_MASK);
 552                 }
 553                 cqd++;
 554                 *rx++ = mb;
 555         }
 556         /* Number of descriptors visited */
 557         nb_rx = cqd - (struct cq_enet_rq_desc *)(cq->ring.descs) - cq_idx;
 558         if (nb_rx == 0)
 559                 return 0;
 560         rqd = ((struct rq_enet_desc *)rq->ring.descs) + cq_idx;
 561         rxmb = rq->mbuf_ring + cq_idx;
 562         cq_idx += nb_rx;
 563         rq->rx_nb_hold += nb_rx;
 564         if (unlikely(cq_idx == cq->ring.desc_count)) {
 565                 cq_idx = 0;
 566                 cq->last_color ^= CQ_DESC_COLOR_MASK_NOSHIFT;
 567         }
 568         cq->to_clean = cq_idx;
 569
 570         memcpy(rxmb, rq->free_mbufs + ENIC_RX_BURST_MAX - rq->num_free_mbufs,
 571                sizeof(struct rte_mbuf *) * nb_rx);
 572         rq->num_free_mbufs -= nb_rx;
 573         while (nb_rx) {
 574                 nb_rx--;
 575                 mb = *rxmb++;
 576                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 577                 rqd->address = mb->buf_iova + RTE_PKTMBUF_HEADROOM;
 578                 rqd++;
 579         }
 580         if (rq->rx_nb_hold > rq->rx_free_thresh) {
 581                 rq->posted_index = enic_ring_add(rq->ring.desc_count,
 582                                                  rq->posted_index,
 583                                                  rq->rx_nb_hold);
 584                 rq->rx_nb_hold = 0;
 585                 rte_wmb();
 586                 iowrite32_relaxed(rq->posted_index,
 587                                   &rq->ctrl->posted_index);
 588         }
 589
 590         return rx - rx_pkts;
 591 }
 592
 593 static inline void enic_free_wq_bufs(struct vnic_wq *wq, u16 completed_index)
 594 {
 595         struct rte_mbuf *buf;
 596         struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
 597         unsigned int nb_to_free, nb_free = 0, i;
 598         struct rte_mempool *pool;
 599         unsigned int tail_idx;
 600         unsigned int desc_count = wq->ring.desc_count;
 601
 602         nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
 603                                    + 1;
 604         tail_idx = wq->tail_idx;
 605         pool = wq->bufs[tail_idx]->pool;
 606         for (i = 0; i < nb_to_free; i++) {
 607                 buf = wq->bufs[tail_idx];
 608                 m = rte_pktmbuf_prefree_seg(buf);
 609                 if (unlikely(m == NULL)) {
 610                         tail_idx = enic_ring_incr(desc_count, tail_idx);
 611                         continue;
 612                 }
 613
 614                 if (likely(m->pool == pool)) {
 615                         RTE_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
 616                         free[nb_free++] = m;
 617                 } else {
 618                         rte_mempool_put_bulk(pool, (void *)free, nb_free);
 619                         free[0] = m;
 620                         nb_free = 1;
 621                         pool = m->pool;
 622                 }
 623                 tail_idx = enic_ring_incr(desc_count, tail_idx);
 624         }
 625
 626         if (nb_free > 0)
 627                 rte_mempool_put_bulk(pool, (void **)free, nb_free);
 628
 629         wq->tail_idx = tail_idx;
 630         wq->ring.desc_avail += nb_to_free;
 631 }
 632
 633 unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
 634 {
 635         u16 completed_index;
 636
 637         completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
 638
 639         if (wq->last_completed_index != completed_index) {
 640                 enic_free_wq_bufs(wq, completed_index);
 641                 wq->last_completed_index = completed_index;
 642         }
 643         return 0;
 644 }
 645
 646 uint16_t enic_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 647                         uint16_t nb_pkts)
 648 {
 649         struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
 650         int32_t ret;
 651         uint16_t i;
 652         uint64_t ol_flags;
 653         struct rte_mbuf *m;
 654
 655         for (i = 0; i != nb_pkts; i++) {
 656                 m = tx_pkts[i];
 657                 if (unlikely(m->pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
 658                         rte_errno = EINVAL;
 659                         return i;
 660                 }
 661                 ol_flags = m->ol_flags;
 662                 if (ol_flags & wq->tx_offload_notsup_mask) {
 663                         rte_errno = ENOTSUP;
 664                         return i;
 665                 }
 666 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 667                 ret = rte_validate_tx_offload(m);
 668                 if (ret != 0) {
 669                         rte_errno = ret;
 670                         return i;
 671                 }
 672 #endif
 673                 ret = rte_net_intel_cksum_prepare(m);
 674                 if (ret != 0) {
 675                         rte_errno = ret;
 676                         return i;
 677                 }
 678         }
 679
 680         return i;
 681 }
 682
 683 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 684         uint16_t nb_pkts)
 685 {
 686         uint16_t index;
 687         unsigned int pkt_len, data_len;
 688         unsigned int nb_segs;
 689         struct rte_mbuf *tx_pkt;
 690         struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
 691         struct enic *enic = vnic_dev_priv(wq->vdev);
 692         unsigned short vlan_id;
 693         uint64_t ol_flags;
 694         uint64_t ol_flags_mask;
 695         unsigned int wq_desc_avail;
 696         int head_idx;
 697         unsigned int desc_count;
 698         struct wq_enet_desc *descs, *desc_p, desc_tmp;
 699         uint16_t mss;
 700         uint8_t vlan_tag_insert;
 701         uint8_t eop, cq;
 702         uint64_t bus_addr;
 703         uint8_t offload_mode;
 704         uint16_t header_len;
 705         uint64_t tso;
 706         rte_atomic64_t *tx_oversized;
 707
 708         enic_cleanup_wq(enic, wq);
 709         wq_desc_avail = vnic_wq_desc_avail(wq);
 710         head_idx = wq->head_idx;
 711         desc_count = wq->ring.desc_count;
 712         ol_flags_mask = PKT_TX_VLAN_PKT | PKT_TX_IP_CKSUM | PKT_TX_L4_MASK;
 713         tx_oversized = &enic->soft_stats.tx_oversized;
 714
 715         nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
 716
 717         for (index = 0; index < nb_pkts; index++) {
 718                 tx_pkt = *tx_pkts++;
 719                 pkt_len = tx_pkt->pkt_len;
 720                 data_len = tx_pkt->data_len;
 721                 ol_flags = tx_pkt->ol_flags;
 722                 nb_segs = tx_pkt->nb_segs;
 723                 tso = ol_flags & PKT_TX_TCP_SEG;
 724
 725                 /* drop packet if it's too big to send */
 726                 if (unlikely(!tso && pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
 727                         rte_pktmbuf_free(tx_pkt);
 728                         rte_atomic64_inc(tx_oversized);
 729                         continue;
 730                 }
 731
 732                 if (nb_segs > wq_desc_avail) {
 733                         if (index > 0)
 734                                 goto post;
 735                         goto done;
 736                 }
 737
 738                 mss = 0;
 739                 vlan_id = tx_pkt->vlan_tci;
 740                 vlan_tag_insert = !!(ol_flags & PKT_TX_VLAN_PKT);
 741                 bus_addr = (dma_addr_t)
 742                            (tx_pkt->buf_iova + tx_pkt->data_off);
 743
 744                 descs = (struct wq_enet_desc *)wq->ring.descs;
 745                 desc_p = descs + head_idx;
 746
 747                 eop = (data_len == pkt_len);
 748                 offload_mode = WQ_ENET_OFFLOAD_MODE_CSUM;
 749                 header_len = 0;
 750
 751                 if (tso) {
 752                         header_len = tx_pkt->l2_len + tx_pkt->l3_len +
 753                                      tx_pkt->l4_len;
 754
 755                         /* Drop if non-TCP packet or TSO seg size is too big */
 756                         if (unlikely(header_len == 0 || ((tx_pkt->tso_segsz +
 757                             header_len) > ENIC_TX_MAX_PKT_SIZE))) {
 758                                 rte_pktmbuf_free(tx_pkt);
 759                                 rte_atomic64_inc(tx_oversized);
 760                                 continue;
 761                         }
 762
 763                         offload_mode = WQ_ENET_OFFLOAD_MODE_TSO;
 764                         mss = tx_pkt->tso_segsz;
 765                         /* For tunnel, need the size of outer+inner headers */
 766                         if (ol_flags & PKT_TX_TUNNEL_MASK) {
 767                                 header_len += tx_pkt->outer_l2_len +
 768                                         tx_pkt->outer_l3_len;
 769                         }
 770                 }
 771
 772                 if ((ol_flags & ol_flags_mask) && (header_len == 0)) {
 773                         if (ol_flags & PKT_TX_IP_CKSUM)
 774                                 mss |= ENIC_CALC_IP_CKSUM;
 775
 776                         /* Nic uses just 1 bit for UDP and TCP */
 777                         switch (ol_flags & PKT_TX_L4_MASK) {
 778                         case PKT_TX_TCP_CKSUM:
 779                         case PKT_TX_UDP_CKSUM:
 780                                 mss |= ENIC_CALC_TCP_UDP_CKSUM;
 781                                 break;
 782                         }
 783                 }
 784                 wq->cq_pend++;
 785                 cq = 0;
 786                 if (eop && wq->cq_pend >= ENIC_WQ_CQ_THRESH) {
 787                         cq = 1;
 788                         wq->cq_pend = 0;
 789                 }
 790                 wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, header_len,
 791                                  offload_mode, eop, cq, 0, vlan_tag_insert,
 792                                  vlan_id, 0);
 793
 794                 *desc_p = desc_tmp;
 795                 wq->bufs[head_idx] = tx_pkt;
 796                 head_idx = enic_ring_incr(desc_count, head_idx);
 797                 wq_desc_avail--;
 798
 799                 if (!eop) {
 800                         for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
 801                             tx_pkt->next) {
 802                                 data_len = tx_pkt->data_len;
 803
 804                                 wq->cq_pend++;
 805                                 cq = 0;
 806                                 if (tx_pkt->next == NULL) {
 807                                         eop = 1;
 808                                         if (wq->cq_pend >= ENIC_WQ_CQ_THRESH) {
 809                                                 cq = 1;
 810                                                 wq->cq_pend = 0;
 811                                         }
 812                                 }
 813                                 desc_p = descs + head_idx;
 814                                 bus_addr = (dma_addr_t)(tx_pkt->buf_iova
 815                                            + tx_pkt->data_off);
 816                                 wq_enet_desc_enc((struct wq_enet_desc *)
 817                                                  &desc_tmp, bus_addr, data_len,
 818                                                  mss, 0, offload_mode, eop, cq,
 819                                                  0, vlan_tag_insert, vlan_id,
 820                                                  0);
 821
 822                                 *desc_p = desc_tmp;
 823                                 wq->bufs[head_idx] = tx_pkt;
 824                                 head_idx = enic_ring_incr(desc_count, head_idx);
 825                                 wq_desc_avail--;
 826                         }
 827                 }
 828         }
 829  post:
 830         rte_wmb();
 831         iowrite32_relaxed(head_idx, &wq->ctrl->posted_index);
 832  done:
 833         wq->ring.desc_avail = wq_desc_avail;
 834         wq->head_idx = head_idx;
 835
 836         return index;
 837 }
 838
 839 static void enqueue_simple_pkts(struct rte_mbuf **pkts,
 840                                 struct wq_enet_desc *desc,
 841                                 uint16_t n,
 842                                 struct enic *enic)
 843 {
 844         struct rte_mbuf *p;
 845
 846         while (n) {
 847                 n--;
 848                 p = *pkts++;
 849                 desc->address = p->buf_iova + p->data_off;
 850                 desc->length = p->pkt_len;
 851                 /*
 852                  * The app should not send oversized
 853                  * packets. tx_pkt_prepare includes a check as
 854                  * well. But some apps ignore the device max size and
 855                  * tx_pkt_prepare. Oversized packets cause WQ errrors
 856                  * and the NIC ends up disabling the whole WQ. So
 857                  * truncate packets..
 858                  */
 859                 if (unlikely(p->pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
 860                         desc->length = ENIC_TX_MAX_PKT_SIZE;
 861                         rte_atomic64_inc(&enic->soft_stats.tx_oversized);
 862                 }
 863                 desc++;
 864         }
 865 }
 866
 867 uint16_t enic_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 868                                uint16_t nb_pkts)
 869 {
 870         unsigned int head_idx, desc_count;
 871         struct wq_enet_desc *desc;
 872         struct vnic_wq *wq;
 873         struct enic *enic;
 874         uint16_t rem, n;
 875
 876         wq = (struct vnic_wq *)tx_queue;
 877         enic = vnic_dev_priv(wq->vdev);
 878         enic_cleanup_wq(enic, wq);
 879         /* Will enqueue this many packets in this call */
 880         nb_pkts = RTE_MIN(nb_pkts, wq->ring.desc_avail);
 881         if (nb_pkts == 0)
 882                 return 0;
 883
 884         head_idx = wq->head_idx;
 885         desc_count = wq->ring.desc_count;
 886
 887         /* Descriptors until the end of the ring */
 888         n = desc_count - head_idx;
 889         n = RTE_MIN(nb_pkts, n);
 890
 891         /* Save mbuf pointers to free later */
 892         memcpy(wq->bufs + head_idx, tx_pkts, sizeof(struct rte_mbuf *) * n);
 893
 894         /* Enqueue until the ring end */
 895         rem = nb_pkts - n;
 896         desc = ((struct wq_enet_desc *)wq->ring.descs) + head_idx;
 897         enqueue_simple_pkts(tx_pkts, desc, n, enic);
 898
 899         /* Wrap to the start of the ring */
 900         if (rem) {
 901                 tx_pkts += n;
 902                 memcpy(wq->bufs, tx_pkts, sizeof(struct rte_mbuf *) * rem);
 903                 desc = (struct wq_enet_desc *)wq->ring.descs;
 904                 enqueue_simple_pkts(tx_pkts, desc, rem, enic);
 905         }
 906         rte_wmb();
 907
 908         /* Update head_idx and desc_avail */
 909         wq->ring.desc_avail -= nb_pkts;
 910         head_idx += nb_pkts;
 911         if (head_idx >= desc_count)
 912                 head_idx -= desc_count;
 913         wq->head_idx = head_idx;
 914         iowrite32_relaxed(head_idx, &wq->ctrl->posted_index);
 915         return nb_pkts;
 916 }