1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
7 #include <ethdev_driver.h>
9 #include <rte_prefetch.h>
11 #include "enic_compat.h"
12 #include "rq_enet_desc.h"
14 #include "enic_rxtx_common.h"
15 #include <rte_ether.h>
19 #define RTE_PMD_USE_PREFETCH
21 #ifdef RTE_PMD_USE_PREFETCH
22 /*Prefetch a cache line into all cache levels. */
23 #define rte_enic_prefetch(p) rte_prefetch0(p)
25 #define rte_enic_prefetch(p) do {} while (0)
28 #ifdef RTE_PMD_PACKET_PREFETCH
29 #define rte_packet_prefetch(p) rte_prefetch1(p)
31 #define rte_packet_prefetch(p) do {} while (0)
34 static inline uint16_t
35 enic_recv_pkts_common(void *rx_queue, struct rte_mbuf **rx_pkts,
36 uint16_t nb_pkts, const bool use_64b_desc)
38 struct vnic_rq *sop_rq = rx_queue;
39 struct vnic_rq *data_rq;
41 struct enic *enic = vnic_dev_priv(sop_rq->vdev);
43 uint16_t rq_idx, max_rx;
45 struct rte_mbuf *nmb, *rxmb;
48 volatile struct cq_desc *cqd_ptr;
52 struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
53 struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
54 const int desc_size = use_64b_desc ?
55 sizeof(struct cq_enet_rq_desc_64) :
56 sizeof(struct cq_enet_rq_desc);
57 RTE_BUILD_BUG_ON(sizeof(struct cq_enet_rq_desc_64) != 64);
59 cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
60 cq_idx = cq->to_clean; /* index of cqd, rqd, mbuf_table */
61 cqd_ptr = (struct cq_desc *)((uintptr_t)(cq->ring.descs) +
62 (uintptr_t)cq_idx * desc_size);
63 color = cq->last_color;
65 data_rq = &enic->rq[sop_rq->data_queue_idx];
67 /* Receive until the end of the ring, at most. */
68 max_rx = RTE_MIN(nb_pkts, cq->ring.desc_count - cq_idx);
71 volatile struct rq_enet_desc *rqd_ptr;
76 uint16_t rq_idx_msbs = 0;
80 tc = *(volatile uint8_t *)((uintptr_t)cqd_ptr + desc_size - 1);
81 /* Check for pkts available */
82 if ((tc & CQ_DESC_COLOR_MASK_NOSHIFT) == color)
85 /* Get the cq descriptor and extract rq info from it */
89 * The first 16B of a 64B descriptor is identical to a 16B
90 * descriptor except for the type_color and fetch index. Extract
91 * fetch index and copy the type_color from the 64B to where it
92 * would be in a 16B descriptor so sebwequent code can run
93 * without further conditionals.
96 rq_idx_msbs = (((volatile struct cq_enet_rq_desc_64 *)
97 cqd_ptr)->fetch_idx_flags
98 & CQ_ENET_RQ_DESC_FETCH_IDX_MASK)
99 << CQ_DESC_COMP_NDX_BITS;
102 rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
103 rq_idx = rq_idx_msbs +
104 (cqd.completed_index & CQ_DESC_COMP_NDX_MASK);
106 rq = &enic->rq[rq_num];
107 rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
109 /* allocate a new mbuf */
110 nmb = rte_mbuf_raw_alloc(rq->mp);
112 rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
116 /* A packet error means descriptor and data are untrusted */
117 packet_error = enic_cq_rx_check_err(&cqd);
119 /* Get the mbuf to return and replace with one just allocated */
120 rxmb = rq->mbuf_ring[rq_idx];
121 rq->mbuf_ring[rq_idx] = nmb;
124 /* Prefetch next mbuf & desc while processing current one */
125 cqd_ptr = (struct cq_desc *)((uintptr_t)(cq->ring.descs) +
126 (uintptr_t)cq_idx * desc_size);
127 rte_enic_prefetch(cqd_ptr);
129 ciflags = enic_cq_rx_desc_ciflags(
130 (struct cq_enet_rq_desc *)&cqd);
132 /* Push descriptor for newly allocated mbuf */
133 nmb->data_off = RTE_PKTMBUF_HEADROOM;
135 * Only the address needs to be refilled. length_type of the
136 * descriptor it set during initialization
137 * (enic_alloc_rx_queue_mbufs) and does not change.
139 rqd_ptr->address = rte_cpu_to_le_64(nmb->buf_iova +
140 RTE_PKTMBUF_HEADROOM);
142 /* Fill in the rest of the mbuf */
143 seg_length = enic_cq_rx_desc_n_bytes(&cqd);
147 first_seg->pkt_len = seg_length;
149 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
151 first_seg->nb_segs++;
152 last_seg->next = rxmb;
155 rxmb->port = enic->port_id;
156 rxmb->data_len = seg_length;
160 if (!(enic_cq_rx_desc_eop(ciflags))) {
166 * When overlay offload is enabled, CQ.fcoe indicates the
167 * packet is tunnelled.
169 tnl = enic->overlay_offload &&
170 (ciflags & CQ_ENET_RQ_DESC_FLAGS_FCOE) != 0;
171 /* cq rx flags are only valid if eop bit is set */
172 first_seg->packet_type =
173 enic_cq_rx_flags_to_pkt_type(&cqd, tnl);
174 enic_cq_rx_to_pkt_flags(&cqd, first_seg);
176 /* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */
178 first_seg->packet_type &= ~(RTE_PTYPE_L3_MASK |
181 if (unlikely(packet_error)) {
182 rte_pktmbuf_free(first_seg);
183 rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
188 /* prefetch mbuf data for caller */
189 rte_packet_prefetch(RTE_PTR_ADD(first_seg->buf_addr,
190 RTE_PKTMBUF_HEADROOM));
192 /* store the mbuf address into the next entry of the array */
193 rx_pkts[nb_rx++] = first_seg;
195 if (unlikely(cq_idx == cq->ring.desc_count)) {
197 cq->last_color ^= CQ_DESC_COLOR_MASK_NOSHIFT;
200 sop_rq->pkt_first_seg = first_seg;
201 sop_rq->pkt_last_seg = last_seg;
203 cq->to_clean = cq_idx;
205 if ((sop_rq->rx_nb_hold + data_rq->rx_nb_hold) >
206 sop_rq->rx_free_thresh) {
207 if (data_rq->in_use) {
208 data_rq->posted_index =
209 enic_ring_add(data_rq->ring.desc_count,
210 data_rq->posted_index,
211 data_rq->rx_nb_hold);
212 data_rq->rx_nb_hold = 0;
214 sop_rq->posted_index = enic_ring_add(sop_rq->ring.desc_count,
215 sop_rq->posted_index,
217 sop_rq->rx_nb_hold = 0;
221 iowrite32_relaxed(data_rq->posted_index,
222 &data_rq->ctrl->posted_index);
223 rte_compiler_barrier();
224 iowrite32_relaxed(sop_rq->posted_index,
225 &sop_rq->ctrl->posted_index);
233 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
235 return enic_recv_pkts_common(rx_queue, rx_pkts, nb_pkts, false);
239 enic_recv_pkts_64(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
241 return enic_recv_pkts_common(rx_queue, rx_pkts, nb_pkts, true);
245 enic_noscatter_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
248 struct rte_mbuf *mb, **rx, **rxmb;
249 uint16_t cq_idx, nb_rx, max_rx;
250 struct cq_enet_rq_desc *cqd;
251 struct rq_enet_desc *rqd;
252 unsigned int port_id;
261 enic = vnic_dev_priv(rq->vdev);
262 cq = &enic->cq[enic_cq_rq(enic, rq->index)];
263 cq_idx = cq->to_clean;
266 * Fill up the reserve of free mbufs. Below, we restock the receive
267 * ring with these mbufs to avoid allocation failures.
269 if (rq->num_free_mbufs == 0) {
270 if (rte_mempool_get_bulk(rq->mp, (void **)rq->free_mbufs,
273 rq->num_free_mbufs = ENIC_RX_BURST_MAX;
276 /* Receive until the end of the ring, at most. */
277 max_rx = RTE_MIN(nb_pkts, rq->num_free_mbufs);
278 max_rx = RTE_MIN(max_rx, cq->ring.desc_count - cq_idx);
280 cqd = (struct cq_enet_rq_desc *)(cq->ring.descs) + cq_idx;
281 color = cq->last_color;
282 rxmb = rq->mbuf_ring + cq_idx;
283 port_id = enic->port_id;
284 overlay = enic->overlay_offload;
289 if ((cqd->type_color & CQ_DESC_COLOR_MASK_NOSHIFT) == color)
291 if (unlikely(cqd->bytes_written_flags &
292 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED)) {
293 rte_pktmbuf_free(*rxmb++);
294 rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
300 /* prefetch mbuf data for caller */
301 rte_packet_prefetch(RTE_PTR_ADD(mb->buf_addr,
302 RTE_PKTMBUF_HEADROOM));
303 mb->data_len = cqd->bytes_written_flags &
304 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
305 mb->pkt_len = mb->data_len;
307 tnl = overlay && (cqd->completed_index_flags &
308 CQ_ENET_RQ_DESC_FLAGS_FCOE) != 0;
310 enic_cq_rx_flags_to_pkt_type((struct cq_desc *)cqd,
312 enic_cq_rx_to_pkt_flags((struct cq_desc *)cqd, mb);
313 /* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */
315 mb->packet_type &= ~(RTE_PTYPE_L3_MASK |
321 /* Number of descriptors visited */
322 nb_rx = cqd - (struct cq_enet_rq_desc *)(cq->ring.descs) - cq_idx;
325 rqd = ((struct rq_enet_desc *)rq->ring.descs) + cq_idx;
326 rxmb = rq->mbuf_ring + cq_idx;
328 rq->rx_nb_hold += nb_rx;
329 if (unlikely(cq_idx == cq->ring.desc_count)) {
331 cq->last_color ^= CQ_DESC_COLOR_MASK_NOSHIFT;
333 cq->to_clean = cq_idx;
335 memcpy(rxmb, rq->free_mbufs + ENIC_RX_BURST_MAX - rq->num_free_mbufs,
336 sizeof(struct rte_mbuf *) * nb_rx);
337 rq->num_free_mbufs -= nb_rx;
341 mb->data_off = RTE_PKTMBUF_HEADROOM;
342 rqd->address = mb->buf_iova + RTE_PKTMBUF_HEADROOM;
345 if (rq->rx_nb_hold > rq->rx_free_thresh) {
346 rq->posted_index = enic_ring_add(rq->ring.desc_count,
351 iowrite32_relaxed(rq->posted_index,
352 &rq->ctrl->posted_index);
358 static inline void enic_free_wq_bufs(struct vnic_wq *wq,
359 uint16_t completed_index)
361 struct rte_mbuf *buf;
362 struct rte_mbuf *m, *free[ENIC_LEGACY_MAX_WQ_DESCS];
363 unsigned int nb_to_free, nb_free = 0, i;
364 struct rte_mempool *pool;
365 unsigned int tail_idx;
366 unsigned int desc_count = wq->ring.desc_count;
369 * On 1500 Series VIC and beyond, greater than ENIC_LEGACY_MAX_WQ_DESCS
370 * may be attempted to be freed. Cap it at ENIC_LEGACY_MAX_WQ_DESCS.
372 nb_to_free = RTE_MIN(enic_ring_sub(desc_count, wq->tail_idx,
373 completed_index) + 1,
374 (uint32_t)ENIC_LEGACY_MAX_WQ_DESCS);
375 tail_idx = wq->tail_idx;
376 pool = wq->bufs[tail_idx]->pool;
377 for (i = 0; i < nb_to_free; i++) {
378 buf = wq->bufs[tail_idx];
379 m = rte_pktmbuf_prefree_seg(buf);
380 if (unlikely(m == NULL)) {
381 tail_idx = enic_ring_incr(desc_count, tail_idx);
385 if (likely(m->pool == pool)) {
386 RTE_ASSERT(nb_free < ENIC_LEGACY_MAX_WQ_DESCS);
389 rte_mempool_put_bulk(pool, (void *)free, nb_free);
394 tail_idx = enic_ring_incr(desc_count, tail_idx);
398 rte_mempool_put_bulk(pool, (void **)free, nb_free);
400 wq->tail_idx = tail_idx;
401 wq->ring.desc_avail += nb_to_free;
404 unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
406 uint16_t completed_index;
408 completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
410 if (wq->last_completed_index != completed_index) {
411 enic_free_wq_bufs(wq, completed_index);
412 wq->last_completed_index = completed_index;
417 uint16_t enic_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
420 struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
426 for (i = 0; i != nb_pkts; i++) {
428 ol_flags = m->ol_flags;
429 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
430 if (unlikely(m->pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
437 header_len = m->l2_len + m->l3_len + m->l4_len;
438 if (m->tso_segsz + header_len > ENIC_TX_MAX_PKT_SIZE) {
444 if (ol_flags & wq->tx_offload_notsup_mask) {
448 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
449 ret = rte_validate_tx_offload(m);
455 ret = rte_net_intel_cksum_prepare(m);
465 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
469 unsigned int pkt_len, data_len;
470 unsigned int nb_segs;
471 struct rte_mbuf *tx_pkt;
472 struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
473 struct enic *enic = vnic_dev_priv(wq->vdev);
474 unsigned short vlan_id;
476 uint64_t ol_flags_mask;
477 unsigned int wq_desc_avail;
479 unsigned int desc_count;
480 struct wq_enet_desc *descs, *desc_p, desc_tmp;
482 uint8_t vlan_tag_insert;
485 uint8_t offload_mode;
488 rte_atomic64_t *tx_oversized;
490 enic_cleanup_wq(enic, wq);
491 wq_desc_avail = vnic_wq_desc_avail(wq);
492 head_idx = wq->head_idx;
493 desc_count = wq->ring.desc_count;
494 ol_flags_mask = RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK;
495 tx_oversized = &enic->soft_stats.tx_oversized;
497 nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
499 for (index = 0; index < nb_pkts; index++) {
501 pkt_len = tx_pkt->pkt_len;
502 data_len = tx_pkt->data_len;
503 ol_flags = tx_pkt->ol_flags;
504 nb_segs = tx_pkt->nb_segs;
505 tso = ol_flags & RTE_MBUF_F_TX_TCP_SEG;
507 /* drop packet if it's too big to send */
508 if (unlikely(!tso && pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
509 rte_pktmbuf_free(tx_pkt);
510 rte_atomic64_inc(tx_oversized);
514 if (nb_segs > wq_desc_avail) {
521 vlan_id = tx_pkt->vlan_tci;
522 vlan_tag_insert = !!(ol_flags & RTE_MBUF_F_TX_VLAN);
523 bus_addr = (dma_addr_t)
524 (tx_pkt->buf_iova + tx_pkt->data_off);
526 descs = (struct wq_enet_desc *)wq->ring.descs;
527 desc_p = descs + head_idx;
529 eop = (data_len == pkt_len);
530 offload_mode = WQ_ENET_OFFLOAD_MODE_CSUM;
534 header_len = tx_pkt->l2_len + tx_pkt->l3_len +
537 /* Drop if non-TCP packet or TSO seg size is too big */
538 if (unlikely(header_len == 0 || ((tx_pkt->tso_segsz +
539 header_len) > ENIC_TX_MAX_PKT_SIZE))) {
540 rte_pktmbuf_free(tx_pkt);
541 rte_atomic64_inc(tx_oversized);
545 offload_mode = WQ_ENET_OFFLOAD_MODE_TSO;
546 mss = tx_pkt->tso_segsz;
547 /* For tunnel, need the size of outer+inner headers */
548 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
549 header_len += tx_pkt->outer_l2_len +
550 tx_pkt->outer_l3_len;
554 if ((ol_flags & ol_flags_mask) && (header_len == 0)) {
555 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM)
556 mss |= ENIC_CALC_IP_CKSUM;
558 /* Nic uses just 1 bit for UDP and TCP */
559 switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
560 case RTE_MBUF_F_TX_TCP_CKSUM:
561 case RTE_MBUF_F_TX_UDP_CKSUM:
562 mss |= ENIC_CALC_TCP_UDP_CKSUM;
568 if (eop && wq->cq_pend >= ENIC_WQ_CQ_THRESH) {
572 wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, header_len,
573 offload_mode, eop, cq, 0, vlan_tag_insert,
577 wq->bufs[head_idx] = tx_pkt;
578 head_idx = enic_ring_incr(desc_count, head_idx);
582 for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
584 data_len = tx_pkt->data_len;
588 if (tx_pkt->next == NULL) {
590 if (wq->cq_pend >= ENIC_WQ_CQ_THRESH) {
595 desc_p = descs + head_idx;
596 bus_addr = (dma_addr_t)(tx_pkt->buf_iova
598 wq_enet_desc_enc((struct wq_enet_desc *)
599 &desc_tmp, bus_addr, data_len,
600 mss, 0, offload_mode, eop, cq,
601 0, vlan_tag_insert, vlan_id,
605 wq->bufs[head_idx] = tx_pkt;
606 head_idx = enic_ring_incr(desc_count, head_idx);
613 iowrite32_relaxed(head_idx, &wq->ctrl->posted_index);
615 wq->ring.desc_avail = wq_desc_avail;
616 wq->head_idx = head_idx;
621 static void enqueue_simple_pkts(struct rte_mbuf **pkts,
622 struct wq_enet_desc *desc,
632 desc->address = p->buf_iova + p->data_off;
633 desc->length = p->pkt_len;
635 desc->vlan_tag = p->vlan_tci;
636 desc->header_length_flags &=
637 ((1 << WQ_ENET_FLAGS_EOP_SHIFT) |
638 (1 << WQ_ENET_FLAGS_CQ_ENTRY_SHIFT));
639 if (p->ol_flags & RTE_MBUF_F_TX_VLAN) {
640 desc->header_length_flags |=
641 1 << WQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT;
644 * Checksum offload. We use WQ_ENET_OFFLOAD_MODE_CSUM, which
645 * is 0, so no need to set offload_mode.
648 if (p->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)
649 mss |= ENIC_CALC_IP_CKSUM << WQ_ENET_MSS_SHIFT;
650 if (p->ol_flags & RTE_MBUF_F_TX_L4_MASK)
651 mss |= ENIC_CALC_TCP_UDP_CKSUM << WQ_ENET_MSS_SHIFT;
652 desc->mss_loopback = mss;
655 * The app should not send oversized
656 * packets. tx_pkt_prepare includes a check as
657 * well. But some apps ignore the device max size and
658 * tx_pkt_prepare. Oversized packets cause WQ errors
659 * and the NIC ends up disabling the whole WQ. So
662 if (unlikely(p->pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
663 desc->length = ENIC_TX_MAX_PKT_SIZE;
664 rte_atomic64_inc(&enic->soft_stats.tx_oversized);
670 uint16_t enic_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
673 unsigned int head_idx, desc_count;
674 struct wq_enet_desc *desc;
679 wq = (struct vnic_wq *)tx_queue;
680 enic = vnic_dev_priv(wq->vdev);
681 enic_cleanup_wq(enic, wq);
682 /* Will enqueue this many packets in this call */
683 nb_pkts = RTE_MIN(nb_pkts, wq->ring.desc_avail);
687 head_idx = wq->head_idx;
688 desc_count = wq->ring.desc_count;
690 /* Descriptors until the end of the ring */
691 n = desc_count - head_idx;
692 n = RTE_MIN(nb_pkts, n);
694 /* Save mbuf pointers to free later */
695 memcpy(wq->bufs + head_idx, tx_pkts, sizeof(struct rte_mbuf *) * n);
697 /* Enqueue until the ring end */
699 desc = ((struct wq_enet_desc *)wq->ring.descs) + head_idx;
700 enqueue_simple_pkts(tx_pkts, desc, n, enic);
702 /* Wrap to the start of the ring */
705 memcpy(wq->bufs, tx_pkts, sizeof(struct rte_mbuf *) * rem);
706 desc = (struct wq_enet_desc *)wq->ring.descs;
707 enqueue_simple_pkts(tx_pkts, desc, rem, enic);
711 /* Update head_idx and desc_avail */
712 wq->ring.desc_avail -= nb_pkts;
714 if (head_idx >= desc_count)
715 head_idx -= desc_count;
716 wq->head_idx = head_idx;
717 iowrite32_relaxed(head_idx, &wq->ctrl->posted_index);