1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
7 #include <ethdev_driver.h>
9 #include <rte_prefetch.h>
11 #include "enic_compat.h"
12 #include "rq_enet_desc.h"
14 #include "enic_rxtx_common.h"
15 #include <rte_ether.h>
19 #define RTE_PMD_USE_PREFETCH
21 #ifdef RTE_PMD_USE_PREFETCH
22 /*Prefetch a cache line into all cache levels. */
23 #define rte_enic_prefetch(p) rte_prefetch0(p)
25 #define rte_enic_prefetch(p) do {} while (0)
28 #ifdef RTE_PMD_PACKET_PREFETCH
29 #define rte_packet_prefetch(p) rte_prefetch1(p)
31 #define rte_packet_prefetch(p) do {} while (0)
34 /* dummy receive function to replace actual function in
35 * order to do safe reconfiguration operations.
38 enic_dummy_recv_pkts(__rte_unused void *rx_queue,
39 __rte_unused struct rte_mbuf **rx_pkts,
40 __rte_unused uint16_t nb_pkts)
45 static inline uint16_t
46 enic_recv_pkts_common(void *rx_queue, struct rte_mbuf **rx_pkts,
47 uint16_t nb_pkts, const bool use_64b_desc)
49 struct vnic_rq *sop_rq = rx_queue;
50 struct vnic_rq *data_rq;
52 struct enic *enic = vnic_dev_priv(sop_rq->vdev);
54 uint16_t rq_idx, max_rx;
56 struct rte_mbuf *nmb, *rxmb;
59 volatile struct cq_desc *cqd_ptr;
63 struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
64 struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
65 const int desc_size = use_64b_desc ?
66 sizeof(struct cq_enet_rq_desc_64) :
67 sizeof(struct cq_enet_rq_desc);
68 RTE_BUILD_BUG_ON(sizeof(struct cq_enet_rq_desc_64) != 64);
70 cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
71 cq_idx = cq->to_clean; /* index of cqd, rqd, mbuf_table */
72 cqd_ptr = (struct cq_desc *)((uintptr_t)(cq->ring.descs) +
74 color = cq->last_color;
76 data_rq = &enic->rq[sop_rq->data_queue_idx];
78 /* Receive until the end of the ring, at most. */
79 max_rx = RTE_MIN(nb_pkts, cq->ring.desc_count - cq_idx);
82 volatile struct rq_enet_desc *rqd_ptr;
90 tc = *(volatile uint8_t *)((uintptr_t)cqd_ptr + desc_size - 1);
91 /* Check for pkts available */
92 if ((tc & CQ_DESC_COLOR_MASK_NOSHIFT) == color)
95 /* Get the cq descriptor and extract rq info from it */
98 * The first 16B of 64B descriptor is identical to the
99 * 16B descriptor, except type_color. Copy type_color
100 * from the 64B descriptor into the 16B descriptor's
101 * field, so the code below can assume the 16B
106 rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
107 rq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;
109 rq = &enic->rq[rq_num];
110 rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
112 /* allocate a new mbuf */
113 nmb = rte_mbuf_raw_alloc(rq->mp);
115 rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
119 /* A packet error means descriptor and data are untrusted */
120 packet_error = enic_cq_rx_check_err(&cqd);
122 /* Get the mbuf to return and replace with one just allocated */
123 rxmb = rq->mbuf_ring[rq_idx];
124 rq->mbuf_ring[rq_idx] = nmb;
127 /* Prefetch next mbuf & desc while processing current one */
128 cqd_ptr = (struct cq_desc *)((uintptr_t)(cq->ring.descs) +
130 rte_enic_prefetch(cqd_ptr);
132 ciflags = enic_cq_rx_desc_ciflags(
133 (struct cq_enet_rq_desc *)&cqd);
135 /* Push descriptor for newly allocated mbuf */
136 nmb->data_off = RTE_PKTMBUF_HEADROOM;
138 * Only the address needs to be refilled. length_type of the
139 * descriptor it set during initialization
140 * (enic_alloc_rx_queue_mbufs) and does not change.
142 rqd_ptr->address = rte_cpu_to_le_64(nmb->buf_iova +
143 RTE_PKTMBUF_HEADROOM);
145 /* Fill in the rest of the mbuf */
146 seg_length = enic_cq_rx_desc_n_bytes(&cqd);
150 first_seg->pkt_len = seg_length;
152 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
154 first_seg->nb_segs++;
155 last_seg->next = rxmb;
158 rxmb->port = enic->port_id;
159 rxmb->data_len = seg_length;
163 if (!(enic_cq_rx_desc_eop(ciflags))) {
169 * When overlay offload is enabled, CQ.fcoe indicates the
170 * packet is tunnelled.
172 tnl = enic->overlay_offload &&
173 (ciflags & CQ_ENET_RQ_DESC_FLAGS_FCOE) != 0;
174 /* cq rx flags are only valid if eop bit is set */
175 first_seg->packet_type =
176 enic_cq_rx_flags_to_pkt_type(&cqd, tnl);
177 enic_cq_rx_to_pkt_flags(&cqd, first_seg);
179 /* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */
181 first_seg->packet_type &= ~(RTE_PTYPE_L3_MASK |
184 if (unlikely(packet_error)) {
185 rte_pktmbuf_free(first_seg);
186 rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
191 /* prefetch mbuf data for caller */
192 rte_packet_prefetch(RTE_PTR_ADD(first_seg->buf_addr,
193 RTE_PKTMBUF_HEADROOM));
195 /* store the mbuf address into the next entry of the array */
196 rx_pkts[nb_rx++] = first_seg;
198 if (unlikely(cq_idx == cq->ring.desc_count)) {
200 cq->last_color ^= CQ_DESC_COLOR_MASK_NOSHIFT;
203 sop_rq->pkt_first_seg = first_seg;
204 sop_rq->pkt_last_seg = last_seg;
206 cq->to_clean = cq_idx;
208 if ((sop_rq->rx_nb_hold + data_rq->rx_nb_hold) >
209 sop_rq->rx_free_thresh) {
210 if (data_rq->in_use) {
211 data_rq->posted_index =
212 enic_ring_add(data_rq->ring.desc_count,
213 data_rq->posted_index,
214 data_rq->rx_nb_hold);
215 data_rq->rx_nb_hold = 0;
217 sop_rq->posted_index = enic_ring_add(sop_rq->ring.desc_count,
218 sop_rq->posted_index,
220 sop_rq->rx_nb_hold = 0;
224 iowrite32_relaxed(data_rq->posted_index,
225 &data_rq->ctrl->posted_index);
226 rte_compiler_barrier();
227 iowrite32_relaxed(sop_rq->posted_index,
228 &sop_rq->ctrl->posted_index);
236 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
238 return enic_recv_pkts_common(rx_queue, rx_pkts, nb_pkts, false);
242 enic_recv_pkts_64(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
244 return enic_recv_pkts_common(rx_queue, rx_pkts, nb_pkts, true);
248 enic_noscatter_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
251 struct rte_mbuf *mb, **rx, **rxmb;
252 uint16_t cq_idx, nb_rx, max_rx;
253 struct cq_enet_rq_desc *cqd;
254 struct rq_enet_desc *rqd;
255 unsigned int port_id;
264 enic = vnic_dev_priv(rq->vdev);
265 cq = &enic->cq[enic_cq_rq(enic, rq->index)];
266 cq_idx = cq->to_clean;
269 * Fill up the reserve of free mbufs. Below, we restock the receive
270 * ring with these mbufs to avoid allocation failures.
272 if (rq->num_free_mbufs == 0) {
273 if (rte_mempool_get_bulk(rq->mp, (void **)rq->free_mbufs,
276 rq->num_free_mbufs = ENIC_RX_BURST_MAX;
279 /* Receive until the end of the ring, at most. */
280 max_rx = RTE_MIN(nb_pkts, rq->num_free_mbufs);
281 max_rx = RTE_MIN(max_rx, cq->ring.desc_count - cq_idx);
283 cqd = (struct cq_enet_rq_desc *)(cq->ring.descs) + cq_idx;
284 color = cq->last_color;
285 rxmb = rq->mbuf_ring + cq_idx;
286 port_id = enic->port_id;
287 overlay = enic->overlay_offload;
292 if ((cqd->type_color & CQ_DESC_COLOR_MASK_NOSHIFT) == color)
294 if (unlikely(cqd->bytes_written_flags &
295 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED)) {
296 rte_pktmbuf_free(*rxmb++);
297 rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
303 /* prefetch mbuf data for caller */
304 rte_packet_prefetch(RTE_PTR_ADD(mb->buf_addr,
305 RTE_PKTMBUF_HEADROOM));
306 mb->data_len = cqd->bytes_written_flags &
307 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
308 mb->pkt_len = mb->data_len;
310 tnl = overlay && (cqd->completed_index_flags &
311 CQ_ENET_RQ_DESC_FLAGS_FCOE) != 0;
313 enic_cq_rx_flags_to_pkt_type((struct cq_desc *)cqd,
315 enic_cq_rx_to_pkt_flags((struct cq_desc *)cqd, mb);
316 /* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */
318 mb->packet_type &= ~(RTE_PTYPE_L3_MASK |
324 /* Number of descriptors visited */
325 nb_rx = cqd - (struct cq_enet_rq_desc *)(cq->ring.descs) - cq_idx;
328 rqd = ((struct rq_enet_desc *)rq->ring.descs) + cq_idx;
329 rxmb = rq->mbuf_ring + cq_idx;
331 rq->rx_nb_hold += nb_rx;
332 if (unlikely(cq_idx == cq->ring.desc_count)) {
334 cq->last_color ^= CQ_DESC_COLOR_MASK_NOSHIFT;
336 cq->to_clean = cq_idx;
338 memcpy(rxmb, rq->free_mbufs + ENIC_RX_BURST_MAX - rq->num_free_mbufs,
339 sizeof(struct rte_mbuf *) * nb_rx);
340 rq->num_free_mbufs -= nb_rx;
344 mb->data_off = RTE_PKTMBUF_HEADROOM;
345 rqd->address = mb->buf_iova + RTE_PKTMBUF_HEADROOM;
348 if (rq->rx_nb_hold > rq->rx_free_thresh) {
349 rq->posted_index = enic_ring_add(rq->ring.desc_count,
354 iowrite32_relaxed(rq->posted_index,
355 &rq->ctrl->posted_index);
361 static inline void enic_free_wq_bufs(struct vnic_wq *wq,
362 uint16_t completed_index)
364 struct rte_mbuf *buf;
365 struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
366 unsigned int nb_to_free, nb_free = 0, i;
367 struct rte_mempool *pool;
368 unsigned int tail_idx;
369 unsigned int desc_count = wq->ring.desc_count;
371 nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
373 tail_idx = wq->tail_idx;
374 pool = wq->bufs[tail_idx]->pool;
375 for (i = 0; i < nb_to_free; i++) {
376 buf = wq->bufs[tail_idx];
377 m = rte_pktmbuf_prefree_seg(buf);
378 if (unlikely(m == NULL)) {
379 tail_idx = enic_ring_incr(desc_count, tail_idx);
383 if (likely(m->pool == pool)) {
384 RTE_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
387 rte_mempool_put_bulk(pool, (void *)free, nb_free);
392 tail_idx = enic_ring_incr(desc_count, tail_idx);
396 rte_mempool_put_bulk(pool, (void **)free, nb_free);
398 wq->tail_idx = tail_idx;
399 wq->ring.desc_avail += nb_to_free;
402 unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
404 uint16_t completed_index;
406 completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
408 if (wq->last_completed_index != completed_index) {
409 enic_free_wq_bufs(wq, completed_index);
410 wq->last_completed_index = completed_index;
415 uint16_t enic_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
418 struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
424 for (i = 0; i != nb_pkts; i++) {
426 ol_flags = m->ol_flags;
427 if (!(ol_flags & PKT_TX_TCP_SEG)) {
428 if (unlikely(m->pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
435 header_len = m->l2_len + m->l3_len + m->l4_len;
436 if (m->tso_segsz + header_len > ENIC_TX_MAX_PKT_SIZE) {
442 if (ol_flags & wq->tx_offload_notsup_mask) {
446 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
447 ret = rte_validate_tx_offload(m);
453 ret = rte_net_intel_cksum_prepare(m);
463 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
467 unsigned int pkt_len, data_len;
468 unsigned int nb_segs;
469 struct rte_mbuf *tx_pkt;
470 struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
471 struct enic *enic = vnic_dev_priv(wq->vdev);
472 unsigned short vlan_id;
474 uint64_t ol_flags_mask;
475 unsigned int wq_desc_avail;
477 unsigned int desc_count;
478 struct wq_enet_desc *descs, *desc_p, desc_tmp;
480 uint8_t vlan_tag_insert;
483 uint8_t offload_mode;
486 rte_atomic64_t *tx_oversized;
488 enic_cleanup_wq(enic, wq);
489 wq_desc_avail = vnic_wq_desc_avail(wq);
490 head_idx = wq->head_idx;
491 desc_count = wq->ring.desc_count;
492 ol_flags_mask = PKT_TX_VLAN | PKT_TX_IP_CKSUM | PKT_TX_L4_MASK;
493 tx_oversized = &enic->soft_stats.tx_oversized;
495 nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
497 for (index = 0; index < nb_pkts; index++) {
499 pkt_len = tx_pkt->pkt_len;
500 data_len = tx_pkt->data_len;
501 ol_flags = tx_pkt->ol_flags;
502 nb_segs = tx_pkt->nb_segs;
503 tso = ol_flags & PKT_TX_TCP_SEG;
505 /* drop packet if it's too big to send */
506 if (unlikely(!tso && pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
507 rte_pktmbuf_free(tx_pkt);
508 rte_atomic64_inc(tx_oversized);
512 if (nb_segs > wq_desc_avail) {
519 vlan_id = tx_pkt->vlan_tci;
520 vlan_tag_insert = !!(ol_flags & PKT_TX_VLAN);
521 bus_addr = (dma_addr_t)
522 (tx_pkt->buf_iova + tx_pkt->data_off);
524 descs = (struct wq_enet_desc *)wq->ring.descs;
525 desc_p = descs + head_idx;
527 eop = (data_len == pkt_len);
528 offload_mode = WQ_ENET_OFFLOAD_MODE_CSUM;
532 header_len = tx_pkt->l2_len + tx_pkt->l3_len +
535 /* Drop if non-TCP packet or TSO seg size is too big */
536 if (unlikely(header_len == 0 || ((tx_pkt->tso_segsz +
537 header_len) > ENIC_TX_MAX_PKT_SIZE))) {
538 rte_pktmbuf_free(tx_pkt);
539 rte_atomic64_inc(tx_oversized);
543 offload_mode = WQ_ENET_OFFLOAD_MODE_TSO;
544 mss = tx_pkt->tso_segsz;
545 /* For tunnel, need the size of outer+inner headers */
546 if (ol_flags & PKT_TX_TUNNEL_MASK) {
547 header_len += tx_pkt->outer_l2_len +
548 tx_pkt->outer_l3_len;
552 if ((ol_flags & ol_flags_mask) && (header_len == 0)) {
553 if (ol_flags & PKT_TX_IP_CKSUM)
554 mss |= ENIC_CALC_IP_CKSUM;
556 /* Nic uses just 1 bit for UDP and TCP */
557 switch (ol_flags & PKT_TX_L4_MASK) {
558 case PKT_TX_TCP_CKSUM:
559 case PKT_TX_UDP_CKSUM:
560 mss |= ENIC_CALC_TCP_UDP_CKSUM;
566 if (eop && wq->cq_pend >= ENIC_WQ_CQ_THRESH) {
570 wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, header_len,
571 offload_mode, eop, cq, 0, vlan_tag_insert,
575 wq->bufs[head_idx] = tx_pkt;
576 head_idx = enic_ring_incr(desc_count, head_idx);
580 for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
582 data_len = tx_pkt->data_len;
586 if (tx_pkt->next == NULL) {
588 if (wq->cq_pend >= ENIC_WQ_CQ_THRESH) {
593 desc_p = descs + head_idx;
594 bus_addr = (dma_addr_t)(tx_pkt->buf_iova
596 wq_enet_desc_enc((struct wq_enet_desc *)
597 &desc_tmp, bus_addr, data_len,
598 mss, 0, offload_mode, eop, cq,
599 0, vlan_tag_insert, vlan_id,
603 wq->bufs[head_idx] = tx_pkt;
604 head_idx = enic_ring_incr(desc_count, head_idx);
611 iowrite32_relaxed(head_idx, &wq->ctrl->posted_index);
613 wq->ring.desc_avail = wq_desc_avail;
614 wq->head_idx = head_idx;
619 static void enqueue_simple_pkts(struct rte_mbuf **pkts,
620 struct wq_enet_desc *desc,
630 desc->address = p->buf_iova + p->data_off;
631 desc->length = p->pkt_len;
633 desc->vlan_tag = p->vlan_tci;
634 desc->header_length_flags &=
635 ((1 << WQ_ENET_FLAGS_EOP_SHIFT) |
636 (1 << WQ_ENET_FLAGS_CQ_ENTRY_SHIFT));
637 if (p->ol_flags & PKT_TX_VLAN) {
638 desc->header_length_flags |=
639 1 << WQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT;
642 * Checksum offload. We use WQ_ENET_OFFLOAD_MODE_CSUM, which
643 * is 0, so no need to set offload_mode.
646 if (p->ol_flags & PKT_TX_IP_CKSUM)
647 mss |= ENIC_CALC_IP_CKSUM << WQ_ENET_MSS_SHIFT;
648 if (p->ol_flags & PKT_TX_L4_MASK)
649 mss |= ENIC_CALC_TCP_UDP_CKSUM << WQ_ENET_MSS_SHIFT;
650 desc->mss_loopback = mss;
653 * The app should not send oversized
654 * packets. tx_pkt_prepare includes a check as
655 * well. But some apps ignore the device max size and
656 * tx_pkt_prepare. Oversized packets cause WQ errrors
657 * and the NIC ends up disabling the whole WQ. So
660 if (unlikely(p->pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
661 desc->length = ENIC_TX_MAX_PKT_SIZE;
662 rte_atomic64_inc(&enic->soft_stats.tx_oversized);
668 uint16_t enic_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
671 unsigned int head_idx, desc_count;
672 struct wq_enet_desc *desc;
677 wq = (struct vnic_wq *)tx_queue;
678 enic = vnic_dev_priv(wq->vdev);
679 enic_cleanup_wq(enic, wq);
680 /* Will enqueue this many packets in this call */
681 nb_pkts = RTE_MIN(nb_pkts, wq->ring.desc_avail);
685 head_idx = wq->head_idx;
686 desc_count = wq->ring.desc_count;
688 /* Descriptors until the end of the ring */
689 n = desc_count - head_idx;
690 n = RTE_MIN(nb_pkts, n);
692 /* Save mbuf pointers to free later */
693 memcpy(wq->bufs + head_idx, tx_pkts, sizeof(struct rte_mbuf *) * n);
695 /* Enqueue until the ring end */
697 desc = ((struct wq_enet_desc *)wq->ring.descs) + head_idx;
698 enqueue_simple_pkts(tx_pkts, desc, n, enic);
700 /* Wrap to the start of the ring */
703 memcpy(wq->bufs, tx_pkts, sizeof(struct rte_mbuf *) * rem);
704 desc = (struct wq_enet_desc *)wq->ring.descs;
705 enqueue_simple_pkts(tx_pkts, desc, rem, enic);
709 /* Update head_idx and desc_avail */
710 wq->ring.desc_avail -= nb_pkts;
712 if (head_idx >= desc_count)
713 head_idx -= desc_count;
714 wq->head_idx = head_idx;
715 iowrite32_relaxed(head_idx, &wq->ctrl->posted_index);