1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
7 #include <rte_ethdev.h>
8 #include <rte_prefetch.h>
10 #include "enic_compat.h"
11 #include "rq_enet_desc.h"
13 #include <rte_ether.h>
17 #define RTE_PMD_USE_PREFETCH
19 #ifdef RTE_PMD_USE_PREFETCH
20 /*Prefetch a cache line into all cache levels. */
21 #define rte_enic_prefetch(p) rte_prefetch0(p)
23 #define rte_enic_prefetch(p) do {} while (0)
26 #ifdef RTE_PMD_PACKET_PREFETCH
27 #define rte_packet_prefetch(p) rte_prefetch1(p)
29 #define rte_packet_prefetch(p) do {} while (0)
32 static inline uint16_t
33 enic_cq_rx_desc_ciflags(struct cq_enet_rq_desc *crd)
35 return le16_to_cpu(crd->completed_index_flags) & ~CQ_DESC_COMP_NDX_MASK;
38 static inline uint16_t
39 enic_cq_rx_desc_bwflags(struct cq_enet_rq_desc *crd)
41 return le16_to_cpu(crd->bytes_written_flags) &
42 ~CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
46 enic_cq_rx_desc_packet_error(uint16_t bwflags)
48 return (bwflags & CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ==
49 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED;
53 enic_cq_rx_desc_eop(uint16_t ciflags)
55 return (ciflags & CQ_ENET_RQ_DESC_FLAGS_EOP)
56 == CQ_ENET_RQ_DESC_FLAGS_EOP;
60 enic_cq_rx_desc_csum_not_calc(struct cq_enet_rq_desc *cqrd)
62 return (le16_to_cpu(cqrd->q_number_rss_type_flags) &
63 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ==
64 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC;
68 enic_cq_rx_desc_ipv4_csum_ok(struct cq_enet_rq_desc *cqrd)
70 return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ==
71 CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK;
75 enic_cq_rx_desc_tcp_udp_csum_ok(struct cq_enet_rq_desc *cqrd)
77 return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ==
78 CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK;
82 enic_cq_rx_desc_rss_type(struct cq_enet_rq_desc *cqrd)
84 return (uint8_t)((le16_to_cpu(cqrd->q_number_rss_type_flags) >>
85 CQ_DESC_Q_NUM_BITS) & CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
88 static inline uint32_t
89 enic_cq_rx_desc_rss_hash(struct cq_enet_rq_desc *cqrd)
91 return le32_to_cpu(cqrd->rss_hash);
94 static inline uint16_t
95 enic_cq_rx_desc_vlan(struct cq_enet_rq_desc *cqrd)
97 return le16_to_cpu(cqrd->vlan);
100 static inline uint16_t
101 enic_cq_rx_desc_n_bytes(struct cq_desc *cqd)
103 struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
104 return le16_to_cpu(cqrd->bytes_written_flags) &
105 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
108 /* Find the offset to L5. This is needed by enic TSO implementation.
109 * Return 0 if not a TCP packet or can't figure out the length.
111 static inline uint8_t tso_header_len(struct rte_mbuf *mbuf)
113 struct ether_hdr *eh;
115 struct ipv4_hdr *ip4;
116 struct ipv6_hdr *ip6;
121 /* offset past Ethernet header */
122 eh = rte_pktmbuf_mtod(mbuf, struct ether_hdr *);
123 ether_type = eh->ether_type;
124 hdr_len = sizeof(struct ether_hdr);
125 if (ether_type == rte_cpu_to_be_16(ETHER_TYPE_VLAN)) {
126 vh = rte_pktmbuf_mtod_offset(mbuf, struct vlan_hdr *, hdr_len);
127 ether_type = vh->eth_proto;
128 hdr_len += sizeof(struct vlan_hdr);
131 /* offset past IP header */
132 switch (rte_be_to_cpu_16(ether_type)) {
133 case ETHER_TYPE_IPv4:
134 ip4 = rte_pktmbuf_mtod_offset(mbuf, struct ipv4_hdr *, hdr_len);
135 if (ip4->next_proto_id != IPPROTO_TCP)
137 hdr_len += (ip4->version_ihl & 0xf) * 4;
139 case ETHER_TYPE_IPv6:
140 ip6 = rte_pktmbuf_mtod_offset(mbuf, struct ipv6_hdr *, hdr_len);
141 if (ip6->proto != IPPROTO_TCP)
143 hdr_len += sizeof(struct ipv6_hdr);
149 if ((hdr_len + sizeof(struct tcp_hdr)) > mbuf->pkt_len)
152 /* offset past TCP header */
153 th = rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, hdr_len);
154 hdr_len += (th->data_off >> 4) * 4;
156 if (hdr_len > mbuf->pkt_len)
162 static inline uint8_t
163 enic_cq_rx_check_err(struct cq_desc *cqd)
165 struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
168 bwflags = enic_cq_rx_desc_bwflags(cqrd);
169 if (unlikely(enic_cq_rx_desc_packet_error(bwflags)))
174 /* Lookup table to translate RX CQ flags to mbuf flags. */
175 static inline uint32_t
176 enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd)
178 struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
179 uint8_t cqrd_flags = cqrd->flags;
180 static const uint32_t cq_type_table[128] __rte_cache_aligned = {
181 [0x00] = RTE_PTYPE_UNKNOWN,
182 [0x20] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
183 [0x22] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
184 [0x24] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
185 [0x60] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
186 [0x62] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
187 [0x64] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
188 [0x10] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
189 [0x12] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
190 [0x14] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
191 [0x50] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
192 [0x52] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
193 [0x54] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
194 /* All others reserved */
196 cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
197 | CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
198 | CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
199 return cq_type_table[cqrd_flags];
203 enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
205 struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
206 uint16_t bwflags, pkt_flags = 0, vlan_tci;
207 bwflags = enic_cq_rx_desc_bwflags(cqrd);
208 vlan_tci = enic_cq_rx_desc_vlan(cqrd);
210 /* VLAN STRIPPED flag. The L2 packet type updated here also */
211 if (bwflags & CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) {
212 pkt_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
213 mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
216 mbuf->packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
218 mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
220 mbuf->vlan_tci = vlan_tci;
222 if ((cqd->type_color & CQ_DESC_TYPE_MASK) == CQ_DESC_TYPE_CLASSIFIER) {
223 struct cq_enet_rq_clsf_desc *clsf_cqd;
225 clsf_cqd = (struct cq_enet_rq_clsf_desc *)cqd;
226 filter_id = clsf_cqd->filter_id;
228 pkt_flags |= PKT_RX_FDIR;
229 if (filter_id != ENIC_MAGIC_FILTER_ID) {
230 mbuf->hash.fdir.hi = clsf_cqd->filter_id;
231 pkt_flags |= PKT_RX_FDIR_ID;
234 } else if (enic_cq_rx_desc_rss_type(cqrd)) {
236 pkt_flags |= PKT_RX_RSS_HASH;
237 mbuf->hash.rss = enic_cq_rx_desc_rss_hash(cqrd);
241 if (mbuf->packet_type & RTE_PTYPE_L3_IPV4) {
242 if (!enic_cq_rx_desc_csum_not_calc(cqrd)) {
244 l4_flags = mbuf->packet_type & RTE_PTYPE_L4_MASK;
246 if (enic_cq_rx_desc_ipv4_csum_ok(cqrd))
247 pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
249 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
251 if (l4_flags == RTE_PTYPE_L4_UDP ||
252 l4_flags == RTE_PTYPE_L4_TCP) {
253 if (enic_cq_rx_desc_tcp_udp_csum_ok(cqrd))
254 pkt_flags |= PKT_RX_L4_CKSUM_GOOD;
256 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
261 mbuf->ol_flags = pkt_flags;
264 /* dummy receive function to replace actual function in
265 * order to do safe reconfiguration operations.
268 enic_dummy_recv_pkts(__rte_unused void *rx_queue,
269 __rte_unused struct rte_mbuf **rx_pkts,
270 __rte_unused uint16_t nb_pkts)
276 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
279 struct vnic_rq *sop_rq = rx_queue;
280 struct vnic_rq *data_rq;
282 struct enic *enic = vnic_dev_priv(sop_rq->vdev);
286 struct rte_mbuf *nmb, *rxmb;
289 volatile struct cq_desc *cqd_ptr;
292 struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
293 struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
295 cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
296 cq_idx = cq->to_clean; /* index of cqd, rqd, mbuf_table */
297 cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
299 data_rq = &enic->rq[sop_rq->data_queue_idx];
301 while (nb_rx < nb_pkts) {
302 volatile struct rq_enet_desc *rqd_ptr;
304 uint8_t packet_error;
307 /* Check for pkts available */
308 color = (cqd_ptr->type_color >> CQ_DESC_COLOR_SHIFT)
309 & CQ_DESC_COLOR_MASK;
310 if (color == cq->last_color)
313 /* Get the cq descriptor and extract rq info from it */
315 rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
316 rq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;
318 rq = &enic->rq[rq_num];
319 rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
321 /* allocate a new mbuf */
322 nmb = rte_mbuf_raw_alloc(rq->mp);
324 rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
328 /* A packet error means descriptor and data are untrusted */
329 packet_error = enic_cq_rx_check_err(&cqd);
331 /* Get the mbuf to return and replace with one just allocated */
332 rxmb = rq->mbuf_ring[rq_idx];
333 rq->mbuf_ring[rq_idx] = nmb;
335 /* Increment cqd, rqd, mbuf_table index */
337 if (unlikely(cq_idx == cq->ring.desc_count)) {
339 cq->last_color = cq->last_color ? 0 : 1;
342 /* Prefetch next mbuf & desc while processing current one */
343 cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
344 rte_enic_prefetch(cqd_ptr);
346 ciflags = enic_cq_rx_desc_ciflags(
347 (struct cq_enet_rq_desc *)&cqd);
349 /* Push descriptor for newly allocated mbuf */
350 nmb->data_off = RTE_PKTMBUF_HEADROOM;
352 * Only the address needs to be refilled. length_type of the
353 * descriptor it set during initialization
354 * (enic_alloc_rx_queue_mbufs) and does not change.
356 rqd_ptr->address = rte_cpu_to_le_64(nmb->buf_iova +
357 RTE_PKTMBUF_HEADROOM);
359 /* Fill in the rest of the mbuf */
360 seg_length = enic_cq_rx_desc_n_bytes(&cqd);
364 first_seg->pkt_len = seg_length;
366 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
368 first_seg->nb_segs++;
369 last_seg->next = rxmb;
372 rxmb->port = enic->port_id;
373 rxmb->data_len = seg_length;
377 if (!(enic_cq_rx_desc_eop(ciflags))) {
382 /* cq rx flags are only valid if eop bit is set */
383 first_seg->packet_type = enic_cq_rx_flags_to_pkt_type(&cqd);
384 enic_cq_rx_to_pkt_flags(&cqd, first_seg);
386 if (unlikely(packet_error)) {
387 rte_pktmbuf_free(first_seg);
388 rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
393 /* prefetch mbuf data for caller */
394 rte_packet_prefetch(RTE_PTR_ADD(first_seg->buf_addr,
395 RTE_PKTMBUF_HEADROOM));
397 /* store the mbuf address into the next entry of the array */
398 rx_pkts[nb_rx++] = first_seg;
401 sop_rq->pkt_first_seg = first_seg;
402 sop_rq->pkt_last_seg = last_seg;
404 cq->to_clean = cq_idx;
406 if ((sop_rq->rx_nb_hold + data_rq->rx_nb_hold) >
407 sop_rq->rx_free_thresh) {
408 if (data_rq->in_use) {
409 data_rq->posted_index =
410 enic_ring_add(data_rq->ring.desc_count,
411 data_rq->posted_index,
412 data_rq->rx_nb_hold);
413 data_rq->rx_nb_hold = 0;
415 sop_rq->posted_index = enic_ring_add(sop_rq->ring.desc_count,
416 sop_rq->posted_index,
418 sop_rq->rx_nb_hold = 0;
422 iowrite32_relaxed(data_rq->posted_index,
423 &data_rq->ctrl->posted_index);
424 rte_compiler_barrier();
425 iowrite32_relaxed(sop_rq->posted_index,
426 &sop_rq->ctrl->posted_index);
433 static inline void enic_free_wq_bufs(struct vnic_wq *wq, u16 completed_index)
435 struct vnic_wq_buf *buf;
436 struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
437 unsigned int nb_to_free, nb_free = 0, i;
438 struct rte_mempool *pool;
439 unsigned int tail_idx;
440 unsigned int desc_count = wq->ring.desc_count;
442 nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
444 tail_idx = wq->tail_idx;
445 buf = &wq->bufs[tail_idx];
446 pool = ((struct rte_mbuf *)buf->mb)->pool;
447 for (i = 0; i < nb_to_free; i++) {
448 buf = &wq->bufs[tail_idx];
449 m = rte_pktmbuf_prefree_seg((struct rte_mbuf *)(buf->mb));
452 if (unlikely(m == NULL)) {
453 tail_idx = enic_ring_incr(desc_count, tail_idx);
457 if (likely(m->pool == pool)) {
458 RTE_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
461 rte_mempool_put_bulk(pool, (void *)free, nb_free);
466 tail_idx = enic_ring_incr(desc_count, tail_idx);
470 rte_mempool_put_bulk(pool, (void **)free, nb_free);
472 wq->tail_idx = tail_idx;
473 wq->ring.desc_avail += nb_to_free;
476 unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
480 completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
482 if (wq->last_completed_index != completed_index) {
483 enic_free_wq_bufs(wq, completed_index);
484 wq->last_completed_index = completed_index;
489 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
493 unsigned int pkt_len, data_len;
494 unsigned int nb_segs;
495 struct rte_mbuf *tx_pkt;
496 struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
497 struct enic *enic = vnic_dev_priv(wq->vdev);
498 unsigned short vlan_id;
500 uint64_t ol_flags_mask;
501 unsigned int wq_desc_avail;
503 struct vnic_wq_buf *buf;
504 unsigned int desc_count;
505 struct wq_enet_desc *descs, *desc_p, desc_tmp;
507 uint8_t vlan_tag_insert;
510 uint8_t offload_mode;
513 rte_atomic64_t *tx_oversized;
515 enic_cleanup_wq(enic, wq);
516 wq_desc_avail = vnic_wq_desc_avail(wq);
517 head_idx = wq->head_idx;
518 desc_count = wq->ring.desc_count;
519 ol_flags_mask = PKT_TX_VLAN_PKT | PKT_TX_IP_CKSUM | PKT_TX_L4_MASK;
520 tx_oversized = &enic->soft_stats.tx_oversized;
522 nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
524 for (index = 0; index < nb_pkts; index++) {
526 pkt_len = tx_pkt->pkt_len;
527 data_len = tx_pkt->data_len;
528 ol_flags = tx_pkt->ol_flags;
529 nb_segs = tx_pkt->nb_segs;
530 tso = ol_flags & PKT_TX_TCP_SEG;
532 /* drop packet if it's too big to send */
533 if (unlikely(!tso && pkt_len > ENIC_TX_MAX_PKT_SIZE)) {
534 rte_pktmbuf_free(tx_pkt);
535 rte_atomic64_inc(tx_oversized);
539 if (nb_segs > wq_desc_avail) {
548 bus_addr = (dma_addr_t)
549 (tx_pkt->buf_iova + tx_pkt->data_off);
551 descs = (struct wq_enet_desc *)wq->ring.descs;
552 desc_p = descs + head_idx;
554 eop = (data_len == pkt_len);
555 offload_mode = WQ_ENET_OFFLOAD_MODE_CSUM;
559 header_len = tso_header_len(tx_pkt);
561 /* Drop if non-TCP packet or TSO seg size is too big */
562 if (unlikely(header_len == 0 || ((tx_pkt->tso_segsz +
563 header_len) > ENIC_TX_MAX_PKT_SIZE))) {
564 rte_pktmbuf_free(tx_pkt);
565 rte_atomic64_inc(tx_oversized);
569 offload_mode = WQ_ENET_OFFLOAD_MODE_TSO;
570 mss = tx_pkt->tso_segsz;
573 if ((ol_flags & ol_flags_mask) && (header_len == 0)) {
574 if (ol_flags & PKT_TX_IP_CKSUM)
575 mss |= ENIC_CALC_IP_CKSUM;
577 /* Nic uses just 1 bit for UDP and TCP */
578 switch (ol_flags & PKT_TX_L4_MASK) {
579 case PKT_TX_TCP_CKSUM:
580 case PKT_TX_UDP_CKSUM:
581 mss |= ENIC_CALC_TCP_UDP_CKSUM;
586 if (ol_flags & PKT_TX_VLAN_PKT) {
588 vlan_id = tx_pkt->vlan_tci;
591 wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, header_len,
592 offload_mode, eop, eop, 0, vlan_tag_insert,
596 buf = &wq->bufs[head_idx];
597 buf->mb = (void *)tx_pkt;
598 head_idx = enic_ring_incr(desc_count, head_idx);
602 for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
604 data_len = tx_pkt->data_len;
606 if (tx_pkt->next == NULL)
608 desc_p = descs + head_idx;
609 bus_addr = (dma_addr_t)(tx_pkt->buf_iova
611 wq_enet_desc_enc((struct wq_enet_desc *)
612 &desc_tmp, bus_addr, data_len,
613 mss, 0, offload_mode, eop, eop,
614 0, vlan_tag_insert, vlan_id,
618 buf = &wq->bufs[head_idx];
619 buf->mb = (void *)tx_pkt;
620 head_idx = enic_ring_incr(desc_count, head_idx);
627 iowrite32_relaxed(head_idx, &wq->ctrl->posted_index);
629 wq->ring.desc_avail = wq_desc_avail;
630 wq->head_idx = head_idx;