drivers/net/enic/enic_rxtx.c

   1 /* Copyright 2008-2016 Cisco Systems, Inc.  All rights reserved.
   2  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   3  *
   4  * Copyright (c) 2014, Cisco Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer.
  13  *
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  * notice, this list of conditions and the following disclaimer in
  16  * the documentation and/or other materials provided with the
  17  * distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  26  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  27  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  29  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <rte_mbuf.h>
  34 #include <rte_ethdev.h>
  35 #include <rte_prefetch.h>
  36
  37 #include "enic_compat.h"
  38 #include "rq_enet_desc.h"
  39 #include "enic.h"
  40 #include <rte_ether.h>
  41 #include <rte_ip.h>
  42 #include <rte_tcp.h>
  43
  44 #define RTE_PMD_USE_PREFETCH
  45
  46 #ifdef RTE_PMD_USE_PREFETCH
  47 /*Prefetch a cache line into all cache levels. */
  48 #define rte_enic_prefetch(p) rte_prefetch0(p)
  49 #else
  50 #define rte_enic_prefetch(p) do {} while (0)
  51 #endif
  52
  53 #ifdef RTE_PMD_PACKET_PREFETCH
  54 #define rte_packet_prefetch(p) rte_prefetch1(p)
  55 #else
  56 #define rte_packet_prefetch(p) do {} while (0)
  57 #endif
  58
  59 static inline uint16_t
  60 enic_cq_rx_desc_ciflags(struct cq_enet_rq_desc *crd)
  61 {
  62         return le16_to_cpu(crd->completed_index_flags) & ~CQ_DESC_COMP_NDX_MASK;
  63 }
  64
  65 static inline uint16_t
  66 enic_cq_rx_desc_bwflags(struct cq_enet_rq_desc *crd)
  67 {
  68         return le16_to_cpu(crd->bytes_written_flags) &
  69                            ~CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
  70 }
  71
  72 static inline uint8_t
  73 enic_cq_rx_desc_packet_error(uint16_t bwflags)
  74 {
  75         return (bwflags & CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ==
  76                 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED;
  77 }
  78
  79 static inline uint8_t
  80 enic_cq_rx_desc_eop(uint16_t ciflags)
  81 {
  82         return (ciflags & CQ_ENET_RQ_DESC_FLAGS_EOP)
  83                 == CQ_ENET_RQ_DESC_FLAGS_EOP;
  84 }
  85
  86 static inline uint8_t
  87 enic_cq_rx_desc_csum_not_calc(struct cq_enet_rq_desc *cqrd)
  88 {
  89         return (le16_to_cpu(cqrd->q_number_rss_type_flags) &
  90                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ==
  91                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC;
  92 }
  93
  94 static inline uint8_t
  95 enic_cq_rx_desc_ipv4_csum_ok(struct cq_enet_rq_desc *cqrd)
  96 {
  97         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ==
  98                 CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK;
  99 }
 100
 101 static inline uint8_t
 102 enic_cq_rx_desc_tcp_udp_csum_ok(struct cq_enet_rq_desc *cqrd)
 103 {
 104         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ==
 105                 CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK;
 106 }
 107
 108 static inline uint8_t
 109 enic_cq_rx_desc_rss_type(struct cq_enet_rq_desc *cqrd)
 110 {
 111         return (uint8_t)((le16_to_cpu(cqrd->q_number_rss_type_flags) >>
 112                 CQ_DESC_Q_NUM_BITS) & CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
 113 }
 114
 115 static inline uint32_t
 116 enic_cq_rx_desc_rss_hash(struct cq_enet_rq_desc *cqrd)
 117 {
 118         return le32_to_cpu(cqrd->rss_hash);
 119 }
 120
 121 static inline uint16_t
 122 enic_cq_rx_desc_vlan(struct cq_enet_rq_desc *cqrd)
 123 {
 124         return le16_to_cpu(cqrd->vlan);
 125 }
 126
 127 static inline uint16_t
 128 enic_cq_rx_desc_n_bytes(struct cq_desc *cqd)
 129 {
 130         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 131         return le16_to_cpu(cqrd->bytes_written_flags) &
 132                 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
 133 }
 134
 135 /* Find the offset to L5. This is needed by enic TSO implementation.
 136  * Return 0 if not a TCP packet or can't figure out the length.
 137  */
 138 static inline uint8_t tso_header_len(struct rte_mbuf *mbuf)
 139 {
 140         struct ether_hdr *eh;
 141         struct vlan_hdr *vh;
 142         struct ipv4_hdr *ip4;
 143         struct ipv6_hdr *ip6;
 144         struct tcp_hdr *th;
 145         uint8_t hdr_len;
 146         uint16_t ether_type;
 147
 148         /* offset past Ethernet header */
 149         eh = rte_pktmbuf_mtod(mbuf, struct ether_hdr *);
 150         ether_type = eh->ether_type;
 151         hdr_len = sizeof(struct ether_hdr);
 152         if (ether_type == rte_cpu_to_be_16(ETHER_TYPE_VLAN)) {
 153                 vh = rte_pktmbuf_mtod_offset(mbuf, struct vlan_hdr *, hdr_len);
 154                 ether_type = vh->eth_proto;
 155                 hdr_len += sizeof(struct vlan_hdr);
 156         }
 157
 158         /* offset past IP header */
 159         switch (rte_be_to_cpu_16(ether_type)) {
 160         case ETHER_TYPE_IPv4:
 161                 ip4 = rte_pktmbuf_mtod_offset(mbuf, struct ipv4_hdr *, hdr_len);
 162                 if (ip4->next_proto_id != IPPROTO_TCP)
 163                         return 0;
 164                 hdr_len += (ip4->version_ihl & 0xf) * 4;
 165                 break;
 166         case ETHER_TYPE_IPv6:
 167                 ip6 = rte_pktmbuf_mtod_offset(mbuf, struct ipv6_hdr *, hdr_len);
 168                 if (ip6->proto != IPPROTO_TCP)
 169                         return 0;
 170                 hdr_len += sizeof(struct ipv6_hdr);
 171                 break;
 172         default:
 173                 return 0;
 174         }
 175
 176         if ((hdr_len + sizeof(struct tcp_hdr)) > mbuf->pkt_len)
 177                 return 0;
 178
 179         /* offset past TCP header */
 180         th = rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, hdr_len);
 181         hdr_len += (th->data_off >> 4) * 4;
 182
 183         if (hdr_len > mbuf->pkt_len)
 184                 return 0;
 185
 186         return hdr_len;
 187 }
 188
 189 static inline uint8_t
 190 enic_cq_rx_check_err(struct cq_desc *cqd)
 191 {
 192         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 193         uint16_t bwflags;
 194
 195         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 196         if (unlikely(enic_cq_rx_desc_packet_error(bwflags)))
 197                 return 1;
 198         return 0;
 199 }
 200
 201 /* Lookup table to translate RX CQ flags to mbuf flags. */
 202 static inline uint32_t
 203 enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd)
 204 {
 205         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 206         uint8_t cqrd_flags = cqrd->flags;
 207         static const uint32_t cq_type_table[128] __rte_cache_aligned = {
 208                 [0x00] = RTE_PTYPE_UNKNOWN,
 209                 [0x20] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
 210                 [0x22] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 211                 [0x24] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 212                 [0x60] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 213                 [0x62] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 214                 [0x64] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 215                 [0x10] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
 216                 [0x12] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 217                 [0x14] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 218                 [0x50] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 219                 [0x52] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 220                 [0x54] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 221                 /* All others reserved */
 222         };
 223         cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
 224                 | CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
 225                 | CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
 226         return cq_type_table[cqrd_flags];
 227 }
 228
 229 static inline void
 230 enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
 231 {
 232         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 233         uint16_t ciflags, bwflags, pkt_flags = 0, vlan_tci;
 234         ciflags = enic_cq_rx_desc_ciflags(cqrd);
 235         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 236         vlan_tci = enic_cq_rx_desc_vlan(cqrd);
 237
 238         mbuf->ol_flags = 0;
 239
 240         /* flags are meaningless if !EOP */
 241         if (unlikely(!enic_cq_rx_desc_eop(ciflags)))
 242                 goto mbuf_flags_done;
 243
 244         /* VLAN STRIPPED flag. The L2 packet type updated here also */
 245         if (bwflags & CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) {
 246                 pkt_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 247                 mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
 248         } else {
 249                 if (vlan_tci != 0)
 250                         mbuf->packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
 251                 else
 252                         mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
 253         }
 254         mbuf->vlan_tci = vlan_tci;
 255
 256         /* RSS flag */
 257         if (enic_cq_rx_desc_rss_type(cqrd)) {
 258                 pkt_flags |= PKT_RX_RSS_HASH;
 259                 mbuf->hash.rss = enic_cq_rx_desc_rss_hash(cqrd);
 260         }
 261
 262         /* checksum flags */
 263         if (!enic_cq_rx_desc_csum_not_calc(cqrd) &&
 264                 (mbuf->packet_type & RTE_PTYPE_L3_IPV4)) {
 265                 uint32_t l4_flags = mbuf->packet_type & RTE_PTYPE_L4_MASK;
 266
 267                 if (unlikely(!enic_cq_rx_desc_ipv4_csum_ok(cqrd)))
 268                         pkt_flags |= PKT_RX_IP_CKSUM_BAD;
 269                 if (l4_flags == RTE_PTYPE_L4_UDP ||
 270                     l4_flags == RTE_PTYPE_L4_TCP) {
 271                         if (unlikely(!enic_cq_rx_desc_tcp_udp_csum_ok(cqrd)))
 272                                 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
 273                 }
 274         }
 275
 276  mbuf_flags_done:
 277         mbuf->ol_flags = pkt_flags;
 278 }
 279
 280 /* dummy receive function to replace actual function in
 281  * order to do safe reconfiguration operations.
 282  */
 283 uint16_t
 284 enic_dummy_recv_pkts(__rte_unused void *rx_queue,
 285                      __rte_unused struct rte_mbuf **rx_pkts,
 286                      __rte_unused uint16_t nb_pkts)
 287 {
 288         return 0;
 289 }
 290
 291 uint16_t
 292 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 293                uint16_t nb_pkts)
 294 {
 295         struct vnic_rq *sop_rq = rx_queue;
 296         struct vnic_rq *data_rq;
 297         struct vnic_rq *rq;
 298         struct enic *enic = vnic_dev_priv(sop_rq->vdev);
 299         uint16_t cq_idx;
 300         uint16_t rq_idx;
 301         uint16_t rq_num;
 302         struct rte_mbuf *nmb, *rxmb;
 303         uint16_t nb_rx = 0;
 304         struct vnic_cq *cq;
 305         volatile struct cq_desc *cqd_ptr;
 306         uint8_t color;
 307         uint16_t seg_length;
 308         struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
 309         struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
 310
 311         cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
 312         cq_idx = cq->to_clean;          /* index of cqd, rqd, mbuf_table */
 313         cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
 314
 315         data_rq = &enic->rq[sop_rq->data_queue_idx];
 316
 317         while (nb_rx < nb_pkts) {
 318                 volatile struct rq_enet_desc *rqd_ptr;
 319                 dma_addr_t dma_addr;
 320                 struct cq_desc cqd;
 321                 uint8_t packet_error;
 322                 uint16_t ciflags;
 323
 324                 /* Check for pkts available */
 325                 color = (cqd_ptr->type_color >> CQ_DESC_COLOR_SHIFT)
 326                         & CQ_DESC_COLOR_MASK;
 327                 if (color == cq->last_color)
 328                         break;
 329
 330                 /* Get the cq descriptor and extract rq info from it */
 331                 cqd = *cqd_ptr;
 332                 rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
 333                 rq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;
 334
 335                 rq = &enic->rq[rq_num];
 336                 rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
 337
 338                 /* allocate a new mbuf */
 339                 nmb = rte_mbuf_raw_alloc(rq->mp);
 340                 if (nmb == NULL) {
 341                         rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
 342                         break;
 343                 }
 344
 345                 /* A packet error means descriptor and data are untrusted */
 346                 packet_error = enic_cq_rx_check_err(&cqd);
 347
 348                 /* Get the mbuf to return and replace with one just allocated */
 349                 rxmb = rq->mbuf_ring[rq_idx];
 350                 rq->mbuf_ring[rq_idx] = nmb;
 351
 352                 /* Increment cqd, rqd, mbuf_table index */
 353                 cq_idx++;
 354                 if (unlikely(cq_idx == cq->ring.desc_count)) {
 355                         cq_idx = 0;
 356                         cq->last_color = cq->last_color ? 0 : 1;
 357                 }
 358
 359                 /* Prefetch next mbuf & desc while processing current one */
 360                 cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
 361                 rte_enic_prefetch(cqd_ptr);
 362
 363                 ciflags = enic_cq_rx_desc_ciflags(
 364                         (struct cq_enet_rq_desc *)&cqd);
 365
 366                 /* Push descriptor for newly allocated mbuf */
 367                 nmb->data_off = RTE_PKTMBUF_HEADROOM;
 368                 dma_addr = (dma_addr_t)(nmb->buf_physaddr +
 369                                         RTE_PKTMBUF_HEADROOM);
 370                 rq_enet_desc_enc(rqd_ptr, dma_addr,
 371                                 (rq->is_sop ? RQ_ENET_TYPE_ONLY_SOP
 372                                 : RQ_ENET_TYPE_NOT_SOP),
 373                                 nmb->buf_len - RTE_PKTMBUF_HEADROOM);
 374
 375                 /* Fill in the rest of the mbuf */
 376                 seg_length = enic_cq_rx_desc_n_bytes(&cqd);
 377
 378                 if (rq->is_sop) {
 379                         first_seg = rxmb;
 380                         first_seg->nb_segs = 1;
 381                         first_seg->pkt_len = seg_length;
 382                 } else {
 383                         first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
 384                                                         + seg_length);
 385                         first_seg->nb_segs++;
 386                         last_seg->next = rxmb;
 387                 }
 388
 389                 rxmb->next = NULL;
 390                 rxmb->port = enic->port_id;
 391                 rxmb->data_len = seg_length;
 392
 393                 rq->rx_nb_hold++;
 394
 395                 if (!(enic_cq_rx_desc_eop(ciflags))) {
 396                         last_seg = rxmb;
 397                         continue;
 398                 }
 399
 400                 /* cq rx flags are only valid if eop bit is set */
 401                 first_seg->packet_type = enic_cq_rx_flags_to_pkt_type(&cqd);
 402                 enic_cq_rx_to_pkt_flags(&cqd, first_seg);
 403
 404                 if (unlikely(packet_error)) {
 405                         rte_pktmbuf_free(first_seg);
 406                         rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
 407                         continue;
 408                 }
 409
 410
 411                 /* prefetch mbuf data for caller */
 412                 rte_packet_prefetch(RTE_PTR_ADD(first_seg->buf_addr,
 413                                     RTE_PKTMBUF_HEADROOM));
 414
 415                 /* store the mbuf address into the next entry of the array */
 416                 rx_pkts[nb_rx++] = first_seg;
 417         }
 418
 419         sop_rq->pkt_first_seg = first_seg;
 420         sop_rq->pkt_last_seg = last_seg;
 421
 422         cq->to_clean = cq_idx;
 423
 424         if ((sop_rq->rx_nb_hold + data_rq->rx_nb_hold) >
 425             sop_rq->rx_free_thresh) {
 426                 if (data_rq->in_use) {
 427                         data_rq->posted_index =
 428                                 enic_ring_add(data_rq->ring.desc_count,
 429                                               data_rq->posted_index,
 430                                               data_rq->rx_nb_hold);
 431                         data_rq->rx_nb_hold = 0;
 432                 }
 433                 sop_rq->posted_index = enic_ring_add(sop_rq->ring.desc_count,
 434                                                      sop_rq->posted_index,
 435                                                      sop_rq->rx_nb_hold);
 436                 sop_rq->rx_nb_hold = 0;
 437
 438                 rte_mb();
 439                 if (data_rq->in_use)
 440                         iowrite32(data_rq->posted_index,
 441                                   &data_rq->ctrl->posted_index);
 442                 rte_compiler_barrier();
 443                 iowrite32(sop_rq->posted_index, &sop_rq->ctrl->posted_index);
 444         }
 445
 446
 447         return nb_rx;
 448 }
 449
 450 static inline void enic_free_wq_bufs(struct vnic_wq *wq, u16 completed_index)
 451 {
 452         struct vnic_wq_buf *buf;
 453         struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
 454         unsigned int nb_to_free, nb_free = 0, i;
 455         struct rte_mempool *pool;
 456         unsigned int tail_idx;
 457         unsigned int desc_count = wq->ring.desc_count;
 458
 459         nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
 460                                    + 1;
 461         tail_idx = wq->tail_idx;
 462         buf = &wq->bufs[tail_idx];
 463         pool = ((struct rte_mbuf *)buf->mb)->pool;
 464         for (i = 0; i < nb_to_free; i++) {
 465                 buf = &wq->bufs[tail_idx];
 466                 m = __rte_pktmbuf_prefree_seg((struct rte_mbuf *)(buf->mb));
 467                 buf->mb = NULL;
 468
 469                 if (unlikely(m == NULL)) {
 470                         tail_idx = enic_ring_incr(desc_count, tail_idx);
 471                         continue;
 472                 }
 473
 474                 if (likely(m->pool == pool)) {
 475                         RTE_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
 476                         free[nb_free++] = m;
 477                 } else {
 478                         rte_mempool_put_bulk(pool, (void *)free, nb_free);
 479                         free[0] = m;
 480                         nb_free = 1;
 481                         pool = m->pool;
 482                 }
 483                 tail_idx = enic_ring_incr(desc_count, tail_idx);
 484         }
 485
 486         rte_mempool_put_bulk(pool, (void **)free, nb_free);
 487
 488         wq->tail_idx = tail_idx;
 489         wq->ring.desc_avail += nb_to_free;
 490 }
 491
 492 unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
 493 {
 494         u16 completed_index;
 495
 496         completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
 497
 498         if (wq->last_completed_index != completed_index) {
 499                 enic_free_wq_bufs(wq, completed_index);
 500                 wq->last_completed_index = completed_index;
 501         }
 502         return 0;
 503 }
 504
 505 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 506         uint16_t nb_pkts)
 507 {
 508         uint16_t index;
 509         unsigned int pkt_len, data_len;
 510         unsigned int nb_segs;
 511         struct rte_mbuf *tx_pkt;
 512         struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
 513         struct enic *enic = vnic_dev_priv(wq->vdev);
 514         unsigned short vlan_id;
 515         uint64_t ol_flags;
 516         uint64_t ol_flags_mask;
 517         unsigned int wq_desc_avail;
 518         int head_idx;
 519         struct vnic_wq_buf *buf;
 520         unsigned int desc_count;
 521         struct wq_enet_desc *descs, *desc_p, desc_tmp;
 522         uint16_t mss;
 523         uint8_t vlan_tag_insert;
 524         uint8_t eop;
 525         uint64_t bus_addr;
 526         uint8_t offload_mode;
 527         uint16_t header_len;
 528
 529         enic_cleanup_wq(enic, wq);
 530         wq_desc_avail = vnic_wq_desc_avail(wq);
 531         head_idx = wq->head_idx;
 532         desc_count = wq->ring.desc_count;
 533         ol_flags_mask = PKT_TX_VLAN_PKT | PKT_TX_IP_CKSUM | PKT_TX_L4_MASK;
 534
 535         nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
 536
 537         for (index = 0; index < nb_pkts; index++) {
 538                 tx_pkt = *tx_pkts++;
 539                 nb_segs = tx_pkt->nb_segs;
 540                 if (nb_segs > wq_desc_avail) {
 541                         if (index > 0)
 542                                 goto post;
 543                         goto done;
 544                 }
 545
 546                 pkt_len = tx_pkt->pkt_len;
 547                 data_len = tx_pkt->data_len;
 548                 ol_flags = tx_pkt->ol_flags;
 549                 mss = 0;
 550                 vlan_id = 0;
 551                 vlan_tag_insert = 0;
 552                 bus_addr = (dma_addr_t)
 553                            (tx_pkt->buf_physaddr + tx_pkt->data_off);
 554
 555                 descs = (struct wq_enet_desc *)wq->ring.descs;
 556                 desc_p = descs + head_idx;
 557
 558                 eop = (data_len == pkt_len);
 559                 offload_mode = WQ_ENET_OFFLOAD_MODE_CSUM;
 560                 header_len = 0;
 561
 562                 if (tx_pkt->tso_segsz) {
 563                         header_len = tso_header_len(tx_pkt);
 564                         if (header_len) {
 565                                 offload_mode = WQ_ENET_OFFLOAD_MODE_TSO;
 566                                 mss = tx_pkt->tso_segsz;
 567                         }
 568                 }
 569                 if ((ol_flags & ol_flags_mask) && (header_len == 0)) {
 570                         if (ol_flags & PKT_TX_IP_CKSUM)
 571                                 mss |= ENIC_CALC_IP_CKSUM;
 572
 573                         /* Nic uses just 1 bit for UDP and TCP */
 574                         switch (ol_flags & PKT_TX_L4_MASK) {
 575                         case PKT_TX_TCP_CKSUM:
 576                         case PKT_TX_UDP_CKSUM:
 577                                 mss |= ENIC_CALC_TCP_UDP_CKSUM;
 578                                 break;
 579                         }
 580                 }
 581
 582                 if (ol_flags & PKT_TX_VLAN_PKT) {
 583                         vlan_tag_insert = 1;
 584                         vlan_id = tx_pkt->vlan_tci;
 585                 }
 586
 587                 wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, header_len,
 588                                  offload_mode, eop, eop, 0, vlan_tag_insert,
 589                                  vlan_id, 0);
 590
 591                 *desc_p = desc_tmp;
 592                 buf = &wq->bufs[head_idx];
 593                 buf->mb = (void *)tx_pkt;
 594                 head_idx = enic_ring_incr(desc_count, head_idx);
 595                 wq_desc_avail--;
 596
 597                 if (!eop) {
 598                         for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
 599                             tx_pkt->next) {
 600                                 data_len = tx_pkt->data_len;
 601
 602                                 if (tx_pkt->next == NULL)
 603                                         eop = 1;
 604                                 desc_p = descs + head_idx;
 605                                 bus_addr = (dma_addr_t)(tx_pkt->buf_physaddr
 606                                            + tx_pkt->data_off);
 607                                 wq_enet_desc_enc((struct wq_enet_desc *)
 608                                                  &desc_tmp, bus_addr, data_len,
 609                                                  mss, 0, offload_mode, eop, eop,
 610                                                  0, vlan_tag_insert, vlan_id,
 611                                                  0);
 612
 613                                 *desc_p = desc_tmp;
 614                                 buf = &wq->bufs[head_idx];
 615                                 buf->mb = (void *)tx_pkt;
 616                                 head_idx = enic_ring_incr(desc_count, head_idx);
 617                                 wq_desc_avail--;
 618                         }
 619                 }
 620         }
 621  post:
 622         rte_wmb();
 623         iowrite32(head_idx, &wq->ctrl->posted_index);
 624  done:
 625         wq->ring.desc_avail = wq_desc_avail;
 626         wq->head_idx = head_idx;
 627
 628         return index;
 629 }
 630
 631