drivers/net/enic/enic_rxtx.c

   1 /* Copyright 2008-2016 Cisco Systems, Inc.  All rights reserved.
   2  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   3  *
   4  * Copyright (c) 2014, Cisco Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer.
  13  *
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  * notice, this list of conditions and the following disclaimer in
  16  * the documentation and/or other materials provided with the
  17  * distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  26  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  27  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  29  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <rte_mbuf.h>
  34 #include <rte_ethdev.h>
  35 #include <rte_prefetch.h>
  36
  37 #include "enic_compat.h"
  38 #include "rq_enet_desc.h"
  39 #include "enic.h"
  40 #include "enic_vnic_wq.h"
  41
  42 #define RTE_PMD_USE_PREFETCH
  43
  44 #ifdef RTE_PMD_USE_PREFETCH
  45 /*Prefetch a cache line into all cache levels. */
  46 #define rte_enic_prefetch(p) rte_prefetch0(p)
  47 #else
  48 #define rte_enic_prefetch(p) do {} while (0)
  49 #endif
  50
  51 #ifdef RTE_PMD_PACKET_PREFETCH
  52 #define rte_packet_prefetch(p) rte_prefetch1(p)
  53 #else
  54 #define rte_packet_prefetch(p) do {} while (0)
  55 #endif
  56
  57 static inline uint16_t
  58 enic_cq_rx_desc_ciflags(struct cq_enet_rq_desc *crd)
  59 {
  60         return le16_to_cpu(crd->completed_index_flags) & ~CQ_DESC_COMP_NDX_MASK;
  61 }
  62
  63 static inline uint16_t
  64 enic_cq_rx_desc_bwflags(struct cq_enet_rq_desc *crd)
  65 {
  66         return le16_to_cpu(crd->bytes_written_flags) &
  67                            ~CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
  68 }
  69
  70 static inline uint8_t
  71 enic_cq_rx_desc_packet_error(uint16_t bwflags)
  72 {
  73         return (bwflags & CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ==
  74                 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED;
  75 }
  76
  77 static inline uint8_t
  78 enic_cq_rx_desc_eop(uint16_t ciflags)
  79 {
  80         return (ciflags & CQ_ENET_RQ_DESC_FLAGS_EOP)
  81                 == CQ_ENET_RQ_DESC_FLAGS_EOP;
  82 }
  83
  84 static inline uint8_t
  85 enic_cq_rx_desc_csum_not_calc(struct cq_enet_rq_desc *cqrd)
  86 {
  87         return (le16_to_cpu(cqrd->q_number_rss_type_flags) &
  88                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ==
  89                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC;
  90 }
  91
  92 static inline uint8_t
  93 enic_cq_rx_desc_ipv4_csum_ok(struct cq_enet_rq_desc *cqrd)
  94 {
  95         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ==
  96                 CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK;
  97 }
  98
  99 static inline uint8_t
 100 enic_cq_rx_desc_tcp_udp_csum_ok(struct cq_enet_rq_desc *cqrd)
 101 {
 102         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ==
 103                 CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK;
 104 }
 105
 106 static inline uint8_t
 107 enic_cq_rx_desc_rss_type(struct cq_enet_rq_desc *cqrd)
 108 {
 109         return (uint8_t)((le16_to_cpu(cqrd->q_number_rss_type_flags) >>
 110                 CQ_DESC_Q_NUM_BITS) & CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
 111 }
 112
 113 static inline uint32_t
 114 enic_cq_rx_desc_rss_hash(struct cq_enet_rq_desc *cqrd)
 115 {
 116         return le32_to_cpu(cqrd->rss_hash);
 117 }
 118
 119 static inline uint16_t
 120 enic_cq_rx_desc_vlan(struct cq_enet_rq_desc *cqrd)
 121 {
 122         return le16_to_cpu(cqrd->vlan);
 123 }
 124
 125 static inline uint16_t
 126 enic_cq_rx_desc_n_bytes(struct cq_desc *cqd)
 127 {
 128         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 129         return le16_to_cpu(cqrd->bytes_written_flags) &
 130                 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
 131 }
 132
 133 static inline uint8_t
 134 enic_cq_rx_check_err(struct cq_desc *cqd)
 135 {
 136         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 137         uint16_t bwflags;
 138
 139         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 140         if (unlikely(enic_cq_rx_desc_packet_error(bwflags)))
 141                 return 1;
 142         return 0;
 143 }
 144
 145 /* Lookup table to translate RX CQ flags to mbuf flags. */
 146 static inline uint32_t
 147 enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd)
 148 {
 149         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 150         uint8_t cqrd_flags = cqrd->flags;
 151         static const uint32_t cq_type_table[128] __rte_cache_aligned = {
 152                 [32] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4,
 153                 [34] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4
 154                         | RTE_PTYPE_L4_UDP,
 155                 [36] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4
 156                         | RTE_PTYPE_L4_TCP,
 157                 [96] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4
 158                         | RTE_PTYPE_L4_FRAG,
 159                 [16] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6,
 160                 [18] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6
 161                         | RTE_PTYPE_L4_UDP,
 162                 [20] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6
 163                         | RTE_PTYPE_L4_TCP,
 164                 [80] =  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6
 165                         | RTE_PTYPE_L4_FRAG,
 166                 /* All others reserved */
 167         };
 168         cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
 169                 | CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
 170                 | CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
 171         return cq_type_table[cqrd_flags];
 172 }
 173
 174 static inline void
 175 enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
 176 {
 177         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 178         uint16_t ciflags, bwflags, pkt_flags = 0;
 179         ciflags = enic_cq_rx_desc_ciflags(cqrd);
 180         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 181
 182         mbuf->ol_flags = 0;
 183
 184         /* flags are meaningless if !EOP */
 185         if (unlikely(!enic_cq_rx_desc_eop(ciflags)))
 186                 goto mbuf_flags_done;
 187
 188         /* VLAN stripping */
 189         if (bwflags & CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) {
 190                 pkt_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 191                 mbuf->vlan_tci = enic_cq_rx_desc_vlan(cqrd);
 192         } else {
 193                 mbuf->vlan_tci = 0;
 194         }
 195
 196         /* RSS flag */
 197         if (enic_cq_rx_desc_rss_type(cqrd)) {
 198                 pkt_flags |= PKT_RX_RSS_HASH;
 199                 mbuf->hash.rss = enic_cq_rx_desc_rss_hash(cqrd);
 200         }
 201
 202         /* checksum flags */
 203         if (!enic_cq_rx_desc_csum_not_calc(cqrd) &&
 204                 (mbuf->packet_type & RTE_PTYPE_L3_IPV4)) {
 205                 if (unlikely(!enic_cq_rx_desc_ipv4_csum_ok(cqrd)))
 206                         pkt_flags |= PKT_RX_IP_CKSUM_BAD;
 207                 if (mbuf->packet_type & (RTE_PTYPE_L4_UDP | RTE_PTYPE_L4_TCP)) {
 208                         if (unlikely(!enic_cq_rx_desc_tcp_udp_csum_ok(cqrd)))
 209                                 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
 210                 }
 211         }
 212
 213  mbuf_flags_done:
 214         mbuf->ol_flags = pkt_flags;
 215 }
 216
 217 uint16_t
 218 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 219                uint16_t nb_pkts)
 220 {
 221         struct vnic_rq *rq = rx_queue;
 222         struct enic *enic = vnic_dev_priv(rq->vdev);
 223         unsigned int rx_id;
 224         struct rte_mbuf *nmb, *rxmb;
 225         uint16_t nb_rx = 0, nb_err = 0;
 226         uint16_t nb_hold;
 227         struct vnic_cq *cq;
 228         volatile struct cq_desc *cqd_ptr;
 229         uint8_t color;
 230
 231         cq = &enic->cq[enic_cq_rq(enic, rq->index)];
 232         rx_id = cq->to_clean;           /* index of cqd, rqd, mbuf_table */
 233         cqd_ptr = (struct cq_desc *)(cq->ring.descs) + rx_id;
 234
 235         nb_hold = rq->rx_nb_hold;       /* mbufs held by software */
 236
 237         while (nb_rx < nb_pkts) {
 238                 volatile struct rq_enet_desc *rqd_ptr;
 239                 dma_addr_t dma_addr;
 240                 struct cq_desc cqd;
 241                 uint8_t packet_error;
 242
 243                 /* Check for pkts available */
 244                 color = (cqd_ptr->type_color >> CQ_DESC_COLOR_SHIFT)
 245                         & CQ_DESC_COLOR_MASK;
 246                 if (color == cq->last_color)
 247                         break;
 248
 249                 /* Get the cq descriptor and rq pointer */
 250                 cqd = *cqd_ptr;
 251                 rqd_ptr = (struct rq_enet_desc *)(rq->ring.descs) + rx_id;
 252
 253                 /* allocate a new mbuf */
 254                 nmb = rte_mbuf_raw_alloc(rq->mp);
 255                 if (nmb == NULL) {
 256                         rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
 257                         break;
 258                 }
 259
 260                 /* A packet error means descriptor and data are untrusted */
 261                 packet_error = enic_cq_rx_check_err(&cqd);
 262
 263                 /* Get the mbuf to return and replace with one just allocated */
 264                 rxmb = rq->mbuf_ring[rx_id];
 265                 rq->mbuf_ring[rx_id] = nmb;
 266
 267                 /* Increment cqd, rqd, mbuf_table index */
 268                 rx_id++;
 269                 if (unlikely(rx_id == rq->ring.desc_count)) {
 270                         rx_id = 0;
 271                         cq->last_color = cq->last_color ? 0 : 1;
 272                 }
 273
 274                 /* Prefetch next mbuf & desc while processing current one */
 275                 cqd_ptr = (struct cq_desc *)(cq->ring.descs) + rx_id;
 276                 rte_enic_prefetch(cqd_ptr);
 277                 rte_enic_prefetch(rq->mbuf_ring[rx_id]);
 278                 rte_enic_prefetch((struct rq_enet_desc *)(rq->ring.descs)
 279                                  + rx_id);
 280
 281                 /* Push descriptor for newly allocated mbuf */
 282                 dma_addr = (dma_addr_t)(nmb->buf_physaddr
 283                            + RTE_PKTMBUF_HEADROOM);
 284                 rqd_ptr->address = rte_cpu_to_le_64(dma_addr);
 285                 rqd_ptr->length_type = cpu_to_le16(nmb->buf_len
 286                                        - RTE_PKTMBUF_HEADROOM);
 287
 288                 /* Drop incoming bad packet */
 289                 if (unlikely(packet_error)) {
 290                         rte_pktmbuf_free(rxmb);
 291                         nb_err++;
 292                         continue;
 293                 }
 294
 295                 /* Fill in the rest of the mbuf */
 296                 rxmb->data_off = RTE_PKTMBUF_HEADROOM;
 297                 rxmb->nb_segs = 1;
 298                 rxmb->next = NULL;
 299                 rxmb->port = enic->port_id;
 300                 rxmb->pkt_len = enic_cq_rx_desc_n_bytes(&cqd);
 301                 rxmb->packet_type = enic_cq_rx_flags_to_pkt_type(&cqd);
 302                 enic_cq_rx_to_pkt_flags(&cqd, rxmb);
 303                 rxmb->data_len = rxmb->pkt_len;
 304
 305                 /* prefetch mbuf data for caller */
 306                 rte_packet_prefetch(RTE_PTR_ADD(rxmb->buf_addr,
 307                                     RTE_PKTMBUF_HEADROOM));
 308
 309                 /* store the mbuf address into the next entry of the array */
 310                 rx_pkts[nb_rx++] = rxmb;
 311         }
 312
 313         nb_hold += nb_rx + nb_err;
 314         cq->to_clean = rx_id;
 315
 316         if (nb_hold > rq->rx_free_thresh) {
 317                 rq->posted_index = enic_ring_add(rq->ring.desc_count,
 318                                 rq->posted_index, nb_hold);
 319                 nb_hold = 0;
 320                 rte_mb();
 321                 iowrite32(rq->posted_index, &rq->ctrl->posted_index);
 322         }
 323
 324         rq->rx_nb_hold = nb_hold;
 325
 326         return nb_rx;
 327 }
 328
 329 static inline void enic_free_wq_bufs(struct vnic_wq *wq, u16 completed_index)
 330 {
 331         struct vnic_wq_buf *buf;
 332         struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
 333         unsigned int nb_to_free, nb_free = 0, i;
 334         struct rte_mempool *pool;
 335         unsigned int tail_idx;
 336         unsigned int desc_count = wq->ring.desc_count;
 337
 338         nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
 339                                    + 1;
 340         tail_idx = wq->tail_idx;
 341         buf = &wq->bufs[tail_idx];
 342         pool = ((struct rte_mbuf *)buf->mb)->pool;
 343         for (i = 0; i < nb_to_free; i++) {
 344                 buf = &wq->bufs[tail_idx];
 345                 m = (struct rte_mbuf *)(buf->mb);
 346                 if (likely(m->pool == pool)) {
 347                         free[nb_free++] = m;
 348                 } else {
 349                         rte_mempool_put_bulk(pool, (void *)free, nb_free);
 350                         free[0] = m;
 351                         nb_free = 1;
 352                         pool = m->pool;
 353                 }
 354                 tail_idx = enic_ring_incr(desc_count, tail_idx);
 355                 buf->mb = NULL;
 356         }
 357
 358         rte_mempool_put_bulk(pool, (void **)free, nb_free);
 359
 360         wq->tail_idx = tail_idx;
 361         wq->ring.desc_avail += nb_to_free;
 362 }
 363
 364 unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
 365 {
 366         u16 completed_index;
 367
 368         completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
 369
 370         if (wq->last_completed_index != completed_index) {
 371                 enic_free_wq_bufs(wq, completed_index);
 372                 wq->last_completed_index = completed_index;
 373         }
 374         return 0;
 375 }
 376
 377 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 378         uint16_t nb_pkts)
 379 {
 380         uint16_t index;
 381         unsigned int pkt_len, data_len;
 382         unsigned int nb_segs;
 383         struct rte_mbuf *tx_pkt;
 384         struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
 385         struct enic *enic = vnic_dev_priv(wq->vdev);
 386         unsigned short vlan_id;
 387         unsigned short ol_flags;
 388         unsigned int wq_desc_avail;
 389         int head_idx;
 390         struct vnic_wq_buf *buf;
 391         unsigned int hw_ip_cksum_enabled;
 392         unsigned int desc_count;
 393         struct wq_enet_desc *descs, *desc_p, desc_tmp;
 394         uint16_t mss;
 395         uint8_t vlan_tag_insert;
 396         uint8_t eop;
 397         uint64_t bus_addr;
 398
 399         enic_cleanup_wq(enic, wq);
 400         wq_desc_avail = vnic_wq_desc_avail(wq);
 401         head_idx = wq->head_idx;
 402         desc_count = wq->ring.desc_count;
 403
 404         nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
 405
 406         hw_ip_cksum_enabled = enic->hw_ip_checksum;
 407         for (index = 0; index < nb_pkts; index++) {
 408                 tx_pkt = *tx_pkts++;
 409                 nb_segs = tx_pkt->nb_segs;
 410                 if (nb_segs > wq_desc_avail) {
 411                         if (index > 0)
 412                                 goto post;
 413                         goto done;
 414                 }
 415
 416                 pkt_len = tx_pkt->pkt_len;
 417                 data_len = tx_pkt->data_len;
 418                 vlan_id = tx_pkt->vlan_tci;
 419                 ol_flags = tx_pkt->ol_flags;
 420
 421                 mss = 0;
 422                 vlan_tag_insert = 0;
 423                 bus_addr = (dma_addr_t)
 424                            (tx_pkt->buf_physaddr + tx_pkt->data_off);
 425
 426                 descs = (struct wq_enet_desc *)wq->ring.descs;
 427                 desc_p = descs + head_idx;
 428
 429                 eop = (data_len == pkt_len);
 430
 431                 if (ol_flags & PKT_TX_VLAN_PKT)
 432                         vlan_tag_insert = 1;
 433
 434                 if (hw_ip_cksum_enabled && (ol_flags & PKT_TX_IP_CKSUM))
 435                         mss |= ENIC_CALC_IP_CKSUM;
 436
 437                 if (hw_ip_cksum_enabled && (ol_flags & PKT_TX_TCP_UDP_CKSUM))
 438                         mss |= ENIC_CALC_TCP_UDP_CKSUM;
 439
 440                 wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, 0, 0, eop,
 441                                  eop, 0, vlan_tag_insert, vlan_id, 0);
 442
 443                 *desc_p = desc_tmp;
 444                 buf = &wq->bufs[head_idx];
 445                 buf->mb = (void *)tx_pkt;
 446                 head_idx = enic_ring_incr(desc_count, head_idx);
 447                 wq_desc_avail--;
 448
 449                 if (!eop) {
 450                         for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
 451                             tx_pkt->next) {
 452                                 data_len = tx_pkt->data_len;
 453
 454                                 if (tx_pkt->next == NULL)
 455                                         eop = 1;
 456                                 desc_p = descs + head_idx;
 457                                 bus_addr = (dma_addr_t)(tx_pkt->buf_physaddr
 458                                            + tx_pkt->data_off);
 459                                 wq_enet_desc_enc((struct wq_enet_desc *)
 460                                                  &desc_tmp, bus_addr, data_len,
 461                                                  mss, 0, 0, eop, eop, 0,
 462                                                  vlan_tag_insert, vlan_id, 0);
 463
 464                                 *desc_p = desc_tmp;
 465                                 buf = &wq->bufs[head_idx];
 466                                 buf->mb = (void *)tx_pkt;
 467                                 head_idx = enic_ring_incr(desc_count, head_idx);
 468                                 wq_desc_avail--;
 469                         }
 470                 }
 471         }
 472  post:
 473         rte_wmb();
 474         iowrite32(head_idx, &wq->ctrl->posted_index);
 475  done:
 476         wq->ring.desc_avail = wq_desc_avail;
 477         wq->head_idx = head_idx;
 478
 479         return index;
 480 }
 481
 482