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32 ***************************************************************************/
34 #include "fm10k_common.h"
37 * fm10k_get_bus_info_generic - Generic set PCI bus info
38 * @hw: pointer to hardware structure
40 * Gets the PCI bus info (speed, width, type) then calls helper function to
41 * store this data within the fm10k_hw structure.
43 STATIC s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw)
45 u16 link_cap, link_status, device_cap, device_control;
47 DEBUGFUNC("fm10k_get_bus_info_generic");
49 /* Get the maximum link width and speed from PCIe config space */
50 link_cap = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_LINK_CAP);
52 switch (link_cap & FM10K_PCIE_LINK_WIDTH) {
53 case FM10K_PCIE_LINK_WIDTH_1:
54 hw->bus_caps.width = fm10k_bus_width_pcie_x1;
56 case FM10K_PCIE_LINK_WIDTH_2:
57 hw->bus_caps.width = fm10k_bus_width_pcie_x2;
59 case FM10K_PCIE_LINK_WIDTH_4:
60 hw->bus_caps.width = fm10k_bus_width_pcie_x4;
62 case FM10K_PCIE_LINK_WIDTH_8:
63 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
66 hw->bus_caps.width = fm10k_bus_width_unknown;
70 switch (link_cap & FM10K_PCIE_LINK_SPEED) {
71 case FM10K_PCIE_LINK_SPEED_2500:
72 hw->bus_caps.speed = fm10k_bus_speed_2500;
74 case FM10K_PCIE_LINK_SPEED_5000:
75 hw->bus_caps.speed = fm10k_bus_speed_5000;
77 case FM10K_PCIE_LINK_SPEED_8000:
78 hw->bus_caps.speed = fm10k_bus_speed_8000;
81 hw->bus_caps.speed = fm10k_bus_speed_unknown;
85 /* Get the PCIe maximum payload size for the PCIe function */
86 device_cap = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_DEV_CAP);
88 switch (device_cap & FM10K_PCIE_DEV_CAP_PAYLOAD) {
89 case FM10K_PCIE_DEV_CAP_PAYLOAD_128:
90 hw->bus_caps.payload = fm10k_bus_payload_128;
92 case FM10K_PCIE_DEV_CAP_PAYLOAD_256:
93 hw->bus_caps.payload = fm10k_bus_payload_256;
95 case FM10K_PCIE_DEV_CAP_PAYLOAD_512:
96 hw->bus_caps.payload = fm10k_bus_payload_512;
99 hw->bus_caps.payload = fm10k_bus_payload_unknown;
103 /* Get the negotiated link width and speed from PCIe config space */
104 link_status = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_LINK_STATUS);
106 switch (link_status & FM10K_PCIE_LINK_WIDTH) {
107 case FM10K_PCIE_LINK_WIDTH_1:
108 hw->bus.width = fm10k_bus_width_pcie_x1;
110 case FM10K_PCIE_LINK_WIDTH_2:
111 hw->bus.width = fm10k_bus_width_pcie_x2;
113 case FM10K_PCIE_LINK_WIDTH_4:
114 hw->bus.width = fm10k_bus_width_pcie_x4;
116 case FM10K_PCIE_LINK_WIDTH_8:
117 hw->bus.width = fm10k_bus_width_pcie_x8;
120 hw->bus.width = fm10k_bus_width_unknown;
124 switch (link_status & FM10K_PCIE_LINK_SPEED) {
125 case FM10K_PCIE_LINK_SPEED_2500:
126 hw->bus.speed = fm10k_bus_speed_2500;
128 case FM10K_PCIE_LINK_SPEED_5000:
129 hw->bus.speed = fm10k_bus_speed_5000;
131 case FM10K_PCIE_LINK_SPEED_8000:
132 hw->bus.speed = fm10k_bus_speed_8000;
135 hw->bus.speed = fm10k_bus_speed_unknown;
139 /* Get the negotiated PCIe maximum payload size for the PCIe function */
140 device_control = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_DEV_CTRL);
142 switch (device_control & FM10K_PCIE_DEV_CTRL_PAYLOAD) {
143 case FM10K_PCIE_DEV_CTRL_PAYLOAD_128:
144 hw->bus.payload = fm10k_bus_payload_128;
146 case FM10K_PCIE_DEV_CTRL_PAYLOAD_256:
147 hw->bus.payload = fm10k_bus_payload_256;
149 case FM10K_PCIE_DEV_CTRL_PAYLOAD_512:
150 hw->bus.payload = fm10k_bus_payload_512;
153 hw->bus.payload = fm10k_bus_payload_unknown;
157 return FM10K_SUCCESS;
160 u16 fm10k_get_pcie_msix_count_generic(struct fm10k_hw *hw)
164 DEBUGFUNC("fm10k_get_pcie_msix_count_generic");
166 /* read in value from MSI-X capability register */
167 msix_count = FM10K_READ_PCI_WORD(hw, FM10K_PCI_MSIX_MSG_CTRL);
168 msix_count &= FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK;
170 /* MSI-X count is zero-based in HW */
173 if (msix_count > FM10K_MAX_MSIX_VECTORS)
174 msix_count = FM10K_MAX_MSIX_VECTORS;
180 * fm10k_init_ops_generic - Inits function ptrs
181 * @hw: pointer to the hardware structure
183 * Initialize the function pointers.
185 s32 fm10k_init_ops_generic(struct fm10k_hw *hw)
187 struct fm10k_mac_info *mac = &hw->mac;
189 DEBUGFUNC("fm10k_init_ops_generic");
192 mac->ops.get_bus_info = &fm10k_get_bus_info_generic;
194 /* initialize GLORT state to avoid any false hits */
195 mac->dglort_map = FM10K_DGLORTMAP_NONE;
197 return FM10K_SUCCESS;
201 * fm10k_start_hw_generic - Prepare hardware for Tx/Rx
202 * @hw: pointer to hardware structure
204 * This function sets the Tx ready flag to indicate that the Tx path has
207 s32 fm10k_start_hw_generic(struct fm10k_hw *hw)
209 DEBUGFUNC("fm10k_start_hw_generic");
211 /* set flag indicating we are beginning Tx */
212 hw->mac.tx_ready = true;
214 return FM10K_SUCCESS;
218 * fm10k_disable_queues_generic - Stop Tx/Rx queues
219 * @hw: pointer to hardware structure
220 * @q_cnt: number of queues to be disabled
223 s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt)
228 DEBUGFUNC("fm10k_disable_queues_generic");
230 /* clear tx_ready to prevent any false hits for reset */
231 hw->mac.tx_ready = false;
233 if (FM10K_REMOVED(hw->hw_addr))
234 return FM10K_SUCCESS;
236 /* clear the enable bit for all rings */
237 for (i = 0; i < q_cnt; i++) {
238 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(i));
239 FM10K_WRITE_REG(hw, FM10K_TXDCTL(i),
240 reg & ~FM10K_TXDCTL_ENABLE);
241 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(i));
242 FM10K_WRITE_REG(hw, FM10K_RXQCTL(i),
243 reg & ~FM10K_RXQCTL_ENABLE);
246 FM10K_WRITE_FLUSH(hw);
249 /* loop through all queues to verify that they are all disabled */
250 for (i = 0, time = FM10K_QUEUE_DISABLE_TIMEOUT; time;) {
251 /* if we are at end of rings all rings are disabled */
253 return FM10K_SUCCESS;
255 /* if queue enables cleared, then move to next ring pair */
256 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(i));
257 if (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) {
258 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(i));
259 if (!~reg || !(reg & FM10K_RXQCTL_ENABLE)) {
265 /* decrement time and wait 1 usec */
271 return FM10K_ERR_REQUESTS_PENDING;
275 * fm10k_stop_hw_generic - Stop Tx/Rx units
276 * @hw: pointer to hardware structure
279 s32 fm10k_stop_hw_generic(struct fm10k_hw *hw)
281 DEBUGFUNC("fm10k_stop_hw_generic");
283 return fm10k_disable_queues_generic(hw, hw->mac.max_queues);
287 * fm10k_read_hw_stats_32b - Reads value of 32-bit registers
288 * @hw: pointer to the hardware structure
289 * @addr: address of register containing a 32-bit value
291 * Function reads the content of the register and returns the delta
292 * between the base and the current value.
294 u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,
295 struct fm10k_hw_stat *stat)
297 u32 delta = FM10K_READ_REG(hw, addr) - stat->base_l;
299 DEBUGFUNC("fm10k_read_hw_stats_32b");
301 if (FM10K_REMOVED(hw->hw_addr))
308 * fm10k_read_hw_stats_48b - Reads value of 48-bit registers
309 * @hw: pointer to the hardware structure
310 * @addr: address of register containing the lower 32-bit value
312 * Function reads the content of 2 registers, combined to represent a 48-bit
313 * statistical value. Extra processing is required to handle overflowing.
314 * Finally, a delta value is returned representing the difference between the
315 * values stored in registers and values stored in the statistic counters.
317 STATIC u64 fm10k_read_hw_stats_48b(struct fm10k_hw *hw, u32 addr,
318 struct fm10k_hw_stat *stat)
325 DEBUGFUNC("fm10k_read_hw_stats_48b");
327 count_h = FM10K_READ_REG(hw, addr + 1);
329 /* Check for overflow */
332 count_l = FM10K_READ_REG(hw, addr);
333 count_h = FM10K_READ_REG(hw, addr + 1);
334 } while (count_h != count_tmp);
336 delta = ((u64)(count_h - stat->base_h) << 32) + count_l;
337 delta -= stat->base_l;
339 return delta & FM10K_48_BIT_MASK;
343 * fm10k_update_hw_base_48b - Updates 48-bit statistic base value
344 * @stat: pointer to the hardware statistic structure
345 * @delta: value to be updated into the hardware statistic structure
347 * Function receives a value and determines if an update is required based on
348 * a delta calculation. Only the base value will be updated.
350 STATIC void fm10k_update_hw_base_48b(struct fm10k_hw_stat *stat, u64 delta)
352 DEBUGFUNC("fm10k_update_hw_base_48b");
357 /* update lower 32 bits */
358 delta += stat->base_l;
359 stat->base_l = (u32)delta;
361 /* update upper 32 bits */
362 stat->base_h += (u32)(delta >> 32);
366 * fm10k_update_hw_stats_tx_q - Updates TX queue statistics counters
367 * @hw: pointer to the hardware structure
368 * @q: pointer to the ring of hardware statistics queue
369 * @idx: index pointing to the start of the ring iteration
371 * Function updates the TX queue statistics counters that are related to the
374 STATIC void fm10k_update_hw_stats_tx_q(struct fm10k_hw *hw,
375 struct fm10k_hw_stats_q *q,
378 u32 id_tx, id_tx_prev, tx_packets;
381 DEBUGFUNC("fm10k_update_hw_stats_tx_q");
383 /* Retrieve TX Owner Data */
384 id_tx = FM10K_READ_REG(hw, FM10K_TXQCTL(idx));
386 /* Process TX Ring */
388 tx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPTC(idx),
392 tx_bytes = fm10k_read_hw_stats_48b(hw,
396 /* Re-Check Owner Data */
398 id_tx = FM10K_READ_REG(hw, FM10K_TXQCTL(idx));
399 } while ((id_tx ^ id_tx_prev) & FM10K_TXQCTL_ID_MASK);
401 /* drop non-ID bits and set VALID ID bit */
402 id_tx &= FM10K_TXQCTL_ID_MASK;
403 id_tx |= FM10K_STAT_VALID;
405 /* update packet counts */
406 if (q->tx_stats_idx == id_tx) {
407 q->tx_packets.count += tx_packets;
408 q->tx_bytes.count += tx_bytes;
411 /* update bases and record ID */
412 fm10k_update_hw_base_32b(&q->tx_packets, tx_packets);
413 fm10k_update_hw_base_48b(&q->tx_bytes, tx_bytes);
415 q->tx_stats_idx = id_tx;
419 * fm10k_update_hw_stats_rx_q - Updates RX queue statistics counters
420 * @hw: pointer to the hardware structure
421 * @q: pointer to the ring of hardware statistics queue
422 * @idx: index pointing to the start of the ring iteration
424 * Function updates the RX queue statistics counters that are related to the
427 STATIC void fm10k_update_hw_stats_rx_q(struct fm10k_hw *hw,
428 struct fm10k_hw_stats_q *q,
431 u32 id_rx, id_rx_prev, rx_packets, rx_drops;
434 DEBUGFUNC("fm10k_update_hw_stats_rx_q");
436 /* Retrieve RX Owner Data */
437 id_rx = FM10K_READ_REG(hw, FM10K_RXQCTL(idx));
439 /* Process RX Ring */
441 rx_drops = fm10k_read_hw_stats_32b(hw, FM10K_QPRDC(idx),
444 rx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPRC(idx),
448 rx_bytes = fm10k_read_hw_stats_48b(hw,
452 /* Re-Check Owner Data */
454 id_rx = FM10K_READ_REG(hw, FM10K_RXQCTL(idx));
455 } while ((id_rx ^ id_rx_prev) & FM10K_RXQCTL_ID_MASK);
457 /* drop non-ID bits and set VALID ID bit */
458 id_rx &= FM10K_RXQCTL_ID_MASK;
459 id_rx |= FM10K_STAT_VALID;
461 /* update packet counts */
462 if (q->rx_stats_idx == id_rx) {
463 q->rx_drops.count += rx_drops;
464 q->rx_packets.count += rx_packets;
465 q->rx_bytes.count += rx_bytes;
468 /* update bases and record ID */
469 fm10k_update_hw_base_32b(&q->rx_drops, rx_drops);
470 fm10k_update_hw_base_32b(&q->rx_packets, rx_packets);
471 fm10k_update_hw_base_48b(&q->rx_bytes, rx_bytes);
473 q->rx_stats_idx = id_rx;
477 * fm10k_update_hw_stats_q - Updates queue statistics counters
478 * @hw: pointer to the hardware structure
479 * @q: pointer to the ring of hardware statistics queue
480 * @idx: index pointing to the start of the ring iteration
481 * @count: number of queues to iterate over
483 * Function updates the queue statistics counters that are related to the
486 void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,
491 DEBUGFUNC("fm10k_update_hw_stats_q");
493 for (i = 0; i < count; i++, idx++, q++) {
494 fm10k_update_hw_stats_tx_q(hw, q, idx);
495 fm10k_update_hw_stats_rx_q(hw, q, idx);
500 * fm10k_unbind_hw_stats_q - Unbind the queue counters from their queues
501 * @hw: pointer to the hardware structure
502 * @q: pointer to the ring of hardware statistics queue
503 * @idx: index pointing to the start of the ring iteration
504 * @count: number of queues to iterate over
506 * Function invalidates the index values for the queues so any updates that
507 * may have happened are ignored and the base for the queue stats is reset.
509 void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count)
513 for (i = 0; i < count; i++, idx++, q++) {
520 * fm10k_get_host_state_generic - Returns the state of the host
521 * @hw: pointer to hardware structure
522 * @host_ready: pointer to boolean value that will record host state
524 * This function will check the health of the mailbox and Tx queue 0
525 * in order to determine if we should report that the link is up or not.
527 s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready)
529 struct fm10k_mbx_info *mbx = &hw->mbx;
530 struct fm10k_mac_info *mac = &hw->mac;
531 s32 ret_val = FM10K_SUCCESS;
532 u32 txdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(0));
534 DEBUGFUNC("fm10k_get_host_state_generic");
536 /* process upstream mailbox in case interrupts were disabled */
537 mbx->ops.process(hw, mbx);
539 /* If Tx is no longer enabled link should come down */
540 if (!(~txdctl) || !(txdctl & FM10K_TXDCTL_ENABLE))
541 mac->get_host_state = true;
543 /* exit if not checking for link, or link cannot be changed */
544 if (!mac->get_host_state || !(~txdctl))
547 /* if we somehow dropped the Tx enable we should reset */
548 if (mac->tx_ready && !(txdctl & FM10K_TXDCTL_ENABLE)) {
549 ret_val = FM10K_ERR_RESET_REQUESTED;
553 /* if Mailbox timed out we should request reset */
555 ret_val = FM10K_ERR_RESET_REQUESTED;
559 /* verify Mailbox is still valid */
560 if (!mbx->ops.tx_ready(mbx, FM10K_VFMBX_MSG_MTU))
563 /* interface cannot receive traffic without logical ports */
564 if (mac->dglort_map == FM10K_DGLORTMAP_NONE) {
565 if (mac->ops.request_lport_map)
566 ret_val = mac->ops.request_lport_map(hw);
571 /* if we passed all the tests above then the switch is ready and we no
572 * longer need to check for link
574 mac->get_host_state = false;
577 *host_ready = !mac->get_host_state;