1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2013 - 2015 Intel Corporation
5 #ifndef _FM10K_OSDEP_H_
6 #define _FM10K_OSDEP_H_
11 #include <rte_atomic.h>
12 #include <rte_byteorder.h>
13 #include <rte_cycles.h>
16 #include "../fm10k_logs.h"
18 /* TODO: this does not look like it should be used... */
19 #define ERROR_REPORT2(v1, v2, v3) do { } while (0)
21 #ifndef BOULDER_RAPIDS_HW
22 #define BOULDER_RAPIDS_HW
26 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
27 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
28 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
29 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
30 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
31 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
32 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
57 /* offsets are WORD offsets, not BYTE offsets */
58 #define FM10K_WRITE_REG(hw, reg, val) \
59 rte_write32((val), ((hw)->hw_addr + (reg)))
61 #define FM10K_READ_REG(hw, reg) rte_read32(((hw)->hw_addr + (reg)))
63 #define FM10K_WRITE_FLUSH(a) FM10K_READ_REG(a, FM10K_CTRL)
65 #define FM10K_PCI_REG(reg) rte_read32(reg)
67 #define FM10K_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
70 #define FM10K_READ_PCI_WORD(hw, reg) 0
72 #define FM10K_WRITE_MBX(hw, reg, value) FM10K_WRITE_REG(hw, reg, value)
73 #define FM10K_READ_MBX(hw, reg) FM10K_READ_REG(hw, reg)
75 #define FM10K_LE16_TO_CPU rte_le_to_cpu_16
76 #define FM10K_LE32_TO_CPU rte_le_to_cpu_32
77 #define FM10K_CPU_TO_LE32 rte_cpu_to_le_32
78 #define FM10K_CPU_TO_LE16 rte_cpu_to_le_16
79 #define le16_to_cpu rte_le_to_cpu_16
81 #define FM10K_RMB rte_rmb
82 #define FM10K_WMB rte_wmb
84 #define usec_delay rte_delay_us
86 #define FM10K_REMOVED(hw_addr) (!(hw_addr))
88 #ifndef FM10K_IS_ZERO_ETHER_ADDR
89 /* make certain address is not 0 */
90 #define FM10K_IS_ZERO_ETHER_ADDR(addr) \
91 (!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5]))
94 #ifndef FM10K_IS_MULTICAST_ETHER_ADDR
95 #define FM10K_IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1)
98 #ifndef FM10K_IS_VALID_ETHER_ADDR
99 /* make certain address is not multicast or 0 */
100 #define FM10K_IS_VALID_ETHER_ADDR(addr) \
101 (!FM10K_IS_MULTICAST_ETHER_ADDR(addr) && !FM10K_IS_ZERO_ETHER_ADDR(addr))
105 #define do_div(n, base) ({\
110 /* DPDK can't access IOMEM directly */
111 #ifndef FM10K_WRITE_SW_REG
112 #define FM10K_WRITE_SW_REG(v1, v2, v3) do { } while (0)
115 #ifndef fm10k_read_reg
116 #define fm10k_read_reg FM10K_READ_REG
119 #define FM10K_INTEL_VENDOR_ID 0x8086
120 #define FM10K_DMA_CTRL_MINMSS_SHIFT 9
121 #define FM10K_EICR_PCA_FAULT 0x00000001
122 #define FM10K_EICR_THI_FAULT 0x00000004
123 #define FM10K_EICR_FUM_FAULT 0x00000020
124 #define FM10K_EICR_SRAMERROR 0x00000400
125 #define FM10K_SRAM_IP 0x13003
126 #define FM10K_RXINT_TIMER_SHIFT 8
127 #define FM10K_TXINT_TIMER_SHIFT 8
128 #define FM10K_RXD_PKTTYPE_MASK 0x03F0
129 #define FM10K_RXD_PKTTYPE_SHIFT 4
131 #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */
132 #define FM10K_RXD_STATUS_HBO 0x0400 /* header buffer overrun */
134 #define FM10K_TSO_MINMSS \
135 (FM10K_DMA_CTRL_MINMSS_64 >> FM10K_DMA_CTRL_MINMSS_SHIFT)
136 #define FM10K_TSO_MIN_HEADERLEN 54
137 #define FM10K_TSO_MAX_HEADERLEN 192
139 #endif /* _FM10K_OSDEP_H_ */