1 /*******************************************************************************
3 Copyright (c) 2013-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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32 ***************************************************************************/
34 #ifndef _FM10K_OSDEP_H_
35 #define _FM10K_OSDEP_H_
39 #include <rte_atomic.h>
40 #include <rte_byteorder.h>
41 #include <rte_cycles.h>
44 #include "../fm10k_logs.h"
46 /* TODO: this does not look like it should be used... */
47 #define ERROR_REPORT2(v1, v2, v3) do { } while (0)
49 #ifndef BOULDER_RAPIDS_HW
50 #define BOULDER_RAPIDS_HW
54 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
55 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
56 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
57 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
58 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
59 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
60 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
92 /* offsets are WORD offsets, not BYTE offsets */
93 #define FM10K_WRITE_REG(hw, reg, val) \
94 rte_write32((val), ((hw)->hw_addr + (reg)))
96 #define FM10K_READ_REG(hw, reg) rte_read32(((hw)->hw_addr + (reg)))
98 #define FM10K_WRITE_FLUSH(a) FM10K_READ_REG(a, FM10K_CTRL)
100 #define FM10K_PCI_REG(reg) rte_read32(reg)
102 #define FM10K_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
104 /* not implemented */
105 #define FM10K_READ_PCI_WORD(hw, reg) 0
107 #define FM10K_WRITE_MBX(hw, reg, value) FM10K_WRITE_REG(hw, reg, value)
108 #define FM10K_READ_MBX(hw, reg) FM10K_READ_REG(hw, reg)
110 #define FM10K_LE16_TO_CPU rte_le_to_cpu_16
111 #define FM10K_LE32_TO_CPU rte_le_to_cpu_32
112 #define FM10K_CPU_TO_LE32 rte_cpu_to_le_32
113 #define FM10K_CPU_TO_LE16 rte_cpu_to_le_16
114 #define le16_to_cpu rte_le_to_cpu_16
116 #define FM10K_RMB rte_rmb
117 #define FM10K_WMB rte_wmb
119 #define usec_delay rte_delay_us
121 #define FM10K_REMOVED(hw_addr) (!(hw_addr))
123 #ifndef FM10K_IS_ZERO_ETHER_ADDR
124 /* make certain address is not 0 */
125 #define FM10K_IS_ZERO_ETHER_ADDR(addr) \
126 (!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5]))
129 #ifndef FM10K_IS_MULTICAST_ETHER_ADDR
130 #define FM10K_IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1)
133 #ifndef FM10K_IS_VALID_ETHER_ADDR
134 /* make certain address is not multicast or 0 */
135 #define FM10K_IS_VALID_ETHER_ADDR(addr) \
136 (!FM10K_IS_MULTICAST_ETHER_ADDR(addr) && !FM10K_IS_ZERO_ETHER_ADDR(addr))
140 #define do_div(n, base) ({\
145 /* DPDK can't access IOMEM directly */
146 #ifndef FM10K_WRITE_SW_REG
147 #define FM10K_WRITE_SW_REG(v1, v2, v3) do { } while (0)
150 #ifndef fm10k_read_reg
151 #define fm10k_read_reg FM10K_READ_REG
154 #define FM10K_INTEL_VENDOR_ID 0x8086
155 #define FM10K_DMA_CTRL_MINMSS_SHIFT 9
156 #define FM10K_EICR_PCA_FAULT 0x00000001
157 #define FM10K_EICR_THI_FAULT 0x00000004
158 #define FM10K_EICR_FUM_FAULT 0x00000020
159 #define FM10K_EICR_SRAMERROR 0x00000400
160 #define FM10K_SRAM_IP 0x13003
161 #define FM10K_RXINT_TIMER_SHIFT 8
162 #define FM10K_TXINT_TIMER_SHIFT 8
163 #define FM10K_RXD_PKTTYPE_MASK 0x03F0
164 #define FM10K_RXD_PKTTYPE_SHIFT 4
166 #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */
167 #define FM10K_RXD_STATUS_HBO 0x0400 /* header buffer overrun */
169 #define FM10K_TSO_MINMSS \
170 (FM10K_DMA_CTRL_MINMSS_64 >> FM10K_DMA_CTRL_MINMSS_SHIFT)
171 #define FM10K_TSO_MIN_HEADERLEN 54
172 #define FM10K_TSO_MAX_HEADERLEN 192
174 #endif /* _FM10K_OSDEP_H_ */